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path: root/drivers/gpu/nvgpu/clk/clk.c
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* gpu: nvgpu: clear cmd bufferThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | Clear command buffer before setting up the command. Fixes PMU crash on rapid perf events. Bug 2331655 Change-Id: Ic0661cc8fef4b744f15495ab16ddff85b4d7dec6 Reviewed-on: https://git-master.nvidia.com/r/1811245 Reviewed-by: David Jarrett <djarrett@nvidia.com> Tested-by: David Jarrett <djarrett@nvidia.com> Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add GV10x perf eventVaikundanathan S2018-09-20
| | | | | | | | | | | | | | | In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.hddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | Update the location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/boardobj/ nvgpu/clk/ nvgpu/lpwr/ nvgpu/perf/ nvgpu/pmgr/ nvgpu/pstate/ nvgpu/therm/ nvgpu/volt/ Jira NVGPU-597 Change-Id: I5d9e74ae2f1a646087f15a5872daf9017c1580a9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822741 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clk: Fix MISRA 15.6 violationsSrirangan2018-09-05
| | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I228f04adea809e1dd4e6826bf1a04f051a533102 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796831 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gp106 specific clk_arbiter code into HALDebarshi Dutta2018-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, clock arbiter code is extensively using dgpu specific implementation. This patch restructures the clk_arbiter code and moves gp106 specific code into HAL. Following changes are made in this patch 1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e. g->ops.clk.clk_domain_get_f_points. 2) moved nvgpu_clk_arb_change_vf_point and other related static functions to clk_arb_gp106.c. 3) Instead of only checking if get_arbiter_clk_domain is empty, a check for support_clk_freq_controller is also added. This is to enable the clk_arbiter based on support from both the OS and the chips. Bug 2061372 Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774279 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused variables in clkKonsta Holtta2018-06-15
| | | | | | | | | | | | | Delete a couple of unused struct pmu_msg locals from clk.c. Change-Id: Idc7b7e4d18eefb12c4b5c0ebb852f74f721fd0fc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749927 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: effective freq load changesVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | | Read clk frequency through PMU RPC Bug 200399373 Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701276 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set gv10x boot clockVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | - Set gv10x boot gpcclk to 952 MHz - Created ops to set gv10x boot gpcclk instead of using clk arbiter to set clocks Bug 200399373 Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700788 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cleanup more set but unused variablesAlex Waterman2018-03-30
| | | | | | | | | | | | | | | | This time they were largely located in the various common directories. JIRA NVGPU-525 Change-Id: I3a6d523b060a0c6761b227267890298c6d2fb19f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673820 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Selectively disable/enable CFCTejal Kudav2017-09-27
| | | | | | | | | | | | | | | | | | clk_pmu_freq_controller_load used the default mask and affected all the clock frequency controllers (CFC) which had their bits set in the mask. We wish to enable/disable the CFCs in isolation through debugfs. So we add a parameter(bit_idx) to the function which will help affect only one CFC at a time JIRA DNVGPU-207 DEPENDS ON: <http://git-master/r/1563302> Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563303 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: moved & renamed "struct pmu_gk20a"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | | | | | | | | | - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix error for static code analysisVijayakumar2017-05-02
| | | | | | | | | | | | | | | | | | use memset to fill structures with zero instead of assigning zero. mark functions local to the file as static fixing errors in clk, perf and therm modules. Bug 200299572 Change-Id: I0470298803c35b6faed2edc2a0c1dbf0e47e842e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1472940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clk: Use new error macrosTerje Bergstrom2017-04-07
| | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I58bb9e2fb7e5b18f74fbb92b70150cce97968fc3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457347 Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpuMahantesh Kumbar2017-02-10
| | | | | | | | | | | | | | | | | | Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder to support cross platform feature implementation. Made changes to files which accessed “include pmuif/*” to reflect pmuif/* movement changes. Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files. Jira NVGPU-19 Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1299823 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix fll regime checkVijayakumar2016-12-27
| | | | | | | | | | | | | | For target clocks >= FFR cutoff clock use FR, else use FFR. JIRA DNVGPU-180 Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1249041 (cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11) Reviewed-on: http://git-master/r/1270883 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add clock freq controller supportVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-170 1) Add clock frequency controller VBIOS structure definitions 2) Parse VBIOS tables and build boardobj structures for clock frequency controller. 3) send clock frequency controller data structures to PMU 4) implement public function to send load/unload command to pmu to enable/disable clock frequency controller support Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07) Reviewed-on: http://git-master/r/1270897 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: p-state bound arbiterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modification of the ARBITER clocks to be P-State aware Up to now the arbiter just considered the whole range of the GPC and MCLK domains, which could end up on illegal combinations of MCLK, GPC2CLK, and set the SYSCLK and XBARCLK domains below their minimum VCO The following has been implemented: (1) Modified VF tables to add which PState are supported on each point. (2) Return and store the current PState on the arbiter state. (3) Modified logic to prevent illegal combinations of MCLK and GPC2CLK. (4) Modified logic to prevent setting VF points for XBAR and SYS domains below VCO limits. (5) Modified voltage calculation to account for increased values of XBAR and SYS on some VF points. (6) Modified arbiter clock target logic to prevent an application that has not requested a particular VF point to set target to default targets. (7) Remove unnecesary mutexes from critical path JIRA DNVGPU-182 JIRA DNVGPU-183 Change-Id: I3d1c30903278f848681b8da833a867835acc99bb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1247937 (cherry picked from commit b8bcc07eb3b5b70ec1ee19ace237df99d6170138) Reviewed-on: http://git-master/r/1268063 Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp106: Expose the boot max freqTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | Expose the currently hard coded boot frequency, which is at the same time the max frequency. We use it for filling in GPU characteristics. Bug 200251486 Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252906 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Tested-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix sram rail volt calculationVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-120 SRAM rail voltage needs to be picked up from SRAM index of VF entries in CLK prog table. Change-Id: Iabfff62edeec5aa9c2ead62d6b943fb2ebb952ed Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1227665 (cherry picked from commit 8053260438bc94397b20e74cf18453624ebeb325) Reviewed-on: http://git-master/r/1244664 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: construct/load tabels & set voltageMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | - Read voltage tables from VBIOS & construct then send to PMU. - compare & set voltage based on mclk/gpc2clk clk, take higher voltage between two & set. JIRA DNVGPU-122 Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1224365 (cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c) Reviewed-on: http://git-master/r/1244657 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create function to program coreclkVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-123 now a function can be called with GPC2CLK value It will take care calculating slave clock values and calling VF inject to program clock Made programming of boot clock code to use this newly created function. Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1221976 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235056
* gpu: nvgpu: add function to retrieve clk pointsVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 Function will copy possible clock points for a given master clock domain to pointer passed. pointer with NULL value and count of zero can be passed to query number of clock points for a given domain so that memory can be allocated and function called again to fill clock points Change-Id: Iec6206f23789980036be99793599e934bd221035 Reviewed-on: http://git-master/r/1218912 (cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9) Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1235055 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support to parse VF tableVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 function was added to retrieve V for F or F for V for a given clock domain. Clock domain can be master or slave. F or V can be intermediate point between two successive V or F values in VF table. VF table should be cached before calling this function. A F value below Fmin will return Vmin. F > Fmax will return error A V value above Vmax wil return F max. A V value below Vmin will return error. Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1211234 (cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa) Reviewed-on: http://git-master/r/1235054 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add dGPU clocks supportVijayakumar Subbu2016-12-27
JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 20:20:53 -0400