| Commit message (Collapse) | Author | Age |
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In case of VFE update, schedule work to set P0 clocks.
Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event.
Fixed MISRA issues caused by this excluding external functions and MACROs
Bug 2331655
Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808014
Reviewed-on: https://git-master.nvidia.com/r/1813881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This patch constructs clk_arbiter specific code for gp10b as well as
gv11b and does the necessary plumbing in the clk_arbiter code. The
changes made are as follows.
1) Constructed clk_arb_gp10b.* files which add support for clk_arb
related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb.
This doesn't have support for debugfs nor the VFUpdateEvent yet and
consequently no support for arb->notifications.
2) Added gpcclk specific variables corresponding to every gpc2clk in
a given clk_arb related struct.
3) Linux specific support_clk_freq_controller is assigned true in
platform_gp10b.c and platform_gv11b.c files.
4) Incremented the clk_arb_worker.put atomic variable during
worker_deinit so as to allow the worker thread to be stopped.
5) Added the flag clk_arb_events_supported as part of struct
nvgpu_clk_arb. This flag is used to selectively account for the extra
refcounting present in OS specific code i.e.
nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is
reduced during nvgpu_clk_arb_release_completion_dev.
Bug 2061372
Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774281
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they
donot program any hardware registers. Also as an add-on rename
channel_sync_gk20a.* to channel_sync.* and update the headers
in required files.
2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also,
corresponding syncpt and semaphore versions of the struct alongwith
related methods are renamed by removing "gk20a" from their names and
adding "nvgpu".
3) Add misra-c cleanups
Jira NVGPU-1086
Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812594
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Move implementation of MC HAL to common/mc. Also bump gk20a
implementation to gm20b.
gk20a_mc_boot_0 was used via a HAL, but we have only one possible
implementation. It also has to be anyway called directly to detect
which HALs to assign, so make it a true common function.
mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c
so move it there.
JIRA NVGPU-954
Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813519
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Vidmem size query was in mm_xxx.c. It involves reading a register from
FB, so move the query to FB HAL.
JIRA NVGPU-1063
Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801425
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NVHSCLK registers used by NVLINK IP are part of dev_top
hardware headers. This patch adds "Top" as a separate
unit and exposes HALs to access dev_top registers. The top
unit contains top-level configuration information and any
extra registers or features that do not fit into another block's
feature set.
JIRA NVGPU-1053
JIRA NVGPU-966
Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803632
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add fecs trace debugfs initialization as an os op. The
debugfs nodes are set up for gpu versions which call
gk20a_fecs_trace_init().
JIRA NVGPU-602
Change-Id: I606ec31acbf04f633500be4c342db32f3f537794
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812449
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This migrates the common DMA code (os agnostic) to the
common directory. This new unit will be the common DMA
allocator that lets users allocate SYSMEM, VIDMEM, or
either. Other units will be responsible for actually
handling the mechanics of allocating VIDMEM or SYSMEM.
Also update the names of the DMA related files so that
tmake doesn't complain about duplicate C file names. To
do this call the common DMA file dma.c and prepend the
OS to the other DMA files. So now we have:
common/mm/dma.c
os/posix/posix-dma.c
os/linux/linux-dma.c
JIRA NVGPU-990
Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799807
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Move debugfs related part of pmgr to linux files.
JIRA NVGPU-603
Change-Id: I478491e06e2e7cdbe3826166aafd8491d1e6c1e7
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801086
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Move debugfs related code of therm from common driver to linux
specific part of the driver. gp106_therm_debugfs_init()
is updated to use nvgpu_os_linux_ops.
This also affects gv100 as gp106_therm_debugfs_init is used
for gv100 as well.
JIRA NVGPU-603
Change-Id: Ia293d14599bc0c91fd1e917b5a430bd8f3d96e56
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797906
GVS: Gerrit_Virtual_Submit
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Move linux dependencies and CONFIG_DEBUG_FS to linux specific
code from common driver for gp106 clk debugfs. There is no
code change in functions moved from gp106/clk_gp106.c.
It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs
ops. The linux specific part of nvgpu driver uses this op
to initialize gp106 clk debugfs.
As gv100 also uses gp106 clk debugfs ops, set up os ops for
gv100.
JIRA NVGPU-603
Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797904
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Move all code from fb_gk20a.c to fb_gm20b.c.
Change-Id: I87fbdfee76599e019564d66bf248aaffcf978498
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801422
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debug_clk.c implements clk debugfs of gm20b. Rename the file
to reflect clk debugfs functions implemented for gm20b.
JIRA NVGPU-603
Change-Id: I6ff4b71abe400b8fc2a8d79e12e53e2048ccdc05
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797903
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Currently only cde uses nvgpu_os_linux_ops to set up linux
specific ops. Move nvgpu_os_linux_ops of a gpu to a common
file so that those can be reused for other os ops of that
gpu.
JIRA NVGPU-603
Change-Id: Icf1ff275d3832229137f730fe8183b8015e82673
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797902
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Do a simple rename of channel_gk20a.c to common/fifo/channel.c. Header
cleanup and the like will soon follow. Also rename the os-specific files
to have unique names across directories because tmake requires that.
Jira NVGPU-967
Change-Id: I302bbbbe29735264e832378d444a176a4023e3e1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804608
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
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Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.
JIRA NVGPU-957
Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
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Move implementation of ltc HAL to common/ltc.
JIRA NVGPU-956
Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798461
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- fetch ecc info from RM server and create sysfs nodes
- new file ecc_vgpu.c for platform-independent code
- add 2 new commands: GET_ECC_INFO and GET_ECC_COUNTER_VALUE
JIRA EVLR-2590
Change-Id: I040a9fcd23326e432ca93e9a028319f9c1c570f0
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777428
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Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.
Bump gk20a code to gm20b.
JIRA NVGPU-955
Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
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Move implementation of priv_ring HAL to common/priv_ring. Implement
two new HAL APIs to remove illegal dependencies: enable_priv_ring and
enum_ltc.
As enum_ltc can be implemented only gm20b onwards, bump gk20a
implementation to base on gm20b.
JIRA NVGPU-964
Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797025
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Move implementation of xve HAL to common/xve.
JIRA NVGPU-959
Change-Id: I27dba43253e3aa8fd11229a9c4fad97aa5cf0b59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796147
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CBC base needs to be aligned to 64KB. On Linux this is
achieved making compbit backing size multiple of 64KB.
However QNX nvmap alloc function does not allocate
memory aligned to requested size and needs to overallocate
to satisfy alignment requirement. Make cbc alloc function OS
specific to be able to modify QNX code.
Also align cbc base address to 64KB before writing to CBC BASE
register.
Bug 200426427
Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36)
Reviewed-on: https://git-master.nvidia.com/r/1786046
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ce2.c is free of all Linux'isms and can be moved to
the common code, so that it can be used by other
OS'es.
VQRM-3705
Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792100
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-Renamed "struct pmu_queue" to "struct
nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
moved to new file falcon_queue.c
-Created ops for queue functions in struct
nvgpu_falcon_queue to support different queue
types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
to add engine specific queue functionality & assigned
correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
struct pmu_queue & calling queue functions using
nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
"struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
& also for functions gk20a_pmu_queue_head()/
gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c
Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
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Added debugfs node under ltc directory with name:
intr_illegal_compstat_enable
Enabling/disabling of ltc_illegal_compstat intr is
possible through debugfs node.
Since ltc state is lost with rail gate, this setting is
cached and will be populated during ltc initialization.
Bug 2099406
Change-Id: I4bf62228dfd2bbb94f87f923f9f4f6e5ad0b07f0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774683
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- create common file common/ecc.c which include common functions for add
ecc counters and remove counters.
- common code will create a list of all counter which make it easier to
iterate all counters.
- Add chip specific file for adding ecc counters.
- add linux specific file os/linux/ecc_sysfs.c to export counters to
sysfs.
- remove obsolete code
- MISRA violation for using snprintf is not solved, tracking with
jira NVGPU-859
Jira NVGPUT-115
Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763536
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LTC register write is followed by a register read
and if data doesn't match code will report the error.
Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.
nvgpu_writel_check function write and read back and
compare the data.
Bug 2039150
Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
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Move all FB HAL implementations to common/fb.
JIRA NVGPU-596
Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769724
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We do not utilize or test replayable page faults in Pascal. Remove the
code related to that.
JIRA NVGPU-714
Change-Id: I2415bde347f8b018ebf99c3f9038d47c649d9464
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769697
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Rename os/linux/vidmem.c to os/linux/dmabuf_vidmem.c. The code is
mainly dealing with interfacing with Linux dmabuf framework and its
responsibilities got confused with common/mm/vidmem.c.
Also move the header include/nvgpu/linux/vidmem.h to
os/linux/dmabuf_vidmem.h. It does not expose any interface to outside
Linux code.
Change-Id: I2cb1057a8934d5cb5c5860023aa12f8f048a6684
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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To finish OS unification of the submit path, move the
gk20a_submit_channel_gpfifo* functions to a file that's accessible also
outside Linux code.
Also change the prefix of the submit functions from gk20a_ to nvgpu_.
Jira NVGPU-705
Change-Id: I8ca355d1eb69771fb016c7a21fc7f102ca7967d7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760421
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add bios debugfs node to get current VBIOS version.
Bug 2113607
Change-Id: I8d52b651f923080000a4ad529e7efa05667563ba
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743030
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move all Linux source code files to drivers/gpu/nvgpu/os/linux from
drivers/gpu/nvgpu/common/linux. This changes the meaning of common
to be OS independent.
JIRA NVGPU-598
JIRA NVGPU-601
Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747714
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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To make ecc sysfs related code reusable, move it to
a seprate file. This allows possible optimizations
with localized changes.
There is no change in the code.
Bug 1987855
Change-Id: I69aefb649df628d0c8dad529de6dde07ab4e6009
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735988
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- defined platform agnostic wrapper for mempool
mapping and unmapping.
- used platform agnositc wrapper for device
tree parsing.
- modified css_gr_gk20a to include special
handling incase of rm-server
JIRA: VQRM:3699
Change-Id: I08fd26052edfa1edf45a67be57f7d27c38ad106a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added nvgpu_dt_read_u32_index() for now.
Jira VFND-4870
Change-Id: I3e51c408dfba3864372c515ba5d2c77708a489c8
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683008
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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SW scratch register is in bus register range. Move query of that
register to bus HAL from bios.
JIRA NVGPU-588
Change-Id: I69f35af3d5f8da3550eb68fe7d060a3ec48ce275
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.
JIRA NVGPU-588
Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.
JIRA NVGPU-588
Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to
common code so that pramin_gk20a.[ch] can be deleted.
JIRA NVGPU-588
Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730890
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Removed the reference for $NVGPU/drivers/gpu/nvgpu/common
from Makefile and fixed the include path for the
clockgating headers in HAL files.
Change-Id: I34c179866d28c932501b38184ec18d20dce81480
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gk20a_mm_debugfs_init() used to initialize one mm-specific debugfs knob,
but now that there aren't any, delete the function and the related
files.
Change-Id: Ic3177945bbab501c506b5199b44c87450df75452
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729530
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move implementation of bus HAL to common/bus.
Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726337
GVS: Gerrit_Virtual_Submit
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As part of the MISRA fixes, moving all the
gating_reglist files to common/clock_gating dir,
the new directory structure suggested to follow.
Removed unused gating_reglist files for gk20a
JIRA NVGPU-646
Change-Id: I388855befcf991ee68eeffed10fe9ac456210649
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722330
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Now that clk_arb.c is free of Linux'isms, move
it to the clk/ directory.
Jira VQRM-741
Change-Id: I53298c76f834322aa586781cdfd2e6031f4826a1
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709651
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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sync_gk20a.* files are no longer used by core code and only invoked
from linux specific implementations of the OS_FENCE framework which are
under the common/linux directory. Hence, sync_gk20a.* files are also
moved under common/linux.
JIRA NVGPU-66
Change-Id: If623524611373d2da39b63cfb3c1e40089bf8d22
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1712900
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This patch adapts gk20a_channel_syncpt to use os_fence for post fence
as well as pre-fence(wait) use cases.
Jira NVGPU-66
Change-Id: I49627d1f88d52a53511a02f5de60fed6df8350de
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676631
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This patch constructs an abstraction to hide the sync_fence
functionality from the common code. struct nvgpu_os_fence acts as an
abstraction for struct sync_fence.
struct nvgpu_os_fence consists of an ops structure named nvgpu_os_fence_ops
which contains an API to do pushbuffer programming to generate wait
commands for the fence.
The current implementation of nvgpu only allows for wait method on a
sync_fence which was generated using a similar backend(i.e. either
Nvhost Syncpoints or Semaphores). In this patch, a
generic API is introduced which will decide the type of the underlying
implementation of the struct nvgpu_os_fence at runtime and run the
corresponding wait implementation on it.
This patch changes the channel_sync_gk20a's semaphore specific
implementation to use the abstract API. A subsequent patch will make
the changes for the nvhost_syncpoint based implementations as well.
JIRA NVGPU-66
Change-Id: If6675bfde5885c3d15d2ca380bb6c7c0e240e734
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667218
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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segregated os-agnostic function from linux/sim.c and linux/sim_pci.c
to sim.c and sim_pci.c, while retaining os-specific functions.
renamed all gk20a_* api's to nvgpu_*.
renamed hw_sim_gk20a.h to nvgpu/hw_sim.h
moved hw_sim_pci.h to nvgpu/hw_sim_pci.h
JIRA VQRM-2368
Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702425
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move nvlink endpoint operations to common code. These operations
are invoked when handling nvlink core driver requests.
Jira VQRM-3523
Change-Id: I93024bf88a8caa3765b33c1264dde452c1a85ee3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698686
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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