| Commit message (Collapse) | Author | Age |
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
therm sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527423
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fecs_trace sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527420
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
bus sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514661
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add gv11b implementation of gpu_phys_addr() that checks the t19x
GMMU attributes struct to determine if L3 allocation should be
enabled. If L3 alloc is enabled then a special physical address
bit is set.
Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct
nvgpu_as_map_buffer_ex_args so that User space can add a hint to
allocate buffer in L3 cache
Jira GPUT19X-10
Bug 200279508
Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master/r/1512602
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC
Currently all subcontexts with in a tsg can have only
single address space.
Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for
selecting subctx id by client.
Bug 1842197
Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1511145
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- Added t19x vgpu platform data
- Added basic vgpu HAL for gv11b.
- Added subctx header HAL.
Jira VFND-3796
Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1474729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add new abstraction file common/linux/nvhost_t19x.c
for all nvhost APIs exported from linux/nvhost_t194.h
This file will be compiled only if config
CONFIG_TEGRA_GK20A_NVHOST is set
Export the new headers from file <nvgpu/nvhost_t19x.h>
Also add dummy private header file nvhost_priv_t19x.h
to store definition of private structure nvgpu_nvhost_dev
This file should be deleted when nvgpu-t19x repo
is merged into common nvhost repo
Jira NVGPU-29
Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1493792
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add bus HAL and separate bus related functions from mm_gv11b:
timer access.
Change-Id: I311f258857238233103688fb653d27e4e79005a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323354
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add regops whitelists for gv11b.
JIRA GV11B-35
Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1295401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA GV11B-15
Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1266705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv11b needs atleast one subcontext to submit work. To support
legacy in gv11b, currently main context is always copied into
subcontext0 (veid0) during channel commit instance.
As part of channel commit instance, veid0 for that channel is
created and relevant pdb and context info copied to vedi0.
JIRA GV11B-21
Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1231169
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
Volta GPU series
5) Removed hard coded engine_id logic and
made generic way
6) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156023
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All kernel versions are getting moved inside $TOP/kernel folder.
Changing kernel paths accordingly.
Bug 200190733
Change-Id: I7dc6d1768151977fc60bacae34c2f8d839216351
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/1143388
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.
Bug 1735757
Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1735757
Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1122123
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Since NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL was made mandatory,
kernel does not need to know the details about the PTE kinds
anymore. Thus, we can remove the kind_gk20a.h header and the code
related to kind table setup, as well as simplify buffer mapping code
a bit.
Bug 1902982
Change-Id: Iaf798023c219a64fb0a84da09431c5ce4bc046eb
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560933
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update all Makefiles to make use of the new srctree.$(overlay) variables
to remove hard-coding the path to any overlays.
Bug 1978395
Change-Id: I160efb55536c1d2b1e090895d9d62432a1e4c28c
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593802
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Modify the LTC code to only use a contiguous CompBit Cache (CBC). The
original code had two allocation schemes: "physical" and "virtual" -
what they meant was virtually contiguous or physically contiguous. The
CBC must appear contiguous to the GPU be it either from the IOMMU or
from physical pages allocated contiguously.
This change makes the CBC get allocated with the FORCE_CONTIGUOUS flag
if the GPU is not IOMMU'able. If we can get contiguous mem with the
IOMMU then no need to force the underlying pages to be contiguous.
However, not all GPUs may be IOMMU'able so we do need to handle that
case.
Also delete the gk20a/ltc_gk20a.[ch] code. All that remained in these
files was the CBC alloc functions which were completely chip agnostic.
As a result these functions were consolidated and moved to common/ltc.c.
Bug 2015747
Change-Id: I3f41961b4f94378b954e7502a6b27cf0bc627375
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593666
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Nvgpu submit path has a lot of dependency on Linux framework
e.g. use of copy_from_user, use of structures defined in uapi/nvgpu headers,
dma_buf_* calls for trace support etc
Hence to keep common code independent of Linux code, move submit path to
Linux directory
Move below APIs to common/linux/channel.c
trace_write_pushbuffer()
trace_write_pushbuffer_range()
gk20a_submit_prepare_syncs()
gk20a_submit_append_priv_cmdbuf()
gk20a_submit_append_gpfifo()
gk20a_submit_channel_gpfifo()
Move below APIs to common/linux/ce2.c
gk20a_ce_execute_ops()
Define gk20a_ce_execute_ops() in common/linux/ce2.c, and declare it in
gk20a/ce2_gk20a.h since it is needed in common/mm code too
Each OS needs to implement this API separately
gk20a_channel_alloc_gpfifo() use sizeof(nvgpu_gpfifo) to get size of one gpfifo
entry, but structure nvgpu_gpfifo is linux specific
Define new nvgpu_get_gpfifo_entry_size() in linux specific code and use it
in gk20a_channel_alloc_gpfifo() to get gpfifo entry size
Each OS needs to implement this API separately
Export some APIs from gk20a/ce2_gk20a.h and gk20a/channel_gk20a.h that are
needed in linux code
Jira NVGPU-259
Jira NVGPU-313
Change-Id: I360c6cb8ce4494b1e50c66af334a2a379f0d2dc4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586277
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move gk20a_scale.[ch] to be common/linux/scale.[ch]. The code is
Linux specific, and only referred from Linux specific source files.
Change the license back to GPL.
JIRA NVGPU-259
Change-Id: I89fa905a1fea4f93c826ddfe2ffce34aefc1b0a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588650
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Migrate ctxsw_trace_gk20a.c to common/linux/ctxsw_trace.c. This
has been done becasue the ctxsw tracing code is currently too
tightly tied to the Linux OS due to usage of a couple system calls:
- poll()
- mmap()
And general Linux driver framework code. As a result pulling the
logic out of the FECS tracing code is simply too large a scope for
time time being.
Instead the code was just copied as much as possible. The HAL ops
for the FECS code was hidden behind the FECS tracing config so
that the vm_area_struct is not used when QNX does not define said
config. All other non-HAL functions called by the FECS ctxsw
tracing code ha now also been hidden by this config. This is not
pretty but for the time being it seems like the way to go.
JIRA NVGPU-287
Change-Id: Ib880ab237f4abd330dc66998692c86c4507149c2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update all Kconfig files and Makefiles to rely on the kernel overlay
feature. In particular, don't include any Kconfig files or Makefiles
from other overlays. -I directives in CFLAGS are not yet cleaned up.
Bug 1978395
Change-Id: I449ed2f07949785f2dd90a6833f4d8cd1711519a
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566641
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I08e3ffb6b59ab145588a5ecf81b6c2346a481628
Reviewed-on: http://git-master/r/1175267
Reviewed-on: http://git-master/r/1177292
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1183064
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Implement a bitmap allocator for GPU use. This allocator is useful for
managing memory (or resource) regions where the buddy allocator is not
ideal. Some instances are small regions or where the resource management
must not make calls to the kernel's memory allocation routines (anything
that ultimately calls alloc_page()).
The code path where this avoidance of alloc_page() is most required is
the gpfifo submit path. In order to keep this routine fast and have
predicable time constraints no alloc_page() calls is necessary. The
buddy allocator does not work for this since every time a buddy is
allocated there is the possibility that a pair (or more) buddy structs
have to be made. These allocs could perhaps require a call into
alloc_page() if there is not enouch space in the kmem_cache slab for
the buddy structs.
Change-Id: Ia46fce62d4bdafcebbc153b21b515cb51641d241
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1176446
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Move the buddy allocator implementation to a new file to make the
code more organized. Also, as part of this, commonize some macros
and functions which will be used by future allocator implementations.
Bug 1781897
Change-Id: I1611534d5d872bf3b4677f7a1cc024a94b1c437e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1172116
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Added a dedicated device node to allow an
app manager to control TSG scheduling parameters:
- Get list of TSGs
- Get list of recent TSGs
- Get list of TSGs per pid
- Get TSG current scheduling parameters
- Set TSG timeslice
- Set TSG runlist interleave
Jira VFND-1586
Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1160384
(cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e)
Reviewed-on: http://git-master/r/1167021
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Read video memory size from hardware during initialization for devices
that support it.
JIRA DNVGPU-14
Change-Id: If190f2d89f7148520ee274ca674f972987c8056d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157215
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt handling support
for gm206 GPU family
5) Added generic mechanism to identify the
CE engine pri_base address for gm206
(CE0, CE1 and CE2)
6) Removed hard coded engine_id logic and
made generic way
7) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1155963
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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enable gm204/gm206 GPMU secure boot & build.
JIRA DNVGPU-11
Change-Id: I3502d227d0baad9e3a27f46d1d6b0d2a83503b6c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1156331
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use TEGRA_19x_GPU config instead of ARCH_TEGRA_19x_SOC for
t19x functionality. This config will defined only when gpu
repository for t19x is available.
Bug 1757988
Change-Id: I53421f31cbed49a2fb24085c150599c78b8158c0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1158183
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Include chip specific makefiles, only if they are present
in current source tree.
Bug 1757988
Change-Id: I60a468bce6e0d20459aa643ccbce9bacbcd163bf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1154761
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- make tsg_gk20a.c call HAL for enable/disable channels
- add preempt_tsg HAL callbacks
- add tsg bind/unbind channel HAL callbacks
- add according tsg callbacks for vgpu
Bug 1702773
JIRA VFND-1003
Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144932
(cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7)
Reviewed-on: http://git-master/r/1126942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All kernel versions are getting moved inside $TOP/kernel folder.
Changing kernel paths accordingly.
Bug 200190733
Change-Id: I0ed2aa6d4ae75e6fc2c3adf4ae541ecb5f4fb9a9
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/1143380
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sridhar Lavu <slavu@nvidia.com>
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compiling kernel with clang pointed out below issues in nvgpu.
Fixing them.
gr_gk20a.c:1185:12: error: stack frame size of 3152 bytes in
function 'gr_gk20a_setup_alpha_beta_tables'
cde_gk20a.c:1376:22: error: duplicate 'const' declaration
cde_gk20a.c:1377:22: error: duplicate 'const' declaration
cde_gk20a.c:1378:22: error: duplicate 'const' declaration
ctxsw_trace_gk20a.c:71:19: error: unused function 'ring_space'
platform_gk20a_tegra.c:55:19: error: unused function 'pmc_read'
platform_gk20a_tegra.c:60:20: error: unused function 'pmc_write'
bug 1745660
Change-Id: I8cd4383cb898307bbeb162ca00b3e20d04de2c90
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1150486
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for chips gm204 and gm206. Adds also support for reading
VBIOS and booting devinit and pre-os images on PMU.
Change-Id: I4824b44245611e5379ace62793cc37158048f432
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Add support for probing PCIe graphics cards.
JIRA DNVGPU-7
Change-Id: Iad3d31a1dc0ca6575d8a9916857022cac9181948
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1127684
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Add build and gpu framework support for t19x.
Bug 1735757
Change-Id: I4b7c6468871ca27412a6f9be20f744bc730b4142
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1122093
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Part of moving the nvgpu driver out of the common kernel is moving the T18x
part of the nvgpu driver out of kernel-t18x. So, update the Makefile to
replect this change.
bug 200187033
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Change-Id: I97ab32b4c5f8971060b7bfa0aab362ba2fe2eb00
Reviewed-on: http://git-master/r/1119775
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Part of moving the nvgpu driver out of the common kernel is moving the T18x
part of the nvgpu driver out of kernel-t18x. So, update the Makefile to
replect this change.
bug 200187033
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
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The nvgpu driver's headers moved along with the dirver. So, add the new
path to the include search path.
bug 200187033
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
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bug 1648908
This commit adds support for FECS ctxsw tracing. Code is compiled
conditionnaly under CONFIG_GK20_CTXSW_TRACE.
This feature requires an updated FECS ucode that writes one record to a ring
buffer on each context switch. On RM/Kernel side, the GPU driver reads records
from the master ring buffer and generates trace entries into a user-facing
VM ring buffer. For each record in the master ring buffer, RM/Kernel has
to retrieve the vmid+pid of the user process that submitted related work.
Features currently implemented:
- master ring buffer allocation
- debugfs to dump master ring buffer
- FECS record per context switch (with both current and new contexts)
- dedicated device for ctxsw tracing (access to VM ring buffer)
- SOF generation (and access to PTIMER)
- VM ring buffer allocation, and reconfiguration
- enable/disable tracing at user level
- event-based trace filtering
- context_ptr to vmid+pid mapping
- read system call for ctxsw dev
- mmap system call for ctxsw dev (direct access to VM ring buffer)
- poll system call for ctxsw dev
- save/restore register on ELPG/CG6
- separate user ring from FECS ring handling
Features requiring ucode changes:
- enable/disable tracing at FECS level
- actual busy time on engine (bug 1642354)
- master ring buffer threshold interrupt (P1)
- API for GPU to CPU timestamp conversion (P1)
- vmid/pid/uid based filtering (P1)
Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1022737
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Refactor Makefile so that there is only one target.
Bug 1476801
Change-Id: If0fe5f787214c9addd51295355e3ae5606e5e8fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1028349
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Added new RM Server command for regops.
JIRA VFND-1128
Bug 1700139
Change-Id: Ia1cc63e993c29c91f87440c241077fa91edb9e53
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/923235
(cherry picked from commit 7de22e42cfd2e419ad64178b9f1f1ee16273bd03)
Reviewed-on: http://git-master/r/841330
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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Add required fileds and values for thermal slow-down
settings in thermal header file and implemented chip
specific thermal register programming
Reviewed-on: http://git-master/r/822199
(cherry picked from commit 9e8a745b8295af002b9780c83caa8dc7b22cc737)
Change-Id: I016b18ed230fa6c104eada2e166ccd1a5f2ace36
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/823012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add gpu_ops for CDE, and add get_program_numbers function pointer for
determining horizontal and vertical CDE swizzler programs. This allows
different GPUs to have their own specific requirements for choosing
the CDE firmware programs.
Bug 1604102
Change-Id: Ib37c13abb017c8eb1c32adc8cbc6b5984488222e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/784899
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- add hal initializaiton
- create folders vgpu/gk20a and vgpu/gm20b for specific code
Bug 1653185
Change-Id: If94d45e22a1d73d2e4916673736cc29751be4e40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/774148
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Client notification support is now added for the following:
- stalling and non-stalling GR sema release
- non-stalling FIFO channel intr
- non-stalling CE2 nonblockpipe intr
Bug 200097077
Change-Id: Icd3c076d7880e1c9ef1fcc0fc58eed9f23f39277
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/736064
(cherry picked from commit 0585d1f14d5a5ae1ccde8ccb7b7daa5593b3d1bc)
Reviewed-on: http://git-master/r/759824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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That is a kernel supporting code for cyclestats mode E.
Cyclestats mode E implemented following Windows-design in user-space
and required the following operations to be implemented:
- attach a client for shared hardware buffer of device
- detach client from shared hardware buffer
- flush means copy of available data from hardware buffer to private
client buffers according to perfmon IDs assigned for clients
- perfmon IDs management for user-space clients
- a NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT capability added
Bug 1573150
Change-Id: I9e09f0fbb2be5a95c47e6d80a2e23fa839b46f9a
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/740653
(cherry picked from commit 79fe89fd4cea39d8ab9dbef0558cd806ddfda87f)
Reviewed-on: http://git-master/r/753274
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ce2 interrupts enabled only on gk20a and gm20b when
interrupts are handled through hal
Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/677447
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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enables non-blocking interrupts in ce2 all other
ce2 interrupts are cleared and not handled.
bug 200036089
Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/671783
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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