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* gpu: nvgpu: files sim_gk20a.* are changed to sim.*Debarshi Dutta2017-11-30
| | | | | | | | | | | | | | | | | The files sim_gk20a.c and sim_gk20a.h under common/linux/ are renamed to sim.c and sim.h as the suffix gk20a is not needed. JIRA NVGPU-386 Change-Id: I79bbb8e66c4b0cf53f2b1f98a7bed5f682106a0c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606975 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove dependency on linux header for sim_gk20a*Debarshi Dutta2017-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes linux dependencies from sim_gk20a.h under gk20a/sim_gk20a.h. The following changes are made in this patch. 1) Created a linux based structure sim_gk20a_linux that contains a common sim_gk20a struct inside it. The common struct sim_gk20a doesn't contain any linux specific structs. 2) The common struct sim_gk20a contains an added function pointer which is used to invoke gk20a_sim_esc_readl() method. 3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header sim_gk20a.h that contains the definition of struct sim_gk20a_linux. 4) struct gk20a now contains a pointer of sim_gk20a instead of the entire object. The memory for this struct is allocated and initialized during gk20a_init_support() and freed during invocation of gk20_remove_support(). 5) We first obtain the pointer for struct sim_gk20a_linux from the pointer of sim_gk20a using the container_of method in order to work on the struct. JIRA NVGPU-386 Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1603073 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gv11b platform specific file to linuxDeepak Nibade2017-11-27
| | | | | | | | | | | | | | gv11b/platform_gv11b_tegra.c is mostly linux specific so move it to linux specific directory Change-Id: I3e10bafcf672967e35a7955038cd9285b8697a57 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1604283 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add check_priv_security fuse opsSeema Khowala2017-11-22
| | | | | | | | | | | | | | | | | | | | | | | -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove separation of t18x codeTerje Bergstrom2017-11-17
| | | | | | | | | | | Remove separation of t18x specific code and fields and the associated ifdefs. We can build T18x code in always. Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move vgpu code to linuxDeepak Nibade2017-11-17
| | | | | | | | | | | | | | | | | | | | Most of VGPU code is linux specific but lies in common code So until VGPU code is properly abstracted and made os-independent, move all of VGPU code to linux specific directory Handle corresponding Makefile changes Update all #includes to reflect new paths Add GPL license to newly added linux files Jira NVGPU-387 Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599472 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove nvgpu-t19x includesDeepak Nibade2017-11-16
| | | | | | | | | | | | | | | | We no longer use code in nvgpu-t19x or t19x repo, so remove obsolete includes from Makefile Bug 200363166 Change-Id: I29e78931e90e0afffecf756bf7479ed8784dbc25 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599470 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Merge remote-tracking branch 'remotes/origin/dev/linux-nvgpu-t19x' into ↵Deepak Nibade2017-11-16
|\ | | | | | | | | | | | | | | | | linux-nvgpu Bug 200363166 Change-Id: Ic662d7b44b673db28dc0aeba338ae67cf2a43d64 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
| * gpu: nvgpu: vgpu: enable subctx for gv11bThomas Fleury2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add vgpu_gv11b_init_gpu_characteristics() and enable NVGPU_SUPPORT_TSG_SUBCONTEXTS Jira VFND-3797 Jira EVLR-1751 Change-Id: I288ac062e42ec399a302d693471b50b58c9a2653 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1543015 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channelThomas Fleury2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id and runqueu_sel to RM server. Use this command in gv11b's implementation of gops->fifo.tsg_bind_channel. Jira EVLR-1751 Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579840 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * nvgpu-t19x: use kernel overlay featuresStephen Warren2017-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all Kconfig files and Makefiles to rely on the kernel overlay feature. In particular, don't include any Kconfig files or Makefiles from other overlays. -I directives in CFLAGS are not yet cleaned up. Bug 1978395 Change-Id: I16386f7f1e76bd68b55f3128b25eada029ae82c1 Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1571165 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Linux specific GPU characteristics flagsTerje Bergstrom2017-10-26
| | | | | | | | | | | | | | | | | | | | | | | | Make GPU characteristics flags specific to Linux code only. The rest of driver is moved to using nvgpu_is_enabled() API. JIRA NVGPU-259 Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583992 GVS: Gerrit_Virtual_Submit
| * gpu: nvgpu: Add gv10x regops whitelistDavid Nieto2017-10-23
| | | | | | | | | | | | | | | | | | | | | | | | Add regops whitelists for GV100 JIRA: NVGPUGV100-36 Change-Id: Ifeb286e2e8df056ba9afdd32f457bacf1b4813fc Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582835 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: update css opsseshendra Gadagottu2017-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated following hal functions for css gv11b and reused them for gv100: enable_snapshot disable_snapshot check_data_available These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target based on memory aperture used for hwpm inst_block. Bug 200327596 Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1507546 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: fix smid generation of perf tablesDavid Nieto2017-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMID tables were generated according with the local tpc and the pagepool and cb buffers from a different chip and did not take performance in consideration, which made compute kernels hang with CTAs on the fly. This change ensures we are using the right sizes and adds proper enumeration of smids. JIRA: NVGPUGV100-36 bug 2004378 Change-Id: Ic8f50c325d6d6720cca41d9740ae4f5f51e1100a Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581664 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: update dbg opsseshendra Gadagottu2017-10-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated following hal functions for gv11b and reused them for gv100: perfbuffer_enable perfbuffer_disable These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target to sys_ncoh_f(). Bug 200327596 Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1571074 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: Initialize usermode regs for Volta dGPUTerje Bergstrom2017-10-16
| | | | | | | | | | | | | | | | | | | | | | | | Initialize usermode registers also for Volta GPU behind PCIe. Change-Id: Id621a74838839e4d98dfd0828c1ea5a0d54baa2d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579121 Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Tested-by: David Martinez Nieto <dmartineznie@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
| * gpu: nvgpu: gv11b: Abstract IO aperture accessorsTerje Bergstrom2017-10-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement T19x specific usermode aperture initialization functions. Move usermode_regs field to nvgpu_os_linux_t19x, because it is Linux specific. JIRA NVGPU-259 Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569699 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: fix GV100 hal definitionsDavid Nieto2017-10-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: init therm regs for pwr/clkSeema Khowala2017-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
| * gpu: nvgpu: gv11b: Secure boot support.Deepak Goyal2017-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
| * gpu: nvgpu: GV100 supportDavid Nieto2017-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: Reorg therm HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527423 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: Reorg fecs_trace HAL initSunny He2017-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fecs_trace sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527420 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: Reorg bus HAL initSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the bus sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514661 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
| * gpu: nvgpu: add support for L3 cache allocation of buffersDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
| * gpu: nvgpu: gv11b: support for full subcontextseshendra Gadagottu2017-07-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
| * gpu: nvgpu: vgpu: add basic t19x HALsRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added t19x vgpu platform data - Added basic vgpu HAL for gv11b. - Added subctx header HAL. Jira VFND-3796 Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1474729 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: add t19x specific nvhost abstraction filesDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new abstraction file common/linux/nvhost_t19x.c for all nvhost APIs exported from linux/nvhost_t194.h This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Export the new headers from file <nvgpu/nvhost_t19x.h> Also add dummy private header file nvhost_priv_t19x.h to store definition of private structure nvgpu_nvhost_dev This file should be deleted when nvgpu-t19x repo is merged into common nvhost repo Jira NVGPU-29 Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1493792 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| * gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | | | | | | | | | | | | Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: add regops whitelistsseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | | | | | | | | | | | | Add regops whitelists for gv11b. JIRA GV11B-35 Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1295401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: add clock gating prod settingsseshendra Gadagottu2016-12-21
| | | | | | | | | | | | | | | | | | | | JIRA GV11B-15 Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1266705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: legacy support with subcontextseshendra Gadagottu2016-12-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: change kernel pathPritesh Raithatha2016-05-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I7dc6d1768151977fc60bacae34c2f8d839216351 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/1143388 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| * gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
| * gpu: nvgpu: gv11b: added initial source codeSeshendra Gadagottu2016-04-13
| | | | | | | | | | Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: Remove PTE kind logicSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | Since NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL was made mandatory, kernel does not need to know the details about the PTE kinds anymore. Thus, we can remove the kind_gk20a.h header and the code related to kind table setup, as well as simplify buffer mapping code a bit. Bug 1902982 Change-Id: Iaf798023c219a64fb0a84da09431c5ce4bc046eb Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560933 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: use $(srctree.$(overlay))Stephen Warren2017-11-09
| | | | | | | | | | | | | Update all Makefiles to make use of the new srctree.$(overlay) variables to remove hard-coding the path to any overlays. Bug 1978395 Change-Id: I160efb55536c1d2b1e090895d9d62432a1e4c28c Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use only contig CBCsAlex Waterman2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the LTC code to only use a contiguous CompBit Cache (CBC). The original code had two allocation schemes: "physical" and "virtual" - what they meant was virtually contiguous or physically contiguous. The CBC must appear contiguous to the GPU be it either from the IOMMU or from physical pages allocated contiguously. This change makes the CBC get allocated with the FORCE_CONTIGUOUS flag if the GPU is not IOMMU'able. If we can get contiguous mem with the IOMMU then no need to force the underlying pages to be contiguous. However, not all GPUs may be IOMMU'able so we do need to handle that case. Also delete the gk20a/ltc_gk20a.[ch] code. All that remained in these files was the CBC alloc functions which were completely chip agnostic. As a result these functions were consolidated and moved to common/ltc.c. Bug 2015747 Change-Id: I3f41961b4f94378b954e7502a6b27cf0bc627375 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593666 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move submit path to linuxDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvgpu submit path has a lot of dependency on Linux framework e.g. use of copy_from_user, use of structures defined in uapi/nvgpu headers, dma_buf_* calls for trace support etc Hence to keep common code independent of Linux code, move submit path to Linux directory Move below APIs to common/linux/channel.c trace_write_pushbuffer() trace_write_pushbuffer_range() gk20a_submit_prepare_syncs() gk20a_submit_append_priv_cmdbuf() gk20a_submit_append_gpfifo() gk20a_submit_channel_gpfifo() Move below APIs to common/linux/ce2.c gk20a_ce_execute_ops() Define gk20a_ce_execute_ops() in common/linux/ce2.c, and declare it in gk20a/ce2_gk20a.h since it is needed in common/mm code too Each OS needs to implement this API separately gk20a_channel_alloc_gpfifo() use sizeof(nvgpu_gpfifo) to get size of one gpfifo entry, but structure nvgpu_gpfifo is linux specific Define new nvgpu_get_gpfifo_entry_size() in linux specific code and use it in gk20a_channel_alloc_gpfifo() to get gpfifo entry size Each OS needs to implement this API separately Export some APIs from gk20a/ce2_gk20a.h and gk20a/channel_gk20a.h that are needed in linux code Jira NVGPU-259 Jira NVGPU-313 Change-Id: I360c6cb8ce4494b1e50c66af334a2a379f0d2dc4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586277 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gk20a_scale to be Linux onlyTerje Bergstrom2017-11-01
| | | | | | | | | | | | | | | Move gk20a_scale.[ch] to be common/linux/scale.[ch]. The code is Linux specific, and only referred from Linux specific source files. Change the license back to GPL. JIRA NVGPU-259 Change-Id: I89fa905a1fea4f93c826ddfe2ffce34aefc1b0a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588650 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linuxAlex Waterman2017-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate ctxsw_trace_gk20a.c to common/linux/ctxsw_trace.c. This has been done becasue the ctxsw tracing code is currently too tightly tied to the Linux OS due to usage of a couple system calls: - poll() - mmap() And general Linux driver framework code. As a result pulling the logic out of the FECS tracing code is simply too large a scope for time time being. Instead the code was just copied as much as possible. The HAL ops for the FECS code was hidden behind the FECS tracing config so that the vm_area_struct is not used when QNX does not define said config. All other non-HAL functions called by the FECS ctxsw tracing code ha now also been hidden by this config. This is not pretty but for the time being it seems like the way to go. JIRA NVGPU-287 Change-Id: Ib880ab237f4abd330dc66998692c86c4507149c2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586547 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: use kernel overlay featuresStephen Warren2017-10-29
| | | | | | | | | | | | | | | | Update all Kconfig files and Makefiles to rely on the kernel overlay feature. In particular, don't include any Kconfig files or Makefiles from other overlays. -I directives in CFLAGS are not yet cleaned up. Bug 1978395 Change-Id: I449ed2f07949785f2dd90a6833f4d8cd1711519a Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566641 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: rename Makefile to Makefile.nvgpudmitry pervushin2016-07-22
| | | | | | | | | | | | | Bug 1783210 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Change-Id: I08e3ffb6b59ab145588a5ecf81b6c2346a481628 Reviewed-on: http://git-master/r/1175267 Reviewed-on: http://git-master/r/1177292 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1183064
* gpu: nvgpu: Implement a bitmap allocatorAlex Waterman2016-07-19
| | | | | | | | | | | | | | | | | | | | | | Implement a bitmap allocator for GPU use. This allocator is useful for managing memory (or resource) regions where the buddy allocator is not ideal. Some instances are small regions or where the resource management must not make calls to the kernel's memory allocation routines (anything that ultimately calls alloc_page()). The code path where this avoidance of alloc_page() is most required is the gpfifo submit path. In order to keep this routine fast and have predicable time constraints no alloc_page() calls is necessary. The buddy allocator does not work for this since every time a buddy is allocated there is the possibility that a pair (or more) buddy structs have to be made. These allocs could perhaps require a call into alloc_page() if there is not enouch space in the kmem_cache slab for the buddy structs. Change-Id: Ia46fce62d4bdafcebbc153b21b515cb51641d241 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1176446 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Move buddy allocator to new fileAlex Waterman2016-07-19
| | | | | | | | | | | | | Move the buddy allocator implementation to a new file to make the code more organized. Also, as part of this, commonize some macros and functions which will be used by future allocator implementations. Bug 1781897 Change-Id: I1611534d5d872bf3b4677f7a1cc024a94b1c437e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1172116 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: add sched control APIThomas Fleury2016-07-19
| | | | | | | | | | | | | | | | | | | | | | | Added a dedicated device node to allow an app manager to control TSG scheduling parameters: - Get list of TSGs - Get list of recent TSGs - Get list of TSGs per pid - Get TSG current scheduling parameters - Set TSG timeslice - Set TSG runlist interleave Jira VFND-1586 Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1160384 (cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e) Reviewed-on: http://git-master/r/1167021 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: detect vidmem configuration from HWKonsta Holtta2016-06-08
| | | | | | | | | | | | | Read video memory size from hardware during initialization for devices that support it. JIRA DNVGPU-14 Change-Id: If190f2d89f7148520ee274ca674f972987c8056d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157215 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 15:54:02 -0400