| Commit message (Collapse) | Author | Age |
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Compile local t18x code from nvgpu repo (in case
CONFIG_ARCH_TEGRA_18x_SOC config is set)
instead of compiling from $(srctree)/../nvgpu-t18x
Remove Makefile.nvgpu-t18x since this Makefile is
not needed now
Bug 200266498
Change-Id: Ib8ef39be7e948debe0ff895c904a6c370a5711a6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1277119
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-170
1) Add clock frequency controller VBIOS structure definitions
2) Parse VBIOS tables and build boardobj structures for clock frequency
controller.
3) send clock frequency controller data structures to PMU
4) implement public function to send load/unload command to pmu
to enable/disable clock frequency controller support
Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07)
Reviewed-on: http://git-master/r/1270897
GVS: Gerrit_Virtual_Submit
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Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add regops whitelists for gp106. The whitelist is generated, and is the
same for context switched and global registers.
Bug 200239422
Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1243253
(cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db)
Reviewed-on: http://git-master/r/1247645
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The following CL contains the following VBIOS thermal table parsing
and PMU interface support.
1) Thermal device table
2) Thermal channel table
JIRA DNVGPU-130
Change-Id: Ie3abab4bf099a022b1b59db96811c2ed44079519
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1240630
(cherry picked from commit 814962a4be0a8cd0cddc7bc5211c62308ab1fea2)
Reviewed-on: http://git-master/r/1246210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- changes to read voltage tables from VBIOS
& create boardobj then send to pmu
- Rail, Device & Policy objects are read from VBIOS & created boardobjs
- RPC support to load, Set & get voltage.
JIRA DNVGPU-122
Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222774
(cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac)
Reviewed-on: http://git-master/r/1244656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.
JIRA DNVGPU-47
Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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* Parsing of shadow registers from VBIOS
* Partial devinit engine interpreter implementation
JIRA DNVGPU-117
Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1214956
Reviewed-on: http://git-master/r/1237293
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement the basic code to swap between PCIe bus speeds for the GPU.
Other GPUs are not supported yet. Currently the following speeds can
be used:
Gen1 (2.5 MTPS)
Gen2 (5.0 MTPS)
gp106 on DPX2 does not support Gen3.
JIRA DNVGPU-89
Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499
Reviewed-on: http://git-master/r/1218177
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1227925
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added current temperature reading support for gp10x.
JIRA DNVGPU-48
Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1213717
(cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b)
Reviewed-on: http://git-master/r/1234092
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-72
JIRA DNVGPU-73
Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1215915
(cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390)
Reviewed-on: http://git-master/r/1227267
GVS: Gerrit_Virtual_Submit
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FB is enabled in devinit. Skip resetting it in GPU boot.
Bug 1799537
Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208715
(cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698)
Reviewed-on: http://git-master/r/1227265
GVS: Gerrit_Virtual_Submit
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* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-42
Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1205850
(cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114)
Reviewed-on: http://git-master/r/1227257
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-88
Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1202551
(cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108)
Reviewed-on: http://git-master/r/1223854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-9
Change-Id: I22667acfadfcabf79af841ca5389e41d2ac34860
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1206478
(cherry picked from commit 098b932f7633a903c915b1257beb9304735b4113)
Reviewed-on: http://git-master/r/1210288
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use the tegra-path function to compute the path to the t18x project.
This allows the file to be unmodified if the nvmap project is collaped
into the main project.
Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I04e8311fda5ba7984f0985c9abec63beb1b38c74
Reviewed-on: http://git-master/r/1177101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/1178718
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1189710
GVS: Gerrit_Virtual_Submit
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Bug 1783210
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Change-Id: I0ff8be222d18eb2fc81de1b22ae26bd4825e6c97
Reviewed-on: http://git-master/r/1175098
Reviewed-on: http://git-master/r/1178717
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/1183066
GVS: Gerrit_Virtual_Submit
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