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* gpu: nvgpu: Add support for FECS ctxsw tracingAnton Vorontsov2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bug 1648908 This commit adds support for FECS ctxsw tracing. Code is compiled conditionnaly under CONFIG_GK20_CTXSW_TRACE. This feature requires an updated FECS ucode that writes one record to a ring buffer on each context switch. On RM/Kernel side, the GPU driver reads records from the master ring buffer and generates trace entries into a user-facing VM ring buffer. For each record in the master ring buffer, RM/Kernel has to retrieve the vmid+pid of the user process that submitted related work. Features currently implemented: - master ring buffer allocation - debugfs to dump master ring buffer - FECS record per context switch (with both current and new contexts) - dedicated device for ctxsw tracing (access to VM ring buffer) - SOF generation (and access to PTIMER) - VM ring buffer allocation, and reconfiguration - enable/disable tracing at user level - event-based trace filtering - context_ptr to vmid+pid mapping - read system call for ctxsw dev - mmap system call for ctxsw dev (direct access to VM ring buffer) - poll system call for ctxsw dev - save/restore register on ELPG/CG6 - separate user ring from FECS ring handling Features requiring ucode changes: - enable/disable tracing at FECS level - actual busy time on engine (bug 1642354) - master ring buffer threshold interrupt (P1) - API for GPU to CPU timestamp conversion (P1) - vmid/pid/uid based filtering (P1) Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022737 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drm/tegra: Support NVIDIA downstreamArto Merilainen2015-12-04
| | | | | | | | | | | | | | | | | | | This patch modifies TegraDRM to compile on NVIDIA downstream kernel. Currently buffers are pinned to virtual drm device. In upstream this is ok since the buffers will be remapped into the TegraDRM maintained IOMMU domain. However, NVIDIA downstream kernel relies on DMA mapping API and hence requires that the buffers are pinned to the real hardware device. In addition, this patch modifies code to use downstream power-management APIs if the downstream option is enabled. Bug 1698151 Change-Id: I1cb7a1a0ad0ae767c48bfecb608d899e484d6b40 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/823640
* gpu: nvgpu: scaling driver updateSeshendra Gadagottu2015-11-19
| | | | | | | | | | | | | | | | Update scaling driver to support to differnt clock frameworks. Bug 200147662 Reviewed-on: http://git-master/r/816929 (cherry picked from commit cbd4cb575fb2d27870089797ff2a8f22540b87e8) Change-Id: Ie50304b4a593d74bd43b271005cc9616fdb52a6e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/834748 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: Wrappers for upstream host1xArto Merilainen2015-11-19
| | | | | | | | | | | | This patch adds wrappers to use nvhost functions even if the upstream host1x driver was used. In this case the functions are re-routed to corresponding functions in the host1x driver. Bug 1698151 Change-Id: Id49ea78f925e9b14e54e67743cac42610b3ecbeb Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/823638
* gpu: nvgpu: set default channel timeout to 3sDeepak Nibade2015-10-07
| | | | | | | | | | | | | | | We have another constant timeout of 5s for channel watchdog. Hence drop default channel timeout (used for SCHED errors) to 3s so that they both don't conflict with each other Bug 200133289 Change-Id: Ieed675cad462119ff2f1a155a955c8a22cb6c6f8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/810958 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set default timeout to 5sTerje Bergstrom2015-04-04
| | | | | | | | | | 10s is a too long timeout. Set it to 5s. Change-Id: I7093a8ee5bb27828f27cd06a5b3899a4f2df6280 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717042 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: cde: move GK20A_CDE to platform dataKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | CONFIG_GK20A_CDE has not even been used for enabling CDE, just for initializing it at boot time, and it was disabled; initialization has been done late when the engine is first used. Remove the config setting and add information about CDE support in gk20a platform data, forcing the initialization at boot time. Boot time init removes rare race conditions when CDE would be initialized by first user. Bug 200046882 Change-Id: I85d5fb73dc27acbbe203138d25f6e342de030d93 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/562855 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix build without Tegra clk frameworkTerje Bergstrom2015-03-18
| | | | | | | | | | | | Do not build clock code if TEGRA_CLK_FRAMEWORK is not defined. Also make GK20A_DEVFREQ depend on TEGRA_CLK_FRAMEWORK, and build scaling governor only if GK20A_DEVFREQ is enabled. Bug 1567274 Change-Id: I6ea1462e7a110fb46c9d66ceda71167cff19699e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562475
* gpu: nvgpu: Add option to enable GPCPLL NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | Added configuration option to enable GM20b GPCPLL noise aware (NA) mode. In this mode PLL output frequency is automatically adjusted when GM20b voltage is fluctuating. NA mode is disabled by default. Bug 1555318 Change-Id: Ia9741fd02ddacaf4743e5397b729293fa5181f84 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/534079 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: remove config GK20A_PHYS_PAGE_TABLESDeepak Nibade2015-03-18
| | | | | | | | | | | | | | remove config GK20A_PHYS_PAGE_TABLES since all code dependent on this config is now moved to runtime selection Change-Id: I27d2722a9ad91cf4e0537a30943675c9132d6924 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/494499 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: CDE supportArto Merilainen2015-03-18
| | | | | | | | | | | | | | This patch adds support for executing a precompiled GPU program to allow exporting GPU buffers to other graphics units that have color decompression engine (CDE) support. Bug 1409151 Change-Id: Id0c930923f2449b85a6555de71d7ec93eed238ae Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/360418 Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
| | | | | | | | | | | | | | | | | | | GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Allow module buildLauri Peltonen2015-03-18
| | | | | | | | | | | | | This patch makes the necessary modifications to the gk20a driver to allow building it as a module. Bug 1476801 Change-Id: I88c4e1c1867baa1c2d010ac6e0c30bdb5fd63b91 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/380970 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add NVIDIA GPU DriverArto Merilainen2015-03-18
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 19:16:05 -0400