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* gpu: nvgpu: Add RMOS include for the PCI headerAlex Waterman2018-05-01
| | | | | | | | | | | | | | | Necessary in order for QNX to avoid setting __NVGPU_POSIX__ globally. Change-Id: I020609c28766951269371358bae71b0fb4de7803 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703386 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox sizeSeema Khowala2018-05-01
| | | | | | | | | | | | | | fecs_ctxsw_mailbox_size varies per chip. Use hal to get the size. Also dump fecs_ctxsw_status_1 to help debug Bug 2093809 Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698026 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix priv error for slcg regSeema Khowala2018-04-27
| | | | | | | | | | | | | | Bug 2102373 Change-Id: I13a5faa18cf26233eb04ac08d2b8755aeb56ae4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696890 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix per-GPU DMA allocation trackingDeepak Bhosale2018-04-27
| | | | | | | | | | | | | | | | | | | | | | - total DMA memory allocation is currently tracked by adding page aligned size of nvgpu_mem - The sequence is roughly as follows: - total dma memory used += mem->aligned_size - mem->aligned_size = PAGE_ALIGN(size) - In above sequence, nvgpu_mem structure is initially zero when it is added to total dma memory used after which it is assigned page aligned value - This patch fixes total dma memory usage tracking. Change-Id: Ibb879c8d38ae9077c3d198d9bb008a72e9208b4d Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1685312 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to update doorbellDeepak Nibade2018-04-27
| | | | | | | | | | | | | | | | | | | | Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell register and to trigger a runlist scan Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips Jira NVGPUT-18 Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702114 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NULL check for simSeema Khowala2018-04-26
| | | | | | | | | | | | | | | | | sim pointer is not init for non simulation platforms. Change-Id: Ia30e66efbb009293b4e1151c2f1e4ac5d08c3d78 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701681 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: split clk arb codeSourab Gupta2018-04-26
| | | | | | | | | | | | | | | | | Clk arbiter code contains two significant portions - the one which interacts with userspace and is OS specific, and the other which does the heavylifting work which can be moved to the common OS agnostic code. Split the code into two files in prep towards refactoring the clk arbiter. Jira VQRM-3741 Change-Id: I47e2c5b18d86949d02d6963c69c2e2ad161626f7 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699240 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: replace ETIME with ETIMEDOUTRichard Zhao2018-04-25
| | | | | | | | | | | | | | | | ETIME does not exist on integrity. Jira VQRM-2344 Change-Id: I4c9642c5ccf6d5d7ada456716589461b27b72c99 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699843 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move parameter of .vm_bind_channel from as_share to vmRichard Zhao2018-04-25
| | | | | | | | | | | | | | as_share is more os specific and not yet used on other OSes. Jira VQRM-2344 Change-Id: Ie2ed007125400484352fbab602c37a198e8a64ae Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699842 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move mss nvlink credit init to os specific codeRichard Zhao2018-04-25
| | | | | | | | | | | | | | | | | | The code uses ioremap, readl_relaxed/writel_relaxed, which only exists on linux. So move them to linux folder. Also fix build errors on qnx. Jira VQRM-2344 Change-Id: Ide1176d0bf954a804187aa842a6bbfdecbdb0286 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698973 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: save max_comptag_lines in grRichard Zhao2018-04-25
| | | | | | | | | | | | | | | | | max_comptag_lines will be used by RM server to calculate how many lines each guest can get. Jira VQRM-2345 Change-Id: If52208d79617f2f894e48d3a4daec186fda862f1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1695082 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GP106 PMU ucode version updateMahantesh Kumbar2018-04-25
| | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1693596/ - APP_VERSION_GP10X 23732390 to 23913597 Change-Id: Id3ae28325fda8a66b833245113e7010c76ed2750 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1693616 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Port vf_point as per Chips_aVaikundanathan S2018-04-25
| | | | | | | | | | | | | | - Update PMU interface for vf_point Change-Id: I1c457026938025266a9325a93985d81fae3b9fa5 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684286 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update vfe_var interface as per chips_a_23609936Tejal Kudav2018-04-25
| | | | | | | | | | | | | | | | | | | | | Changes made: 1. Fuse value can now be signed or unsigned. A new boolean added to check if the value is signed or not. 2. Masks added for dependent variable and equations 3. Restructing some data structures as per r384 JIRA NVGPUGV100-39 Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1597761 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-04-25
| | | | | | | | | | | | | | | | | | Only for gv11b A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I027f923b63b24bbbc054a7d9a377d757994a07ad Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700981 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to submit and wait for runlistDeepak Nibade2018-04-24
| | | | | | | | | | | | | | | | | | | | | | | | Add below two new HALs gops.fifo.runlist_hw_submit() to submit a new runlist to hardware gops.fifo.runlist_wait_pending() to wait until runlist write is successful Set existing API gk20a_fifo_runlist_wait_pending() to gops.fifo.runlist_wait_pending HAL Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w and set it to gops.fifo.runlist_hw_submit HAL Jira NVGPUT-20 Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700548 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post dbg session header file changePrateek Sethi2018-04-24
| | | | | | | | | | | | | | | | | | | | Need to include bug.h and dbg_gpu_gv11b.h to fix compilation issue at QNX. These changes are required as part of debug session unification. Jira VQRM-2363 Change-Id: I543dab8be16ef6eb321c31f2f262e4dbdeb7dd6a Signed-off-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699079 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Check for all sysmem apertures in GMMUAlex Waterman2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a potential IOMMU'ed GMMU mapping for all SYSMEM buffers inlcuding coherent sysmem. Typically this won't actually happen since IO coherent mappings will also often be accessed over NVLINK which is physically addressed. Also update the comments surrounding this code to take into account the new NVLINK nuances. Since NVLINK buffers are directly mapped even when the IOMMU is enabled this is very deserving of a comment explaining what's going on. Lastly add some simple functions for checking if an nvgpu_mem (or a particular aperture field) is a sysmem aperture. Currently this includes SYSMEM and SYSMEM_COH. JIRA EVLR-2333 Change-Id: I992d3c25d433778eaad9eef338aa5aa42afe597e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cache gpu clk rateArun Kannan2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | Cache the rate used in clk_set_rate(). Return that cached rate on clk_get_rate(), don't read from hardware. This cached rate is used to avoid duplicate requests to clk_set_rate(). Motivation is to support multiple governors for gpu clk. Reading clock from hardware is unreliable in multi-governor situation. Relying on hardware clock value could mislead the kernel gpu governor in its scaling calculations. Bug 2051688 Change-Id: I43fc056eea6f69fe0889c45640fcb892b658071c Signed-off-by: Arun Kannan <akannan@nvidia.com> (cherry picked from commit 7f819a9ba707e6e905168b00b0f3bf6348e86188) Reviewed-on: https://git-master.nvidia.com/r/1662759 Reviewed-on: https://git-master.nvidia.com/r/1668919 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add multiple nvlink recovery modesAdeel Raza2018-04-23
| | | | | | | | | | | | | | | | | | | | Previously all nvlink recovery modes were being grouped under 1 enum. Create an enum for each recovery mode, so the link can go into specific recovery modes. Bug 2090322 Change-Id: I5c2aea758f77b0286e3538424684ddceca98a873 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698799 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Tested-by: Petlozu Pravareshwar <petlozup@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: err if powergate is enabled before hwpm ctxsw mode writeSeema Khowala2018-04-23
| | | | | | | | | | | | | | | If the power gating mode is not disabled before hwpm context switch mode register write, return error. Bug 200379815 Bug 2053656 Bug 2092996 Change-Id: I656f5c38616a4250830779d2bca5e207ff28f3a9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1688219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: vgpu: add support to query rop_l2 en masksAparna Das2018-04-23
| | | | | | | | | | | | | | | | | | Fetch ROP_L2 enable masks in addition to other parameters when guest sends command to query constants. Bug 200401223 Change-Id: Ie386f24caaf7acd1155fc3f2a5e8c1f27016970a Signed-off-by: Aparna Das <aparnad@nvidia.com> (cherry picked from commit a08bb08fb9fff40138d26e5e9bfa21267ca6b6af) Reviewed-on: https://git-master.nvidia.com/r/1694911 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: sync_framework cleanupsDebarshi Dutta2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch deals with cleanups meant to make things simpler for the upcoming os abstraction patches for the sync framework. This patch causes some substantial changes which are listed out as follows. 1) sync_timeline is moved out of gk20a_fence into struct nvgpu_channel_linux. New function pointers are created to facilitate os independent methods for enabling/disabling timeline and are now named as os_fence_framework. These function pointers are located in the struct os_channel under struct gk20a. 2) construction of the channel_sync require nvgpu_finalize_poweron_linux() to be invoked before invocations to nvgpu_init_mm_ce_context(). Hence, these methods are now moved away from gk20a_finalize_poweron() and invoked after nvgpu_finalize_poweron_linux(). 3) sync_fence creation is now delinked from fence construction and move to the channel_sync_gk20a's channel_incr methods. These sync_fences are mainly associated with post_fences. 4) In case userspace requires the sync_fences to be constructed, we try to obtain an fd before the gk20a_channel_submit_gpfifo() instead of trying to do that later. This is used to avoid potential after effects of duplicate work submission due to failure to obtain an unused fd. JIRA NVGPU-66 Change-Id: I42a3e4e2e692a113b1b36d2b48ab107ae4444dfa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1678400 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement dGPU simulation supportTerje Bergstrom2018-04-22
| | | | | | | | | | | | | Implement support for dGPU fmodel. The message protocol is slightly different and accessed via BAR0 aperture. JIRA NVGPUT-41 Change-Id: Ide3c52a751530f520854965c1eba19fa8339a315 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694963 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export gv11b fifo APIsDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | | | | Export below APIs from fifo_gv11b.h gv11b_fifo_init_ramfc_eng_method_buffer() gv11b_userd_writeback_config() Also move #define PBDMA_SUBDEVICE_ID to header file Jira NVGPUT-19 Change-Id: I5e3abf02acfe014e39550f236d60d8991a75b4ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699315 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to set ppriv timeoutsDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | | Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific ppriv timeouts Set this HAL for all supported GPUs for now Jira NVGPUT-35 Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699314 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of pb_header_priv_user()Deepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | H/W field NV_PPBDMA_PB_HEADER_PRIV is obsolete in Volta and has no effect Hence remove use of pb_header_priv_user() from channel_gv11b_setup_ramfc() Jira NVGPUT-31 Change-Id: I0bb08c5d5a26218bb057e19983044dac5238142f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699313 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support upcoming GPUDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | | | | In gpu_init_hal(), call NVGPU_NEXT_INIT_HAL() to initialize HAL of upcoming GPU All upcoming GPU related support is compiled only if CONFIG_TEGRA_GPU_NEXT is set Jira NVGPUT-42 Change-Id: I1563acd60f20fda50f4557a068398c1d5d224f3e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699312 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support PCI device 0x1e3fDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | Add PCI device ID for 0x1e3f and also add gk20a_platform data for same Jira NVGPUT-42 Change-Id: I3a6fb8ac4378d45add09795134da8fd3b174ac56 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699311 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post dbg session event from os specific codeSourab Gupta2018-04-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of debug session unification following changes are required. -Including bug.h header file to fix the compilation issue on QNX - The mechanism of posting debug events is OS specific. In Linux this works through poll fd, wherein we can make use of nvgpu_cond variables to poll and trigger the corresponding wait_queue via nvgpu_cond_broadcast_interruptible() call. The post event functionality on QNX doesn't work on poll though. It uses iofunc_notify_trigger to post the debug events to calling process. As such QNX can't work with nvgpu_cond's. To overcome this issue, it is proposed to create a OS specific interface for posting debugger events. Linux can call nvgpu_cond_broadcast_interruptible() in its implementation, which makes sense since these are already initialized and poll'ed in the Linux specific code only. QNX can implement this interface to call iofunc_notify_* functions, as per its need Jira VQRM-2363 Change-Id: I0abdc0787f771040b8aff5384290d7e6549f81fb Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Signed-off-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696368 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: assume 1:1 IPA to PA mapping for syncptThomas Fleury2018-04-19
| | | | | | | | | | | | | | | | | | | | | Currently, hyp_read_ipa_pa_info() only translates IPA for RAM mappings. It fails for MMIO mappings. In particular, it will fail when attempting to translate addresses in the syncpoint shim aperture. As a workaround, assume 1:1 IPA to PA mapping when hyp_read_ipa_pa_info fails, and address is in syncpt shim aperture. Bug 2096877 Change-Id: I5267f0a8febf065157910ad3408374cacd398731 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687796 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: add hal op for gr set error notifier"Richard Zhao2018-04-19
| | | | | | | | | | | | | | | This reverts commit d6c6c6c483478654b34685b9e13ed160bad49a1c. RM server has moved to gops.fifo.set_error_notifier. gops.gr.set_error_notifier is not needed anymore. Jira VQRM-3058 Change-Id: I0fe7f914778ce66701a699aece2b36a5cd8079da Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679708 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix map buffer overflow handling.Ashutosh Jain2018-04-17
| | | | | | | | | | | | | | | | | | | | Currently in case of overflow in buffer mapping the dma buf fd reference is not freed which causes the handle to remain allocated forever. Bug 200398767 Change-Id: Id3bf88636b927d75595f8a8b9f240b6717bf3b57 Signed-off-by: Ashutosh Jain <ashutoshj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694864 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass pid/tid from os specific code to common codeRichard Zhao2018-04-16
| | | | | | | | | | | | | | | | | | linux driver runs in user's process but qnx driver has dedicate driver process, so they have different way to get user pid. nvgpu common code expect calls from os specific code pass pid/tid. ce/cde open channel for internal use, we use driver pid. Jira VQRM-3534 Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694145 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: consider floorswept FBPA for getting unicast listDeepak Nibade2018-04-16
| | | | | | | | | | | | | | | | | | | | | | | | In gr_gv11b/gk20a_create_priv_addr_table() we do not consider floorswept FBPAs and just calculate the unicast list assuming all FBPAs are present This generates incorrect list of unicast addresses Fix this introducing new HAL ops.gr.split_fbpa_broadcast_addr Set gr_gv100_get_active_fpba_mask() for GV100 Set gr_gk20a_split_fbpa_broadcast_addr() for rest of the chips gr_gv100_get_active_fpba_mask() will first get active FPBA mask and generate unicast list only for active FBPAs Bug 200398811 Jira NVGPU-556 Change-Id: Idd11d6e7ad7b6836525fe41509aeccf52038321f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694444 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable elcg, blcg, slcgSeema Khowala2018-04-12
| | | | | | | | | | | | | | Bug 200399393 Change-Id: I60b2704ba447e45c330f2dc133cb2fa17e107f1c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683105 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: support clock gatingSeema Khowala2018-04-12
| | | | | | | | | | | | | | -Generated list for addr/value pairs using gen_gating_reglist.pl --target_ip=gv100 --soc=t194 -Comment out addresses triggering priv/pbus errors Bug 200399393 Change-Id: Ica0fd65070a7100f20afa32184f4a2e3cad6d0c2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683101 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 f/w version updateMahantesh Kumbar2018-04-12
| | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1684238/ - APP_VERSION_GP10X "23647537" updated to "23732390" Change-Id: Id534b041e4ae90e82b2a8259bb0372689500e871 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_fll interface as per chips_aTejal Kudav2018-04-12
| | | | | | | | | | | | | | | | | | | Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Port clkdomain & clkprog from chips_aVaikundanathan S2018-04-12
| | | | | | | | | | | | | | | | | Update clk_domain_3x_prog, Add vbios hal entry for GV100 Add stubbing in place of boardobj_interfaces. Change-Id: Id880f303f40a07a6bf2a7f4f21d612124e89fe03 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660697 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove uapi include from ce2Sourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | Remove the include of a uapi header from ce2.c since this file no longer makes use of any uapi definition. VQRM-3465 Change-Id: Ib9ba7090021f5fc21734adca80be8a0ea224bf90 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691980 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add conversion function for uapi submit gpfifo flagsSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | The submit gpfifo flags are splattered everywhere inside the nvgpu code. Though the usage is inside nvgpu Linux code only, still it needs to be gotten rid of and replaced with the defines present in common code. VQRM-3465 Change-Id: I901b33565b01fa3e1f9ba6698a323c16547a8d3e Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691979 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_gpfifoSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_gpfifo splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: I9e5ac697a0c7f85239ddba319085c09481d20d6b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691978 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_fenceSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_fence splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: Ic3737450123dfc5e1c40ca5b6b8d8f6b3070aa0d Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691977 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: vgpu: fix gmmu unmapAparna Das2018-04-10
| | | | | | | | | | | | | | Unmap gpu va at vsrv before freeing the address at guest to ensure there is no valid IPA to PA mapping when the address is reallocated at guest. Bug 200399982 Change-Id: If9375c69eac0f0dee23995f61b6486465618bf10 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691532 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc/tpc index for SMPC broadcast conversionDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | In gv11b_gr_egpc_etpc_priv_addr_table(), we call gv11b_gr_update_priv_addr_table_smpc() to convert SMPC broadcast address into list of unicast addresses But before calling gv11b_gr_update_priv_addr_table_smpc() we sometimes incorrectly set gpc_num/tpc_num to zero and that leads to generating incorrect list of unicast addresses Remove this incorrect initialization of gpc_num/tpc_num Also update gv11b_gr_egpc_etpc_priv_addr_table() to receive tpc_num along with gpc_num Bug 2099717 Jira NVGPU-580 Change-Id: Idd4e5f78dbe6ca1800efae93c66355d06417d1f2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691373 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix fpb_en_maskDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | In gr_gm20b_get_fbp_en_mask(), we read incorrect fuse register to get status of enabled FBPs And then we use incorrect arithmetic to calculate fpb_en_mask Fix this by using correct fuse register and also doing correct arithmetic to get mask of enabled FBPs Bug 200398811 Jira NVGPU-556 Change-Id: I79f3ebf590faa9baf176c7a939142c379bf5ebf4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690029 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use HAL for chiplet offsetDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | | | We currently use hard coded values of NV_PERF_PMMGPC_CHIPLET_OFFSET and NV_PMM_FBP_STRIDE which are incorrect for Volta Add new GR HAL get_pmm_per_chiplet_offset() to get correct value per-chip Set gr_gm20b_get_pmm_per_chiplet_offset() for older chips Set gr_gv11b_get_pmm_per_chiplet_offset() for Volta Use HAL instead of hard coded values wherever required Bug 200398811 Jira NVGPU-556 Change-Id: I947e7febd4f84fae740a1bc74f99d72e1df523aa Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support to get unicast addresses on voltaDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | | | We have new broadcast registers on Volta, and we need to generate correct unicast addresses for them so that we can write those registers to context image Add new GR HAL create_priv_addr_table() to do this conversion Set gr_gk20a_create_priv_addr_table() for older chips Set gr_gv11b_create_priv_addr_table() for Volta gr_gv11b_create_priv_addr_table() will use the broadcast flags and then generate appriate list of unicast register for each broadcast register Bug 200398811 Jira NVGPU-556 Change-Id: Id53a9e56106d200fe560ffc93394cc0e976f455f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690027 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add broadcast address decode support for voltaDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Volta we have more number of broadcast registers than previous chips and we don't decode them right now in gr_gk20a_decode_priv_addr() Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all previous chips Add and use gr_gv11b_decode_priv_addr() for Volta gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set the broadcast flags apporiately Define below new broadcast types PRI_BROADCAST_FLAGS_PMMGPC PRI_BROADCAST_FLAGS_PMM_GPCS PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB PRI_BROADCAST_FLAGS_PMMFBP PRI_BROADCAST_FLAGS_PMM_FBPS PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP Bug 200398811 Jira NVGPU-556 Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690026 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 08:31:46 -0500