| Commit message (Collapse) | Author | Age |
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Implement SW method SET_RD_COALESCE to implement correct handling
of texture read coalescing.
Bug 200223870
Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1271303
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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And reduce pri timeout to match PCIE specs
bug 200246808
Change-Id: I0225ae964b5635665fe774c43f773d0ce86650ab
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1264179
(cherry picked from commit 1c3dbf8324b7ec5d06bd0e57e7deee9a1c8e9411)
Reviewed-on: http://git-master/r/1280328
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement the permanent disable_aspm() function for XVE on gp106.
Bug 200256272
Change-Id: I63338415542381d8a43d746d9d4404a74a5f01cd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1263273
(cherry picked from commit 7890419f242a50c6d8ec27c3e8eb331823230ed9)
Reviewed-on: http://git-master/r/1280309
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Disable ASPM on boot for PCIe platforms.
Bug 200256272
Change-Id: I0dc63c1a5a9941a5ecdc6a5d691c0b780fb9a6b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1263272
(cherry picked from commit bf576ea8a88326d107b3a91d196fe6d6018185f6)
Reviewed-on: http://git-master/r/1274478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a platform flag and logic to disable ASPM on boot if a
platform does not want ASPM enabled.
Bug 200256272
Change-Id: I378997290377ef8ffa21bf8e7f3f59fa134b3d4d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1263271
(cherry picked from commit 01e4700b74f4b4c6f0b9ffb40747653f2b63ea3c)
Reviewed-on: http://git-master/r/1274477
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Handle possible asynchronous GPU driver shutdown more gracefully.
This occurs when the GPU disappears from the PCI bus, for example,
if it overheats or detects an over current event.
Also add a preprocessor check to make sure that the
gk20a_channel_cancel_pending_sema_waits()
is always defined. In some builds CONFIG_SYNC is disabled but the
gk20a_remove_support() code does not check for this.
Bug 1816516
Bug 1807277
Change-Id: I932e312291c5c6a6ac5e13525ce8ca56a1be3652
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250028
(cherry picked from commit 337810f8c478238a38d8553c1492622d5fa9aafa)
Reviewed-on: http://git-master/r/1274476
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move the code that waits for deferred interrupts to nvgpu_common.c and
make it global. Also rename that function to use nvgpu_ as the function
prefix.
Bug 1816516
Bug 1807277
Change-Id: I42c4982ea853af5489051534219bfe8b253c2784
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250027
(cherry picked from commit cb6fb03e20b08e5c3606ae8a5a9c237bfdf9e7da)
Reviewed-on: http://git-master/r/1274475
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix miscellaneous issues seen during driver shutdown.
o Make sure pointers are valid before accessing them.
o Busy the GPU during channel timeout.
o Cancel delayed work on channels.
o Avoid access to channels that may have been freed.
Bug 1816516
Bug 1807277
Change-Id: I62df40373fdfb1c4a011364e8c435176a08a7a96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250026
(cherry picked from commit 64a95fc96c8ef7c5af9c53c4bb3402626e0d2f60)
Reviewed-on: http://git-master/r/1274474
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In many helper functions like gk20a_readl() the code assumed that
the GPU is present and registers and available. However, during
GPU shutdown this may not be the case.
In theory the driver should not be accessing GPU registers during
GPU shutdown (since shutdown is triggered by GPU registers being
unavailable) but these changes handle any missed cases where this
may happen.
This goes for GPU device access as well. Many parts of the code
assume that if the struct gk20a is valid, the the GPU dev must be
there are well. This isn't always the case, it seems.
Bug 1816516
Bug 1807277
Change-Id: Icaf6fd56ab7860724e77bda0f5e8d48f0da15642
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250024
(cherry picked from commit e8c9997b2d7cd424d798ecfce1307e6193c0cf32)
Reviewed-on: http://git-master/r/1274473
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable FECS ctxsw tracing for gp106. Ensure that FECS records
have been written to memory before accessing the ring. Update
read index only once all records have been processed.
Jira EVLR-424
Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1258243
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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nvgpu_clk_arb_init_arbiter() allocates master structure arb, and
sub-structures which is assigns as members of arb. At failure,
there's a single error label, and it tries to free the members of
arb without checking that arb was allocated.
Change-Id: Ifac7552b05dad17036835eb3ee624eae351ccb7d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1279226
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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nvgpu_clk_arb_install_fd() leaks dev if it cannot create an fd,
and it leaks both dev and fd if it fails to create a file.
Change-Id: I65c03401dba44d88be543d3aec2fa3fcd2fb0dcc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1279225
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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clk_prog.h and clk_vin.h refer to boardobjgrp_e32 and
boardobjgrp_e255.h. Add explicit #includes for their definition.
Change-Id: Ib651b071f3c17bbc30ddaea0ef9bc5437ec9f2f4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1279224
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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We retrieve perf table from VBIOS only if respective HAL op is
implemented. Later in code we unconditionally dereference the pointer
which can lead to NULL pointer access.
Fix by early aborting creation of devinit tables if the perf VBIOS
getter is missing.
Change-Id: If48aa6dac724056dd1feb2ef520e343736d4db85
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1279223
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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We use GPU reference clock as a divider. Check before division that
reference clock is not zero.
Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275743
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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In gk20a_submit_prepare_syncs(), after we have allocated wait_cmd
we check the results. If we failed to allocate wait_cmd, we still
jump to the error label that tries to free wait_cmd.
Create an own error labal for allocation before wait_cmd, and use
that if we fail to allocate wait_cmd.
Similarly create an error label for incr_cmd, and use that only once
incr_cmd has actually been allocated.
Change-Id: I1f8bc1d947c524038f5f237358a5e6b0dc2e6ac3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275742
GVS: Gerrit_Virtual_Submit
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When allocating job channel_gk20a_job structure we assign the result
of allocation to *job_out, but we check the result of allocation
in job_out.
Change the check to check for result in *job_out.
Change-Id: Ia170cfa2dd5730665434b4c223c5a2f9502c744d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275741
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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We first load VBIOS firmware from file, and then attempt to allocate
space into which we copy the data. If allocation fails, we do not
release the firmware.
Add a release_firmware() in the error path.
Change-Id: Iaa995e93bf8d5a23e08c5e332f70b203ac2e09db
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275740
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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boardobjgrp.h #includes boardobjgrp_e32.h and boardobjgrp_e255.h.
They in turn #include back boardobjgrp.h.
Remove recursion.
Change-Id: Ic0eb8ddf3ddd3996302fe2b74d9e3ff8e395b1b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275739
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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When we allocate boardobj object, we assign the allocated address
to *ppboardobj. The check for result of allocation checks looks
at address in ppboardobj.
Fix the check so that it actually checks results of kzalloc().
Change-Id: I90fda36afd1627efcf2fdea46bcd7ad1a7e3bb51
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275738
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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voltage_get() defines det_out as u32. That variable is used to
calculate a 64-bit result, so cast det_out to u64.
Change-Id: I054ec299a4c7961cb38dd5ac0cbf0ac173b09efb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267692
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Fix slab-out-of-bounds issue reported by KASAN
[ 29.922710] BUG: KASAN: slab-out-of-bounds in
gr_gk20a_init_fs_state+0x1bc/0x898 at addr ffffffc1a0988c04
...
[ 29.961820] INFO: Allocated in gr_gk20a_init_gr_config+0x380/0x1b20
age=374 cpu=5 pid=1
...
Out-of-bound access from
[ 30.241943] [<ffffffc0007d2674>] gr_gk20a_init_fs_state+0x1bc/0x898
[ 30.248205] [<ffffffc000839a2c>] gr_gm20b_init_fs_state+0x4c/0x5c8
[ 30.254381] [<ffffffc000871670>] gr_gp10b_init_fs_state+0x160/0x3a8
[ 30.260643] [<ffffffc0007d70ec>] gk20a_init_gr_setup_hw+0x974/0x1530
[ 30.266991] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0
[ 30.273164] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10
[ 30.279684] [<ffffffc00079dfd0>] gk20a_pm_runtime_resume+0x30/0x58
Fix this by using a separate API gr_gk20a_get_tpc_count()
which returns tpc count for a gpc and returns 0
if gpc index is greater than available gpcs
Bug 200257557
Change-Id: I78856ca93c0381cb4bcef7a56a5210fa269cf3ac
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1277692
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Compile local t18x code from nvgpu repo (in case
CONFIG_ARCH_TEGRA_18x_SOC config is set)
instead of compiling from $(srctree)/../nvgpu-t18x
Remove Makefile.nvgpu-t18x since this Makefile is
not needed now
Bug 200266498
Change-Id: Ib8ef39be7e948debe0ff895c904a6c370a5711a6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1277119
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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In gr_gp10b_set_preemption_mode(), skip setting anything
if both graphics and compute preemption modes are
already set
Bug 200263471
Change-Id: I2788464750835da8f6396c6c1ca8356a63758c80
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1275465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- PG statistics read support for multiple engines
JIRA DNVGPU-71
Change-Id: I2dc3aad243300d21dc3d20a54a5e4736977e071b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1250507
(cherry picked from commit 985cb3be1d6d990bc6651e417d9e6ba9bfe306e0)
Reviewed-on: http://git-master/r/1270991
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Currently sparse mapping is not supported for gp10b
in virtualized environment. Modify gpu characteristics
to reflect non-implementation of this functionality.
Also fix return value in vgpu_gp10b_locked_gmmu_map()
on error condition.
Bug 200243373
Change-Id: Ia367b923b87738a5cad0617cdb074f5a24fb1c81
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: http://git-master/r/1269710
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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(1) Adding additional debug in case of VF update failure
(2) The length of the tables must be re-initialized
prior to requesting the vf table update
JIRA: DNVGPU-193
Change-Id: Id5a369359bc5f52ee58da539bfc3ec1ec7887de1
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1252061
(cherry picked from commit dfb6fec02f8e3ff6a22bbea000347923b0306018)
Reviewed-on: http://git-master/r/1274547
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Current code cast casting the frequency to 16 bit
before division, giving out incorrect data
JIRA DNVGPU-164
Change-Id: I4eb1fa73fb9e8963f550d3d853db39b49b990fa4
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1251663
(cherry picked from commit c0d91a054f8278af9a2383bb3f837465779132a9)
Reviewed-on: http://git-master/r/1274546
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA: DNVGPU-180
Change-Id: I1928e77cea4ac87bf2ba2b6b7b2f2942dfb97de9
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1251493
(cherry picked from commit 7b8a105652a3169d9ec0cb7ce52c3b92e42ca310)
Reviewed-on: http://git-master/r/1274545
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use common fuse write API tegra_fuse_control_write
which should work on all kernel versions
Bug 200262155
Change-Id: I29e8514e9660549ecf94711287ec4bbf4c897a86
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1270169
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We currently do not allow resetting preemption
modes once set
Relax this check to allow upgrading preemption
modes. Downgrading of preemption modes is still
not allowed
Bug 200263471
Change-Id: Ie2dae910028929090899a661f4b8b9dd4d6d7ee7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1269472
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bug 1845211
clfc is reset during vf switch. it resets delta values stored in
pmu structure. if voltage has not changed, delta calculation happens
on top of corrected voltage causing volt to keep on increasing in cases
where voltage does not change during a vf switch.
Change-Id: I9d1a58b6b7652f22c3a7304162bb8ca6f7d1da6f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1266632
(cherry picked from commit 74e2e97d4d149d3eac65b5f65b358b977fba463e)
Reviewed-on: http://git-master/r/1273911
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-175
1)Add functions to be called before and after vf change
2)Capture noise unaware vmin value and pass it as param
to vf change functions
3)Before VF change disable CLFC and update noise unware vmin
4)After VF change is done enable CLFC
Change-Id: I4bb59fbe96ec5a792e8930db3ab4a39ec74c9a71
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248211
(cherry picked from commit cf07892204d7ce11a0d27ecbc1f5826fbabbde61)
Reviewed-on: http://git-master/r/1270950
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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sec2 falcon reset after secure boot complete
to keep sec2 idle
issue: ELPG does not engage if PG engine is
dependent on sec2 idleness
JIRA DNVGPU-71
Change-Id: If264c610dae857ae9b9f9bc77c59f24f239ce1ce
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247290
(cherry-picked from commit de2337de1211e4167993982e50237fe1115053a1)
Reviewed-on: http://git-master/r/1267260
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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lpwr_entry_idx member is required
to map pstate with lwpr tables
JIRA DNVGPU-71
Change-Id: I4cad54c61dec7ad7e3c1a60178938d0eeaf65e24
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247303
(cherry-picked from commit b1f6e0036922d2104b3d08548219e72a38f2e231)
Reviewed-on: http://git-master/r/1267403
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Updated gp10b_pg_gr_init() to post init param based
on PG engine parameter
- Assigned pg engine list/features HAL to respective
functions/NULL
JIRA DNVGPU-71
Change-Id: I7d059796746694b22800c6ae0327cbc90331e929
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247407
(cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502)
Reviewed-on: http://git-master/r/1269321
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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For target clocks >= FFR cutoff clock use FR, else use FFR.
JIRA DNVGPU-180
Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1249041
(cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11)
Reviewed-on: http://git-master/r/1270883
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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bug 200254784
If XBAR and SYS clocks for a given GPC clock point is lower
than minimum value mentioned in P state set the floor to
minimum value mentioned in p state. it was set to value
based ratio of a GPC clk value in VF table which can give
value higher than one mentioned in p state. Ignore ratio
and just set to p state value
Change-Id: I9f7cd1d5842d057aff6d8243a31ab503ce35a8ca
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1257251
Reviewed-by: Automatic_Commit_Validation_User
(cherry picked from commit 5798680286967ff999f674bedd4fc0411615f914)
Reviewed-on: http://git-master/r/1270949
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-170
1) Add clock frequency controller VBIOS structure definitions
2) Parse VBIOS tables and build boardobj structures for clock frequency
controller.
3) send clock frequency controller data structures to PMU
4) implement public function to send load/unload command to pmu
to enable/disable clock frequency controller support
Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07)
Reviewed-on: http://git-master/r/1270897
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-184
implement a function which takes noise unaware vmin for
logic and sram rails as input and sends them to pmu via RPC
Change-Id: Ic0d72daf99870477d4dbd17e1c609dd0c39f8197
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248210
(cherry picked from commit 2ad833c1edf65ada6c72b56ecd3551e7c4d396f6)
Reviewed-on: http://git-master/r/1270885
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Modification of the ARBITER clocks to be P-State aware
Up to now the arbiter just considered the whole range
of the GPC and MCLK domains, which could end up on
illegal combinations of MCLK, GPC2CLK, and set the
SYSCLK and XBARCLK domains below their minimum VCO
The following has been implemented:
(1) Modified VF tables to add which PState are
supported on each point.
(2) Return and store the current PState on the
arbiter state.
(3) Modified logic to prevent illegal combinations of
MCLK and GPC2CLK.
(4) Modified logic to prevent setting VF points for
XBAR and SYS domains below VCO limits.
(5) Modified voltage calculation to account for increased
values of XBAR and SYS on some VF points.
(6) Modified arbiter clock target logic to prevent an
application that has not requested a particular VF point
to set target to default targets.
(7) Remove unnecesary mutexes from critical path
JIRA DNVGPU-182
JIRA DNVGPU-183
Change-Id: I3d1c30903278f848681b8da833a867835acc99bb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1247937
(cherry picked from commit b8bcc07eb3b5b70ec1ee19ace237df99d6170138)
Reviewed-on: http://git-master/r/1268063
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-129
1)send 150'c as default temperature to PMU so that PMU will
start reading temperature from sensor to evaluate VFE equations
2)Send GP106's temp min and max range for GPU sensor so that PMU
will read right temperature
3)PMU will send event whenever temperature goes above +ve hysteresis
or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation
function in the event handler.
Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1245392
(cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7)
Reviewed-on: http://git-master/r/1268062
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The current code can lead to application hang when
opening device on first time if the arbiter fails
to set the clocks
Also it solves a buffer overrun condition in case
the requested frequency is above the maximum range
of the VF curve
bug 1835042
Change-Id: I385401ea27d5cc4bfa41b7ca2eb3a1db53138418
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1245911
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268061
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-143
Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1268107
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add ioctls to retrieve voltage, current, power and temperature.
Add flags in GPU characteristics to indicate if feature is supported.
Jira DNVGPU-166
Change-Id: Ifaafe2efdb6b09d7b28215b641814f28e894151e
Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1241861
Tested-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1267122
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Modification of the arbiter to remove all locking
from the arbiter callback and move the callbacks
out of the global queue
Adding modification to call for updated values of
vf table from arbiter init function and on
vf table update
JIRA: DNVGPU-170
Change-Id: I7a7d34c0590522901e06356c06fd8114ebf10f37
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1243212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1268009
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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(1) modified counters debug code to export to the driver
(2) modified arbiter to read from those functions
(3) modified counter for higher accuracy on MHz range
JIRA DNVGPU-164
Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268008
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