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* gpu: nvgpu: handle memfmt exceptionDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | In gk20a_gr_isr(), handle memfmt exception as below : - read NV_PGRAPH_PRI_MEMFMT_HWW_ESR - debug print for contents of above register - write same value back to NV_PGRAPH_PRI_MEMFMT_HWW_ESR and clear the exception Bug 200078514 Change-Id: I5b9afacd7f99b5a37de953041582b3a53b863642 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713713 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* sync: Support timestamp passingMichael Frydrych2015-04-04
| | | | | | | | | | | | | | | | | Timestamps read in an interrupt handler and when fence state is being updated can differ by variable amount. That add unnecessary jitter to original interrupt times. This patch adds support for passing timestamp from the device driver thereby allowing more accurate timestamps. Bug 1543760 Change-Id: Idcfd5cb435b0bd585e3c16cd299c6f456d4509c4 Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/360939
* gpu: nvgpu: Add DT support for gpu power-domainSumit Singh2015-04-04
| | | | | | | | | | | | | First, defining a new structure to support gk20a power domain. Then making necessary modifications to add so as to add DT support for gpu power-domain. bug 200070810 Change-Id: I29e1c24b181e14743d3969103abfd1882d171f07 Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/668973 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: support for dumping vpr/wpr infoSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | | Added support for dumping vpr/wpr info for gm20b. This dump info called when ever gk20a_mm_fb_flush is timed-out. Bug 200082817 Change-Id: I21b0372d0e3f976a189c9c428c015165b715bf88 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/711439 (cherry picked from commit b69897d71c8f6119b49ceb8d3273cdb354178cc5) Reviewed-on: http://git-master/r/712675 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Use busy looping for flush operationsSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | | | | | | | Use busy looping for l2 tag flush and elpg flush operations. This is making total flash time more accurate and reduced overall time compared with usleep. Also added trace points to measure performance for these operations. Also corrected timeout error check for non-silicon platforms. Bug 200081799 Change-Id: I63410bb7528db9258501633996fbdee5fdec1c74 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/710472 (cherry picked from commit 18684cf9d5d6870a1a1fd5711c4fc2d733caad20) Reviewed-on: http://git-master/r/710986 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* Revert "gpu: nvgpu: cache cde compbits buf mappings"Konsta Holtta2015-04-04
| | | | | | | | | | This reverts commit 9968badd26490a9d399f526fc57a9defd161dd6c. The commit accidentally introduced some memory leaks. Change-Id: I00d8d4452a152a8a2fe2d90fb949cdfee0de4c69 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/714288 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
* gpu: nvgpu: Allow enabling PC samplingTerje Bergstrom2015-04-04
| | | | | | | | | | | | Allow enabling of PC sampling hardware workaround. It is only applicable to gm20b. Bug 1517458 Bug 1573150 Change-Id: Iad6a3ae556489fb7ab9628637d291849d2cd98ea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/710421
* gpu: nvgpu: add exception registers to dumpDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: Ib0ec34f7bf5a136928c53cf8398b4929fb4639c5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/712480 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix some GPU boot error pathsTerje Bergstrom2015-04-04
| | | | | | | | Fix panics in error path when FECS cannot be booted. Change-Id: I354e37579386e27f46b80cd4172fe12897a3b92f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712698
* gpu: nvgpu: vgpu: remove explicit TLB invalidateAingara Paramakuru2015-04-04
| | | | | | | | | | | | | | The server does an implicit TLB invalidate after map and unmap operations. Bug 1616964 Change-Id: Ib6f4a23389f1e5d796d0f4b0be312f438c52927c Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/713221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: implement to initialize gr->gpc_tpc_maskHaley Teng2015-04-04
| | | | | | | | | | | | Bug 1509609 Change-Id: Ia78bd49518b41bc9f59e3d47a1390b126c7a2230 Signed-off-by: Haley Teng <hteng@nvidia.com> Reviewed-on: http://git-master/r/706861 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Jubeom Kim <jubeomk@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add flag for CAR reset in do_idle()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "force_reset" flag to __gk20a_do_idle() For real world use cases like VPR resizing, we cannot wait for railgate_delay (which is 500 mS). Hence use CAR reset for this use case. (this is done via gk20a_do_idle() API with force_reset = true) Some of the test cases make use of sysfs "force_idle" and they expect GPU to be into really railgated state and not in CAR reset. Hence when called from sysfs, set force_reset = false. When global flag "force_reset_in_do_idle" is set, it will override local flags and force CAR reset case. This is desired in cases where railgating is not enabled Also, set force_reset_in_do_idle = false for GM20B since railgating has been enabled for GM20B Bug 1592997 Change-Id: I6c5af2977c7211ef82551a86a7c1eb51b8ccee60 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/711615 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warnings of static declarationDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings by making below APIs static : kernel/drivers/gpu/nvgpu/gk20a/mm_gk20a.c:1795:5: warning: symbol 'update_gmmu_pde_locked' was not declared. Should it be static? kernel/drivers/gpu/nvgpu/gk20a/mm_gk20a.c:1841:5: warning: symbol 'update_gmmu_pte_locked' was not declared. Should it be static? Bug 200067946 Change-Id: I8158aaf503378b176cfd5cc129db9557803003c1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713024 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* host1x virtualization: basic supportPeter Daifuku2015-04-04
| | | | | | | | | | | | | - Adds a new host1x pushbuffer queue - Includes support for virtualized VIC Bug 1509609 Change-Id: Ie9b604dc8d8e43166dedb13953c4edac813da18b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/655506 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: add bar2 memory descriptorSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | Save bar2 memory descriptor in mm data structure. Bug 1587825 Change-Id: I3063c3e28a4e583c2d2c099402077d2d25fc6e68 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/682101 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: setup chip specific mm hw initSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | Add support for setting-up mm hw init per soc. Bug 1587825 Change-Id: Ie5c5e49a767cfb14e3dbbb6902349284cd3dca95 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681784 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct API to check valid syncptDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | Below check assumes that available syncpt range starts from 0 id >= nvhost_syncpt_nb_pts_ext() Instead of using this API, use nvhost_syncpt_is_valid_pt_ext() which validates the syncpt id against both upper and lower boundaries Bug 1611482 Change-Id: I7c4465a2bc84b63fefaa17c64f02582885924c5e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/711211 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: remove support for CDE firmware v0Jussi Rasanen2015-04-04
| | | | | | | | | | | | | | -CDE firmware v0 is not used anymore so we can remove support for it. -Bump the threshold for a large surface warning to 8k. Bug 1566740 Change-Id: Ia0434a04cdd453a10a8de08d259e92e6b9a3e964 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/709452 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Sparse warning fixSupriya2015-04-04
| | | | | | | | | | | | Bug 200067946 Change-Id: Ifec926b406c1daf0295d9ee07f1962b56c1b603a Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/711479 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: protect channel ioctls with a mutexKonsta Holtta2015-04-04
| | | | | | | | | | | | | | Add a big mutex for protecting the channel during ioctls, in case the userspace uses the same channel from several threads at once. The lock is taken during all operations except CHANNEL_WAIT, which could deadlock. Bug 1603482 Change-Id: Ibed962eadc9f00645abd54413dde9aaee00377ab Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/678871 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cache cde compbits buf mappingsKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | | don't unmap compbits_buf explicitly from system vm early but store it in the dmabuf's private data, and unmap it later when all user mappings to that buffer have been disappeared. Bug 1546619 Change-Id: I333235a0ea74c48503608afac31f5e9f1eb4b99b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/661949 (cherry picked from commit ed2177e25d9e5facfb38786b818330798a14b9bb) Reviewed-on: http://git-master/r/661835 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: disable ce2 interrupts when unhandledSam Payne2015-04-04
| | | | | | | | | | | ce2 interrupts enabled only on gk20a and gm20b when interrupts are handled through hal Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/677447 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Refactor page mapping codeTerje Bergstrom2015-04-04
| | | | | | | | | | | | | Pass always the directory structure to mm functions instead of pointers to members to it. Also split update_gmmu_ptes_locked() into smaller functions, and turn the hard coded MMU levels (PDE, PTE) into run-time parameters. Change-Id: I315ef7aebbea1e61156705361f2e2a63b5fb7bf1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672485 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: ioctl for flushing GPU L2sujeet baranwal2015-04-04
| | | | | | | | | | | | | | CUDA devtools need to be able to flush the GPU's cache in a sideband fashion and so cannot use methods. This change implements an nvgpu_gpu_ioctl to flush and optionally invalidate the GPU's L2 cache and flush fb. Change-Id: Ib06a0bc8d8880ffbfe4b056518cc3c3df0cc4988 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/671809 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable GO_IDLE timeout and skip waitingTerje Bergstrom2015-04-04
| | | | | | | | | Disable GO_IDLE timeout when pushing SW methods. This stops FE_GI bit from getting enabled, so remove polling for that, too. Change-Id: I695aa9fbc68d4fe722ae46a28d7f4cc05db75b3b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709878
* gpu: nvgpu: Ensure memory subsystem is enabledTerje Bergstrom2015-04-04
| | | | | | | | | | | Ensure that memory subsystem is enabled at init. Bug 1603128 Change-Id: Ie3fcd4d9df4dbd480e44fa8919fc311e61b627ca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/707027 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: add hw perfmon buffer mapping ioctlsKonsta Holtta2015-04-04
| | | | | | | | | | | | | | Map/unmap buffers for HWPM and deal with its instance block, the minimum work required to run the HWPM via regops from userspace. Bug 1517458 Bug 1573150 Change-Id: If14086a88b54bf434843d7c2fee8a9113023a3b0 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/673689 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: validate reg ops alwaysKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | Call validate_reg_ops() even when allow_all is set, since that function takes care of counting ctxsw regops which would not be executed without the counters set. Bug 1517458 Change-Id: Ie6173229fb6580e8812b7d2a52bfa8661f3d95e5 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/709439 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix if/else conds if PMU flag is OFF.Deepak Goyal2015-04-04
| | | | | | | | | | | | | | | | | | bug 200069748 Invalidating FECS code instblk is required only if FECS uses bootloader to load. Added check for same instead of using PMU support to invalidate. Handle elpg enable/disable call in case PMU is OFF. Change-Id: I28abbbbe1f22edd9e0417df9d0e831bbd770502c Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/670664 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: bypass smmu for VPR memory accessKrishna Reddy2015-04-04
| | | | | | | | | | | | | | SMMU translation should be bypassed for VPR accesses via GPU. clear sgt dma address to bypass smmu for VPR. Bug 1215470 Change-Id: I22df41a9afc447e2502055b7907cc1848a770f26 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/696509 (cherry picked from commit a699f55941fa22e90d41a53798956a542b212659) Reviewed-on: http://git-master/r/707889
* gpu: nvgpu: Use vzalloc for bitmapTerje Bergstrom2015-04-04
| | | | | | | | | | | | Allocator bitmap is now larger, and cannot be allocated with kzalloc anymore. Bug 200081843 Change-Id: I9c978ddbdd796e4f1dd5719dbef3a6bd99e64f48 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709884 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: register dump in ctxsw timeoutDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | Dump GR status registers in case of ctxsw timeout. This is helpful in case where ctxsw timeout is encountered during stress testing but we lose the bad state since we do the recovery. So dump as much status as we can when timeouts are seen Bug 200062436 Change-Id: Ie7d320cefa7b272f2cc607cdb5c01ba1f43ba1f2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/708465 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Per-chip PBDMA signatureTerje Bergstrom2015-04-04
| | | | | | | | PBDMA HW signature depends on the chip. Change-Id: If57d721d9bb77a090f967930a1aa2037bf4a16fe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672922
* gpu: nvgpu: Do not return timedout in emulationTerje Bergstrom2015-04-04
| | | | | | | | | We have infinite timeouts for loops in emulation. Some functions with the loops still return error if we exceed the original retry count. Change-Id: I1f9ddbfc0acd9f30f6bd49d9e748d8d8fbefa154 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709491
* gpu: nvgpu: Unify PDE & PTE structsTerje Bergstrom2015-04-04
| | | | | | | | | | Introduce a new struct gk20a_mm_entry. Allocate and store PDE and PTE arrays using the same structure. Always pass pointer to this struct when possible between functions in memory code. Change-Id: Ia4a2a6abdac9ab7ba522dafbf73fc3a3d5355c5f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/696414
* gpu: nvgpu: Install fd after no errors can happenTerje Bergstrom2015-04-04
| | | | | | | | | | | | | | fd_install() should be called only once all other initialization is done and no errors can happen. Bug 1589104 Change-Id: I822511a64d4c6fa59c8e772a896dbd6818459c97 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/706928 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: reduce message severity to infoNaveen Kumar S2015-04-04
| | | | | | | | | | | | | | | Shader informs user about context switch wait time. This doesn't affect any functionality. Hence changing print to info. bug 200015967 Change-Id: I7fbb562e43ee6ec1bc8ac01a51d3c9f19d5cb4cf Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: http://git-master/r/662657 (cherry picked from commit 3a4d2022369f4bfc1701d6543226e01d7f6f8e0d) Reviewed-on: http://git-master/r/671534 Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Tested-by: Venkat Moganty <vmoganty@nvidia.com>
* gpu: nvgpu: vgpu: fix AS splitAingara Paramakuru2015-04-04
| | | | | | | | | | | | | | | The GVA was increased to 128GB but for vgpu, the split was not updated to reflect the correct small and large page split (16GB for small pages, rest for large pages). Bug 1606860 Change-Id: Ieae056d6a6cfd2f2fc5066d33e1247d2a96a3616 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/681340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: APIs to dump GR statusDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add below APIs to dump various GR status registers 1. debugfs : /d/gpu.0/gr_status Read this debugfs at runtime to get status registers 2. API gk20a_gr_debug_dump() Add this API in code to dump registers at any point Bug 200062436 Change-Id: Ic1115b5a2fc16362954b5ed8a9e70afb872a8d91 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/486465 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: optimize fecs status pollingVijayakumar2015-04-04
| | | | | | | | | | | | | | | | bug 200078367 using udelay for fecs status polling during GR init phase brings down fecs transaction time to < 20usec from few hundred usec. Change-Id: I61a27daaf1187ac086a42779b46aa3fbee3b37f2 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/691918 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: WPR size 0, on railgate exitSupriya2015-04-04
| | | | | | | | | | | | | | | | | | | Bug 200066741 ACR ucode has mechanism to skip WPR blob copy for second time, in case WPR size is sent as 0 to acr ucode. With above there is a saving of around 0.5 ms, but, in conjunction with acr change to disable LS sig verification, and scrubbing empty spaces in WPR sections to 0. This change can reduce railgate exit latency by 4ms ACR ucodes to be checked in main, as a different CL, and after getting prod signs for ACR Change-Id: I9d662027abf0b2615176d17433ff3ec3ae53d78a Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/681892 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: FECS HALT methodSupriya2015-04-04
| | | | | | | | | | | | FECS halt method is used to do graceful FECS shutdown. Bug 1551865 Change-Id: Iec8590e86cb09f9b54c36f85859208fc8650f6a6 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/682459 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reset sync point at alloc/freeTerje Bergstrom2015-04-04
| | | | | | | | Change-Id: I8753e47ef4d3f4b3645ed6c6e604449d81d3da4b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709061 (cherry picked from commit cc07f316334b88cc18070fba9dd9149ba193bd38) Reviewed-on: http://git-master/r/707980
* gpu: nvgpu: More robust recoveryTerje Bergstrom2015-04-04
| | | | | | | | | | | | | Make recovery a more straightforward process. When we detect a fault, trigger MMU fault, and wait for it to trigger, and complete recovery. Also reset engines before aborting channel to ensure no stray sync point increments can happen. Change-Id: Iac685db6534cb64fe62d9fb452391f43100f2999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709060 (cherry picked from commit 95c62ffd9ac30a0d2eb88d033dcc6e6ff25efd6f) Reviewed-on: http://git-master/r/707443
* gpu: nvgpu: TLB invalidate after map/unmapTerje Bergstrom2015-04-04
| | | | | | | | | | | Always invalidate TLB after mapping or unmapping, and remove the delayed TLB invalidate. Change-Id: I6df3c5c1fcca59f0f9e3f911168cb2f913c42815 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/696413 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Fix NULL instead of intergerAmit Sharma (SW-TEGRA)2015-04-04
| | | | | | | | | | | | | | Fixed the following sparse warning using proper NULL instead of '0': - mm_gk20a.c:1301: warning: Using plain integer as NULL pointer Bug 200067946 Change-Id: Idd84f541711682bf097bb474049d523a5bb01ae2 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/682242 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Add Fmax at Vmin debugfs nodeAlex Frid2015-04-04
| | | | | | | | | Change-Id: I547cc02a544d117a4c76bf2541b9594d0769c2ef Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/682822 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Remove hard-coded GPU name stringsAlex Frid2015-04-04
| | | | | | | | | | | | Removed hard-coded GPU name strings. Instead retrieved GPU name via device name access interfaces. Change-Id: Iefb41cc610e92e870d4664951c3599df2bb83020 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/682671 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gpu pm control update for cde ioctlsSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | For cde ioctl "NVGPU_GPU_IOCTL_MARK_COMPRESSIBLE_WRITE", gpu hw not engaged. So remove this call from gpu pm control. Bug 1592636 Change-Id: I9b700e469bf365f2d02549cd9cd9babc68fbb049 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/680294 (cherry picked from commit cae24ee5e9630cc891fb7fcf98d234a42126f464) Reviewed-on: http://git-master/r/681622 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add a new CDE parameterJussi Rasanen2015-04-04
| | | | | | | | | | | Add TYPE_PARAM_GOBS_PER_COMPTAGLINE_PER_SLICE. Change-Id: I7cbf7b6db6642a61629ba06f7887bd58af3dc28f Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/673152 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 03:39:02 -0500