| Commit message (Collapse) | Author | Age |
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Move nv-p2p.h to include/linux so that it is
available to external kernel modules to be used.
Bug 200438879
Change-Id: I40707fe9f798b3ccf077dbdc942f8d6fc9019458
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1986646
(cherry picked from commit cfe4a2e5e87560519aedb92e2d12e39e09473a54)
Reviewed-on: https://git-master.nvidia.com/r/2000830
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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If enabled, fecs trace updating happens from ucode
side even when there is no fecs trace dumper application
to consume it. Due to this, trace buffer will get
eventually full and ucode will trigger ctxsw_intr0.
Reset fecs_trace buffer to handle timestamp buffer full
ctxsw_intr0.
Bug 2361571
Bug 200472922
Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965370
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 790ba095543b33f4cc3a145559ad31a1e9f99d98)
Reviewed-on: https://git-master.nvidia.com/r/1979746
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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ctxsw_intr0 is triggered by ucode even if it
is not enabled by driver. Add handling
for processing ctxsw_intr0. fecs mailbox(6)
is used to report fecs/gpccs misc error codes.
Also dump falcon stats for unhandled fecs intr.
Bug 2361571
Bug 200472922
Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966984
(cherry picked from commit 2c379cad0f6a01d07102898b362735a574f3aea8
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/1979745
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue is that local variable clear_intr is reset if fifo intr
handler happens to handle interrupts handled by fifo_error_isr.
This fix is to take care of clearing all handled fifo interrupts.
Bug 2361571
Change-Id: Ic8fe2294cfb25c58925942750a81c104ec9747de
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1960330
(cherry picked from commit 1195239d1c624e600ec4152374c493e887a90774
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/1979744
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-For queue full there is pmu_dbg message & returned with
EAGAIN error to end caller for retry, so intermediate error
message is not correct print for queue full.
Bug 200477085
Bug 200477931
Bug 200475876
Change-Id: I1109f15d0815f4ab2d8f8ca303db447d856f372c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit I263f66f7a8d8f1b98985f32f9daa49b09309c359)
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-on: https://git-master.nvidia.com/r/1979935
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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In nvgpu_kill_task_pg_init(), call nvgpu_thread_join()
if the init thread is no longer running in order to
reclaim thread resources.
Bug 2452799
JIRA ESRM-437
Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967983
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-on: https://git-master.nvidia.com/r/1970058
Reviewed-by: Shmuel Ungerfeld <sungerfeld@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Shmuel Ungerfeld <sungerfeld@nvidia.com>
Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
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- In vGPU code path, function vgpu_channel_abort_cleanup() does not
obtain channel reference before using the channel structure
(channel_gk20a)
- vgpu_channel_abort_cleanup() is called by vgpu_intr_thread() which
runs commands obtained from interrupt queue from RM server.
- If there is a scenario where gk20a_channel_release() function runs
before guest receives notification from RM server to abort channel
cleanup, channel gets freed before vgpu_channel_abort_cleanup() runs.
- However, because vgpu_channel_abort_cleanup() does not take explicit
reference to the channel, it ends up accessing structures
(such as ch->g) which are set to NULL and thus we end up in a crash.
- This patch explicitly takes reference of channel before
vgpu_channel_abort_cleanup() is called.
- If gk20a_channel_release() runs before vgpu_channel_abort_cleanup()
and ends up freeing channel, we dont get reference to freed
channel in vgpu_channel_abort_cleanup() and thus we return from
function rather than continuing with freed channel as was the case
previously.
Bug 200453473
JIRA EVLR-3411
Change-Id: I311043b2231336616b28246531cf8a0dc151b0cd
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932028
(cherry picked from commit b91228e506c14f04945e35b5c996f711bb30a155)
Reviewed-on: https://git-master.nvidia.com/r/1970807
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Karl Ding <kding@nvidia.com>
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Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This change adds RDMA supports for tegra iGPU.
1. Cuda Process allocates the memory and passes
the VA and size to the custom kernel driver.
2. The custom kernel driver maps the user allocated
buf and does the DMA to/from it.
3. Only supports iGPU + cudaHostAlloc sysmem
4. Works only for a given process.
5. Address should be sysmem page aligned and size should
be multiple of sysmem page size.
6. The custom kernel driver must register a free_callback when get_page()
function is called.
Bug 200438879
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: I43ec45734eb46d30341d0701550206c16e051106
Reviewed-on: https://git-master.nvidia.com/r/1953780
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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While tearing down PMU state during power off, nvgpu doesn't disable
the PMU interrupts. Disable them unconditionally.
Bug 200457485
Change-Id: Ia2462d879c1e7bbb4b5e8295ce211c38567c13e5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939025
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951361
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
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Add a flag to show if NVGPU_GPU_IOCTL_GET_GPU_LOAD is supported
Bug 200421190
Change-Id: I59200b1a3dbbcc0d731d1e77597e163c61417a96
Signed-off-by: Thomas Steinle <tsteinle@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1919448
(cherry picked from commit 7cb9e3cc14d3cec7e4685bd56728dc0e61b1b700)
Reviewed-on: https://git-master.nvidia.com/r/1944689
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update the comment to fix obvious issues and describe the
new allocation logic.
Bug 2327792
Change-Id: Ica0dd4159467e3023cc487a2bf9f525db3ad76e6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1831096
(cherry picked from commit c64f9432b13d47a791220578e823efcae4fe2a80)
Reviewed-on: https://git-master.nvidia.com/r/1949221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: James Norton <jnorton@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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If num_in_flight jobs is set use that to determine the proper
size of the priv_cmd_buf. If num_in_flight is not set then use
the original logic: the priv_cmd_buf is sized based on a worst
case assumption for the GPFIFO.
Also clean up MISRA issues.
Bug 2327792
Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1831095
(cherry picked from commit b9ec592f1d3ce23db736ff9c36eab994fc86ed46)
Reviewed-on: https://git-master.nvidia.com/r/1949220
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: James Norton <jnorton@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of using num_inflight_jobs to determine whether to pre-alloc
resources for a channel use the c->deterministic flag and the
number of inflight jobs field. Non-determinsitic channels do not
require pre-alloced resources and deterministic channels with 0
in flight jobs (i.e no kernel job tracking, AKA fast path sumits)
also do not require pre-alloced resources.
Bug 2327792
Change-Id: I7e8eb0478c22e005ca2c46c555415afa0ded0be1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850123
(cherry picked from commit 05ec7b80ebeabbc27d369ebd88dfe511c30d1bad)
Reviewed-on: https://git-master.nvidia.com/r/1949219
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: James Norton <jnorton@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When ACR and PMU BL fail to boot, the firmware are releasd, but the
firmware pointers are not re-initialized. That causes later invalid
pointer usage. Fix that by setting them as NULL.
Bug 200462464
Change-Id: Iacdf4b3c7f7144a77f595c77e6f5a29d35505672
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941671
(cherry picked from commit 3a87a0c99819d9b00d4b7e414ec0ecfeaade961c)
Reviewed-on: https://git-master.nvidia.com/r/1942950
GVS: Gerrit_Virtual_Submit
Reviewed-by: Siddardha Naraharisetti <siddardhan@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The tpc_pg_lock is not released properly when ACR fails to boot, so
the subsequent runtime PM resume operation will block. And it in
turn also causes shutdown block due to pending runtime PM operations.
Bug 200462464
Change-Id: Ia28ac11e8a7bbd826cf5f90ba8f90b29d2a55baa
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941670
(cherry picked from commit 0bda191d7b9c01a22b91feb523134b845ee7523b)
Reviewed-on: https://git-master.nvidia.com/r/1942949
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Add a reboot handler to make sure that nvgpu does not try to busy
the GPU if the system is going down. If the system is going down
then any number of subsystems nvgpu depends on may already have
been deinitialized.
Bug 200333709
Bug 200454316
Change-Id: I2ceaf7ca4fb88643310874b5b26937ef44c6e3dd
Signed-off-by: Kary Jin <karyj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1927018
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Reviewed-by: Vinayak Pane <vpane@nvidia.com>
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When turning off CONFIG_DEBUG_FS, there are build errors:
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o: In function `nvgpu_fecs_trace_init_debugfs':
os_ops_gp106.c:(.text+0x8): multiple definition of `nvgpu_fecs_trace_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp10b.o:os_ops_gp10b.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o: In function `gp106_therm_init_debugfs':
os_ops_gv100.c:(.text+0x0): multiple definition of `gp106_therm_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o:os_ops_gp106.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_tu104.o: In function `gv100_clk_init_debugfs':
os_ops_tu104.c:(.text+0x0): multiple definition of `gv100_clk_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o:os_ops_gv100.c:(.text+0x10): first defined here
This is because those functions aren't marked as static.
So this patch just simply fixes the bug.
Bug 2284925
Change-Id: I1da39345c653dfb50c509adb0c822b4657646c56
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929355
(cherry picked from commit 0fd9c84f870731705d6fdbf83d8e94519ff9d3bd)
Reviewed-on: https://git-master.nvidia.com/r/1933889
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The PMM type-specific broadcast->unicast expansion calculation
was using incorrect values. This caused the invalid register
accesses to be generated.
This change HAL-ifies the values, so that the expansion will be
performed correctly.
Bug 200454109
Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564
Signed-off-by: Matthew Braun <matthewb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921717
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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FECS could use any ctx headers for context switch, so needs to update
all ctx headers in the same tsg with hwpm buffer address.
Bug 2404093
Bug 200454109
Change-Id: I99e74cd8c768c06c3d215779db899a1318522db0
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917756
(cherry picked from commit f447a8d279b0d0abc8e2d3eb6f0596ea5cd87cbf)
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1920608
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The fix is incorrect. hwpm ctxsw mode should always in gr ctx.
This reverts commit 8f30251c67811834f9d93b50ce3e97fe3aa18051.
Bug 2404093
Bug 200454109
Change-Id: I8fae2c379b051a3f48fe9e886e3b2348bb94b935
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917755
(cherry picked from commit 70248d531479fac7946ae296f926518fcc5677a0)
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1920607
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MockIO unit test went in before the tmake changes. Now
adding tmake files so that it builds for target.
Change-Id: I9f08076a46f8f6487342553999d43279fb74cabb
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1851219
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers.
Split this into two different HALs gops.fb.dump_vpr_info() and
gops.fb.dump_wpr_info()
Also unset HALs accessing VPR registers on dGPUs
We don't support VPR on dGPUs
Remove fb_mmu_vpr_info_r() register and all its accessors from
dGPU headers
Bug 2173122
Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850947
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We don't support big page size beginning Pascal, so set HAL
gops.fb.set_mmu_page_size() to NULL on all those platforms
Also remove these accessors from corresponding platforms
fb_mmu_ctrl_use_pdb_big_page_size_v()
fb_mmu_ctrl_use_pdb_big_page_size_true_f()
fb_mmu_ctrl_use_pdb_big_page_size_false_f()
Bug 2173122
Change-Id: I7353412860a7a6f8a993ca9184a0dc3ca9d749af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850946
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Remove these unused accessors
fb_mmu_ctrl_vm_pg_size_f()
fb_mmu_ctrl_vm_pg_size_128kb_f()
fb_mmu_ctrl_vm_pg_size_64kb_f()
ram_rl_entry_tsg_timeslice_timeout_disable_v()
Bug 2173122
Change-Id: I5b18ab502265ed4575fceb4bd5d0ab07dd3c12a8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850945
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Add support for the measure_freq clock op for igpu:
- add nvgpu_clk_measure_freq(), which in turn calls
the get_rate() clock op.
- Initialize the measure_freq clock op to nvgpu_clk_measure_freq()
for native linux and vgpu.
JIRA ESRM-398
Change-Id: I8a3b2ee79e29e3491a16f55281494f05cd841b07
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850585
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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If nvgpu_ioctl_tsg_open() fails, this file has no priv data yet on
release(). In that case there is nothing to free so just return.
Jira NVGPU-967
Change-Id: I02dd1bb12a27745a3b28aaa4a943d79d82b14d2c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1847592
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PMU ucode is updated to use acrlib from t19xbringup
branch.
We are seeing build issues due to incompatibility
with acrlib from tegra_acr branch.
CTX_DMA aperture to be used for loading LS falcons
needed update in the local acrlib.
Bug 2400729.
Change-Id: Iad00a332acfac307c389bde504893a87abaf7460
Signed-off-by: Deepak <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849182
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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-Created struct nvgpu_sec2 to hold members
related to SEC2-RTOS ucode support in header file
sec2.h
-Created nvgpu_sec2 variable under struct gk20a.
-Created NVGPU_SUPPORT_SEC2_RTOS enable flag
to enable SEC2 RTOS support.
-Defined method nvgpu_init_sec2_support() to
init SEC2 RTOS support by performing s/w setup like
mutex-init, sequence-init & add support
for remove_support.
-Defined method nvgpu_sec2_destroy() to deinit
SEC2 RTOS support.
-Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy()
as part gk20a_finalize_poweron()/gk20a_prepare_poweroff()
sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag
-Assigned g->sec2->flcn to point to g->sec2_flcn to access
falcon.
-Made Makefile changes to include sec2.c to build
JIRA NVGPUT-80
Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791955
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-Created command/message nv_flcn_cmd/msg_sec2
data struct to communicate between nvgpu<->sec2-rtos
in header file sec2_cmd_if.h
-Created acr command/message nv_sec2_acr_cmd/msg
to perform operation like bootstrap LSF flacon
in header file sec2_if_acr.h
-Created defines common SEC2 defines to use across
multiple operation related to SEC2-RTOS in header file
sec2_if_cmn.h
-Created data struct sec2_init_msg_sec2_init to receive
message from SEC2-RTOS to init queues, debug
data in header file sec2_if_sec2.h
JIRA NVGPUT-81
Change-Id: I4efbca20de7a2483d17de97841ada5336189e2b8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Add the posix-env test to the unit test suite that gets built
by tmake. This test caught a legit bug in the posix impl on
the target platform which needed to be fixed first.
JIRA NVGPU-1234
Change-Id: Ic62eac0bb62741dd03883dcd24c57b49ff67fa0e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1846180
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Explicitly use signed types in the sXX typedefs. C implementations
are apparently free to use either signed or unsigned as the default
for types like char.
JIRA NVGPU-1234
Change-Id: I0a37025b42d0ecb42ca90f29d3c3b70cf8cc807d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1846179
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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All chips were currently using gm20b_gr_clear_sm_error_state
It was wrong for chips based on volta and later as the implementation didn't
consider non pes-aware vsms mapping
Add new HAL implementation for clear_sm_error_state for volta based and later
chips to fix this.
Bug 200448172
Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837188
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FB reset is done by accessing MC register. Move the code to MC unit.
JIRA NVGPU-954
Change-Id: I1636887af805f016da5490af65e808f9ac015cde
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823385
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Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.
JIRA NVGPU-954
Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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1. Implement the following vgpu functions to support clk-arb:
- vgpu_clk_get_range() to return min and max freqs from
supported frequencies
- implement vgpu_clk_get_round_rate() which sets rounded
rate to input rate. Rounding is handled in RM Server
- modify vgpu_clk_get_freqs() to retrieve freq table in IVM
memory instead of copying the value in array as part of cmd
message.
2. Add support for clk-arb related HALs for vgpu.
3. support_clk_freq_controller is assigned true for vgpu
provided guest VM has the privilege to set clock frequency.
Bug 200422845
Bug 2363882
Jira EVLR-3254
Change-Id: I91fc392db381c5db1d52b19d45ec0481fdc27554
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812379
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Nvgpu uses many ways to check if sync points are enabled. The four
ways used to be:
platform->has_syncpoints
g->has_syncpoints
nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS)
gk20a_platform_has_syncpoints()
This patch standardizes all usage to now be nvgpu_has_syncpoints()
which is based on gk20a_platform_has_syncpoints() - just renamed to
be general to nvgpu.
All usage of the other forms have now been consolidated. However,
under the hood nvgpu_has_syncpoints() does check the is_enabled
flag. This flag is now set where g->has_syncpoints used to be set
based on the platform data.
The basic dependency chain is this:
nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS ->
platform->has_syncpoints
However, note: there are several places where syncpoints can be
disabled if some other driver initialization fails (for ex. host1x).
Also note that nvgpu_has_syncpoints() also considers a disable
variable set by debugfs.
Bug 2327574
Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803975
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Add a -j argument to enable running unit tests on several
threads. Also adds signal handling to prevent a fatal
error in one thread from killing the whole unit test
framework.
JIRA NVGPU-1043
Change-Id: I891a547640cd005a50ffa5c06367ed46c54de012
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1847740
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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-Add support to load dbg/prod mem_unlock ucode
based on debug Signal SCP_CTL_STAT_DEBUG_MODE.
-Defined MEM_UNLOCK_PROD_BIN & MEM_UNLOCK_DBG_BIN
to hold dbg/prod ucode names.
JIRA NVGPUT-76
Change-Id: Ie282a281fe502ada31a69e3b3c734e9a3a725395
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1842880
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Disable ELCG as it is not POR for GV100
Disable in Platform data for SKU250
Bug 200446261
Change-Id: I70bddf450c7e41e91498c613f315e0c82ac5e8e2
Signed-off-by: absalam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828022
Reviewed-by: Automatic_Commit_Validation_User
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- Depending on main context or subcontext,
ctxheader and gr_mem should be updated
with pm mode and buffer addresss accordingly
Bug 2404093
Change-Id: Iba16c762c09b2a420570d4f528205e258ff27e8f
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849396
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-Removed _dmem postfix to some functions which
can be common for DMEM & EMEM queue, and
made changes as needed.
-Defined flcn_queue_push_emem() &
flcn_queue_pop_emem() functions to
to read/write queue data to/from EMEM
-Defined flcn_queue_init_emem_queue()
function to assign EMEM specific functions
to support EMEM queue type.
-Defined QUEUE_TYPE_DMEM to support
DMEM based queue.
-Defined QUEUE_TYPE_EMEM to support
EMEM based queue.
-Modified nvgpu_flcn_queue_init() to call queue
type flcn_queue_init_dmem/emem_queue()
function to assign its ops.
JIRA NVGPU-1161
Change-Id: I06333fa318b7ca4137c977ad63f5a857e7b36cc8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1841084
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-Added HAL copy_from_emem & copy_to_emem to struct
nvgpu_falcon_engine_dependency_ops data struct to point to
engine specific EMEM access functions.
-Added function nvgpu_flcn_copy_from_emem() &
nvgpu_flcn_copy_to_emem() at interface layer to
access EMEM using flacon engine EMEM HAL's.
JIRA NVGPU-1161
Change-Id: Ifb72a617277e73f25f1772c969791b642585e7fb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Creates sysfs nodes to read clk freq on GV100
Following sysfs nodes are created: gpcclk,xbarclk,sysclk
Uses default clock source and counters for measurement
Bug 200446261
Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662
Signed-off-by: absalam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828030
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ic434301441bf43f9eaff43500afb696e4e1395ae
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819014
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809757
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in the
include directory by renaming them to follow the convention,
'NVGPU_HEADER_H'.
JIRA NVGPU-1028
Change-Id: I0289a168252595d17ac47c5ed32cabc4eea33e25
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809755
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809751
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- TPC powergating should be done before
calling gk20a_enable_gr_hw.
gk20a_enable_gr_hw() issues a GR engine reset.
Without this fix, enabling 1 TPC from each PES
causes ctxsw timeout error while running GFX Benchmark.
- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
TPC Config - TPC-MASK
4 TPC configuration - 0x0
3 TPC configuration - 0x1/0x2/0x4/0x8
2 TPC configuration - 0x5/0x9/0x6/0xa
- We should not write to gr_fe_tpc_pesmask_r()
as part of TPC-PG sequence. This register is for
debug purpose only.
Bug 200442360
Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Bootstrap size of 256M is insufficient on some platforms, hence
increase it to 512M
Bug 2402730
Bug 200448236
Change-Id: I5f67e76db0e37d2044f5fc3c27014d6fda853abd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1845051
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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No one is checking return values for the *get_litter_value()
functions in the 100s of references, and some of the *get_litter_value()
functions were already doing a BUG(), we'll just call BUG() in all them.
And since we don't return in the error case, and there's no guarantee
that an errno won't collide with the litter values, we'll just
initialize the local ret value to 0 to avoid problems and confusion.
JIRA NVGPU-647
Change-Id: Id974c904a142c4b3abf1ab940121c270208b0b83
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1830582
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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