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* gpu: nvgpu: gp10b: enable gpu rail gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | Bug 1698618 Change-Id: Iabfd726891165d7879376ab96445b7b81b907153 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/841856 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable adaptive ELPGMahantesh Kumbar2016-12-27
| | | | | | | | | | | | ELPG is enabled on TOT. Bug 200144583 Change-Id: Icbdcb5f575a4ca37becf47b098fbd6a1f89feec7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1013845 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC stats sysfs nodesAdeel Raza2016-12-27
| | | | | | | | | | | Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pass channel pointer to handle sm exceptionDeepak Nibade2016-12-27
| | | | | | | | | | | | | Pass faulting channel pointer to gr_gk20a_handle_sm_exception() instead of NULL Bug 200156699 Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1011289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | fix below sparse warning : drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol 'gr_gp10b_pre_process_sm_exception' was not declared. Should it be static? Bug 200088648 Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1009938 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: vgpu: fix sparse warningsRichard Zhao2016-12-27
| | | | | | | | | | | Bug 200088648 Change-Id: I61be7b4787e9bc9bac310a8739977f43c38a67ee Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1000174 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post events on all channels of TSGDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | While posting CILP preemption complete event to user space, raise the event to all channels of TSG (if channel is part of TSG) This is a WAR until we have proper sync mechanism with user space to raise CILP events Bug 200156699 Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1001696 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add CILP support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: mask hww_warp_esr for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add API gp10b_mask_hww_warp_esr() to mask hww_warp_esr appropriately on gp10b Bug 200156699 Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/927129 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC supportAdeel Raza2016-12-27
| | | | | | | | | | | | | Add ECC exception handling support for SM, TEX, and LTC. Bug 1635727 Bug 1637486 Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935362 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: clean-up pmu init operationsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Removed unwanted initlization of function pointer. Bug 200157852 Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/843218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable power gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Enable engine level power gating(elpg) Bug 200144583 Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/818637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add delay cycles before engine gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | For copy engine, add 16 clock cycle delay before engine clock gating. Bug 1717152 Change-Id: Ife92299c052f44000bc0d900f0129a2eab13f3b5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/998408 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable gradual slowdownSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Enable gradual slowdown for gp10b and also correct thermal slowdown factors with extended mode. Bug 1719974 Change-Id: I31a5d7df71c98135273a980c49b70bc76fac0b40 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/933279 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: bitmap allocator for comptagsKonsta Holtta2016-12-27
| | | | | | | | | | | | | Restore comptags to be bitmap-allocated, like they were before we had the buddy allocator. Bug 200145635 Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/839240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable semaphore acquire timeout for gp10bRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | | It'll detect dead semaphore acquire. The worst case is when ACQUIRE_SWITCH is disabled, semaphore acquire will poll and consume full gpu timeslicees. The timeout value is set to half of channel WDT. Bug 1636800 Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/928830 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Refresh regops whitelistTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Context & global whitelists are same, so delete second copy. Update the list. Bug 200164983 Change-Id: I440ce04316120b8128baeabc002c55436cf41d5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/931178 GVS: Gerrit_Virtual_Submit Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com>
* gpu: nvgpu: vgpu: update interface to free GR ctxAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | | The server only releases ownership of the ctxsw buffer mappings after the GR ctx has been released. Update the sequence to account for this. JIRA VFND-1117 Bug 1708163 Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/922817 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r()David Li2016-12-27
| | | | | | | | | | | | | gr_*__set_alpha_circular_buffer_size() left max_batches field of gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta transitions and poor performance when tessellation or geometry shaders are used Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/840079 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix set_circular_buffer_sizeDavid Li2016-12-27
| | | | | | | | | | | | | | | It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r causing a GPU MMU fault when used. Bug 200141640 Bug 200141981 Bug 200141640 Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/807694 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Recreate HW headersTerje Bergstrom2016-12-27
| | | | | | | | | | | Add gradual slowdown registers, and fix names for L2 flush registers. Change-Id: If085c4febef494ae299d2147ca5201cd373bee0b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/839369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gp10b: Add tile caching registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Add tile caching registers to access map. Bug 1692373 Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/812352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gp10b: Install gp10b access mapTerje Bergstrom2016-12-27
| | | | | | | | | | | Bug 1692373 Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/812351 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: t18x: make gp10b_freq_table staticSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Make gp10b_freq_table static to fix sparse warning Bug 200088648 Change-Id: Ibaaabd145e37685e049ac3a49e2b276fb6545d0e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/837421 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ELPG prod values updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | Bug 200151348 Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/836877 (cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193) Reviewed-on: http://git-master/r/837228 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add support for freq scalingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Add support for gp10b freq scaling. Bug 200147662 Reviewed-on: http://git-master/r/816962 (cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438) Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/834758 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: User-space managed address space support (gp10b)Sami Kiminki2016-12-27
| | | | | | | | | | | | Tell gk20a_init_vm() that bar2 VM is kernel-managed. Bug 200077571 Change-Id: I151c540a6dec76238e7959f745cfca280927f2d4 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/746803 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: correct initial gpcclk rateSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Set initial gpcclk rate to 1GHz. Bug 200151332 Reviewed-on: http://git-master/r/834113 (cherry picked from commit 9ed69164da7afeec20c3a557885f74db4cbea9cb) Change-Id: I85107eb5852b25977b30663f6ae173b271ecafeb Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/834322 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ZBC update without idleTerje Bergstrom2016-12-27
| | | | | | | | | | Do ZBC updates without forcing engine idle first. Bug 1698013 Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/829146
* Revert "gpu: nvgpu: gp10b: Force always SMMU bypass"Terje Bergstrom2016-12-27
| | | | | | | | | This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2. Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1 Reviewed-on: http://git-master/r/830854 GVS: Gerrit_Virtual_Submit
* arm64: tegra: dts: Use new SID dt-bindingsAlex Waterman2016-12-27
| | | | | | | | | | | | Use bindings more specific to the ARM SMMU. Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/812438 (cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0) Reviewed-on: http://git-master/r/831515 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheableAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add L2 clean comptags regsTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Bug 1698618 Change-Id: I5bad939d94171d2296897260043f0e67e43802e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/829097 (cherry picked from commit a067cfeb8dda03641ba981d86bef93fa9041e18e) Reviewed-on: http://git-master/r/829414 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: set correct page size index for gp10bRichard Zhao2016-12-27
| | | | | | | | | | | | | | | VM server only know big page and small page, so convert gmmu_page_size_kernel to according page size index. JIRA VFND-890 Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/816359 (cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421) Reviewed-on: http://git-master/r/827131 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* Revert "gpu: nvgpu: gp10b: Implement sparse PDEs"Terje Bergstrom2016-12-27
| | | | | | | | | | | | | This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It introduces regression in T124. Bug 1702063 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b Reviewed-on: http://git-master/r/830787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: set ptimer source frequencySeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | | Set platform data with ptimer source frequency. Removed ptimerscaling10x platform data, and use ptimer source frequency to calculate ptimerscaling factor. Reviewed-on: http://git-master/r/819031 (cherry picked from commit 6849603024943184b0463233bedd95934c353663) Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/827301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement sparse PDEsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/758653
* gpu: nvgpu: gp10b: update thermal programmingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | | | Add required fileds and values for thermal slow-down settings in thermal header file and corrected thermal register programming with correct values. Bug 1695567 Reviewed-on: http://git-master/r/822200 (cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981) Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/823013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: support to remove bar2 vmSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Implement function to support bar2 vm clean-up. Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/814573 Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/815428 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable clock gating featuresSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Enable clock gating power features: slcg, blcg and elcg Bug 200144583 Reviewed-on: http://git-master/r/821149 (cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce) Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/818636 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add interface to alloc ctxsw buffersAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | | gp10b introduces support for preemption (GfxP and CILP). Add a new interface to allow allocating buffers needed to support this functionality. Bug 1677153 Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/806963 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/817039 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Fix support for new color compression kindsSami Kiminki2016-12-27
| | | | | | | | | | | | | | Fix support for kinds C32_MS4_4CBRA and C64_MS4_4CBRA. They're both compressible and ZBC kinds, so mark them as such, too. Change-Id: Ide09ea79a885361ecfc3c188606799c6b2fbdd2e Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/816015 (cherry picked from commit 302b06b76aed5278286487225d6e7280b747d4b3) Reviewed-on: http://git-master/r/816014 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUTTerje Bergstrom2016-12-27
| | | | | | | | | Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value written in gk20a_init_gr_setup_hw() instead of hard coding here. Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/813959
* gpu: nvgpu: add h/w headers for pbdma_methodsDeepak Nibade2016-12-27
| | | | | | | | | | | Bug 200134238 Change-Id: I263a12b7a3a74d1ab07bca03d5dda685b1e4f22f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/815128 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: create fault buffer only onceSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Create only one instance of replayable fault buffer mapping. Change-Id: Id766298f338ce54cfca7510cbb9e4528ef1945a3 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/814615 (cherry picked from commit 422d2ced384220668347dc8422876d75f6e8807d) Reviewed-on: http://git-master/r/817696 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b non-secure gpmu hw initMahantesh Kumbar2016-12-27
| | | | | | | | | | call gp10b_init_pmu_setup_hw1 during non-secure boot only. Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/815843 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Make CB size and default size sameTerje Bergstrom2016-12-27
| | | | | | | | | | | | | We used to allocate 1.5x buffer size. This leads to memory waste, as we do not set the CB size via SW methods anymore. Bug 1686189 Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801865 (cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2) Reviewed-on: http://git-master/r/815683
* gpu: nvgpu: gp10b: Fix beta CB sizingTerje Bergstrom2016-12-27
| | | | | | | | | | | | Handle beta CB sizing differences for GfxP versus WFI channels. Bug 1686189 Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801533 (cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4) Reviewed-on: http://git-master/r/815682
* gpu: nvgpu: gp10b: Report Pascal DMA copy classTerje Bergstrom2016-12-27
| | | | | | | | | | | | Announce supporting Pascal DMA copy class instead of Maxwell. Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/808140 (cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7) Reviewed-on: http://git-master/r/815679 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Fix spill buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Spill buffer size is in chunks of 256B. Multiply the size by granularity to get the size in bytes. Bug 1686189 Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801344 (cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0) Reviewed-on: http://git-master/r/815680
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 03:44:33 -0400