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* nvgpu: pmu: Assign pmu_queue_get_head/tail ops.Deepak Goyal2017-01-31
| | | | | | | | | | | | | | pmu_get_queue_head/tail & pmu_get_queue_head/tail_size ops are defined for gv11b chip. JIRA GV11B-30 Change-Id: Iae139732d9f68f93e3c197469c04ccd3f0d63ce7 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1285749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: add regops whitelistsseshendra Gadagottu2017-01-27
| | | | | | | | | | | | Add regops whitelists for gv11b. JIRA GV11B-35 Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1295401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update zcull and pm pointersseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | | | | | | Update zcull and perfmon buffer pointers in context header. For gv11b maximum 49 bits gpu va possible. But, zcull and perfmon buffer pointers uses maximum 41 bit va address (258 bytes aligned). To accommodate this, high pointer registers needs to be updated in context header. JIRA GV11B-48 Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1291852 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: gv11b: update clock gating prod settingsseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | Update clock gating setting till HW CL#37750038 JIRA GV11B-15 Change-Id: I98c4a157df979c944122f4a7b05e3e692a28fe2f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1294824 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: restore golden contextseshendra Gadagottu2017-01-20
| | | | | | | | | | | | | | | | Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: sw methods for shader exceptionseshendra Gadagottu2017-01-18
| | | | | | | | | | | | | Added proper sw methods handling of shader execptions for gv11b. Bug 1834201 Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1283729 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gv11b's wait_idle()Alex Waterman2017-01-18
| | | | | | | | | | | | | | | | The interface for wait_idle() was changed for gk20a, etc, so this change is necessary to update the wait_idle function for gv11b. Similarly for wait_fe() - this needs to no longer use an end_jiffie argument. Bug 1799159 Change-Id: I192159feffda5476269194e7d6ef15b5fe3055bd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280459 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Support Stencil ZBCSeema Khowala2017-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gv11b: support for multiple runlistsseshendra Gadagottu2017-01-16
| | | | | | | | | | | | | Add support for multiple runlists in gv11b. Bug 1834201 Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1285044 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw header for CL 37750038 and mmu faultSeema Khowala2017-01-12
| | | | | | | | | | JIRA GV11B-7 Change-Id: I32428e6b91050ad3f697eb80e2aabda2cc1bfda4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1249339 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gv11b: Add non secure PMU bootstrap().Deepak Goyal2017-01-05
| | | | | | | | | | | | | | pmu_bootstrap() does not support gv11b PMU non-secure boot. gv11b_pmu_bootstrap function is added with the updated/new args. JIRA GV11B-30 Change-Id: I42c1a7bd77d75c6e59ee4cc695cc879ce7cec095 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1259271 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: hw header update for CL37750038Seema Khowala2017-01-02
| | | | | | | | | | Change-Id: I7ca3d9968dc37b6514a08d3f49b6d2353e11671d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1277786 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add clock gating prod settingsseshendra Gadagottu2016-12-21
| | | | | | | | | | JIRA GV11B-15 Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1266705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: legacy support with subcontextseshendra Gadagottu2016-12-20
| | | | | | | | | | | | | | | | | gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw header update for CL37510769Seema Khowala2016-12-05
| | | | | | | | | | | Change-Id: Ie25197e9bc08088ff837677d72fa8c28828f0bf4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1263414 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2016-11-30
| | | | | | | | | | | | | | | | | Fix following sparse warning by making function as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5: warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared. Should it be static? Bug 200088648 Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1261891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement mm_setup_hwseshendra Gadagottu2016-11-29
| | | | | | | | | | | | | Reuse gk20a_mm_setup_hw for gv11b. JIRA GV11B-21 Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254939 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set ce context validseshendra Gadagottu2016-11-21
| | | | | | | | | | | | | | | Set copy engine context valid for channel loaded on pbdma. JIRA GV11B-21 Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254916 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: chip specific init_inst_blockseshendra Gadagottu2016-11-21
| | | | | | | | | | | | | Remove va limits for inst block in gv11b. JIRA GV11B-21 Change-Id: I5338e2d64b3bbebeb5e309d63db3e8360ae05723 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254880 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: support for new littler valuesseshendra Gadagottu2016-11-17
| | | | | | | | | | | | | | | | | Add support for new litter values: GPU_LIT_NUM_SUBCTX GPU_LIT_NUM_SM_PER_TPC Also updated get_litter_value api to use int instead of enum type. JIRA GV11B-21 Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254857 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: use fuse control read/write APIs for K4.4Shardar Shariff Md2016-11-11
| | | | | | | | | | | | | | Use fuse control read/write APIs when accessing fuse control registers for Kernel version 4.4 Bug 200243956 Change-Id: I3d78ec2733b5f56615fa0b588664570c85557e63 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245826 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: hw headers for mmu faultSeema Khowala2016-11-07
| | | | | | | | | | JIRA GV11B-7 Change-Id: Ib50c4266a1a9d05b98bf4cbef663b534289055ed Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1249156 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: hw headers for mmu faultSeema Khowala2016-11-03
| | | | | | | | | | | | | JIRA GV11B-7 Change-Id: I9d1a530c668cc3b9e27a6efb4761f68916e85b43 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1246513 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: smid programmingseshendra Gadagottu2016-11-03
| | | | | | | | | | | | | | gv11b specific smid table init, smid numbering and smid programing. JIRA GV11B-21 Change-Id: I3a0f8355f2cd90ab1518cd8a5642a0e84202bdf8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1227096 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add dbg_session_opsseshendra Gadagottu2016-11-01
| | | | | | | | | | | JIRA GV11B-21 Change-Id: Ib9c099fb0f9cf910bd5abfc9fd6010803b52c9f8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1244768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: commit global timesliceseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | | Implement chip specific commit_global_timeslice function. JIRA GV11B-21 Change-Id: I4f852913cb181f62063084c4e118d97148f99056 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243947 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: pmu HAL updateseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | | | | Update pmu HAL to have function for is_pmu_supported(). At this moment pmu support is disabled for gv11b. JIRA GV11B-21 Change-Id: I1790e6e4dc80e0761df78e6092da2b6ca0e39d64 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243919 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: bl compressionSeema Khowala2016-10-25
| | | | | | | | | | | | | updated mmu pte kind JIRA GV11B-8 Change-Id: I2baff42e077411a9c72b0d10739f4a45d4bd79a7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1234567 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: enable correct interruptsseshendra Gadagottu2016-10-21
| | | | | | | | | | | | | | | | Enable stall and non-stall interupts for gv11b. Support for replayable interrupts will be added later. Hub interrupts are not enabled and they will be enabled after non-replayabale fault handling is in place. JIRA GV11B-11 Change-Id: I99cc470dae9d02f92e9fb3cb49186dabfed78875 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1239337 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update ramfcseshendra Gadagottu2016-10-21
| | | | | | | | | | | | | | | Updated ramfc: - To include channel veid info - Set valid context bit - Enabled userd writeback JIRA GV11B-11 Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237764 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update gr cb callbacksseshendra Gadagottu2016-10-19
| | | | | | | | | | | | | Update gr cb callbacks with gv11b default sizes. Also updated sw method ids for volta. JIRA GV11B-11 Change-Id: I77cccedb7a017f378e2194cef98ea4b0bf7acd6b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237786 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: avoid host1x device dependencyseshendra Gadagottu2016-10-19
| | | | | | | | | | | | | gpu is completely out from host1x block and no need to create device nodes under host1x. Bug 1735760 Change-Id: I2df861b07b38ce6931a86a928184ad164095948a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1181063 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update sm arch infoseshendra Gadagottu2016-10-18
| | | | | | | | | | | | | | Use updated register offset for gr_gpc0_tpc0_sm_arch_r() to read and update correct sm arch info. JIRA GV11B-21 Change-Id: I34af2d4a7665d7848bd74bc56a92ff2c861ceac9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237916 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: enable gpc exceptionsSeema Khowala2016-10-17
| | | | | | | | | | | | | | Add function ptr and function for enabling gpc exceptions. Disable Tex exceptions. JIRA GV11B-28 JIRA GV11B-27 Change-Id: Ife8fe22c24da00ae14f68fd977d84d208831eb45 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1236899 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2016-10-17
| | | | | | | | | | | | | | | | Fix following sparse warning my making funtion as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:23:6: warning: symbol 'gv11b_mm_is_bar1_supported' was not declared. Should it be static? Bug 200088648 Change-Id: I4af7ed1ae112813887a14a11b8fcea0b72c90e39 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1236689 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: remove tex exceptionSeema Khowala2016-10-17
| | | | | | | | | | | | update for CL#37320141 JIRA GV11B-27 Change-Id: I095af59ac419b44b3a1e3abc489857d6f533874a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1236274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: header update for CL#37320141Seema Khowala2016-10-17
| | | | | | | | | | | | | | | | Hardware header updates for CL#37320141 JIRA GV11B-27 JIRA GV11B-7 JIRA GV11B-8 JIRA GV11B-9 Change-Id: I54d467f42d4074d1d9ae912f6d46ab2e323f69bc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1236263 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: zcull programmingSeema Khowala2016-10-14
| | | | | | | | | | | | | Bug 1735760 Change-Id: Id801efb613b5740389bde5dc2cfff47232d0a0f3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1221582 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: program sw veid bundlesseshendra Gadagottu2016-10-14
| | | | | | | | | | | | | Program hw state with relevant sw veid bundles. JIRA GV11B-11 Change-Id: I2c5e02016ed41db9c9b7f85cc0b401abaa003d37 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231598 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b : add mm and tsg initSeema Khowala2016-10-14
| | | | | | | | | | | | | Bug 1735760 Change-Id: I6b33b38ed555759a57ad170e7f75839df51da228 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1207273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: setup rop mappingsseshendra Gadagottu2016-10-12
| | | | | | | | | | | JIRA GV11B-21 Change-Id: I7695936bdac4502ceb0bdad4fc029e249eb2f05d Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1224783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sysmem userd supportseshendra Gadagottu2016-10-11
| | | | | | | | | | | | | | | | | | | For gv11b, userd is allocated from sysmem. Updated gp_get and gp_put functions to read or write from sysmem instead of bar1 memory. In gv11b, after updating gp_put, it is required to notify pending work to host through channel doorbell. JIRA GV11B-1 Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1226613 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: kernel hw header updateseshendra Gadagottu2016-09-29
| | | | | | | | | | | | | Kernel hardware headers updtae related to ctxsw, ramfc and pbdma. JIRA GV11B-21 Change-Id: I99588b420a814068eaf894e999a8ad8e6234e26c Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1228760 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: header updates for CL#37119043Seema Khowala2016-09-28
| | | | | | | | | | Bug 1735760 Change-Id: I5216863a25338f14498ae0be58b86993104d4e99 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1222031 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: gv11b: create modified runlistseshendra Gadagottu2016-09-21
| | | | | | | | | | | | | | | Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Add NVIDIA-REVIEWERS file for nvgpu-t19x moduleBharat Nihalani2016-09-19
| | | | | | | | | | | | This is done to designate nvgpu-t19x module owners so as to help with tools like Coverity and Code Coverage. bug 200195707 Change-Id: I1f75c11392c74372112018ed3f8fc882dd676bc4 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/1220031 Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gv11b: hw header updateseshendra Gadagottu2016-09-12
| | | | | | | | | | | | | | Updated hw headers to CL#37001916. Some of important changes include new door bell user mode mechanism and new runlist structure. Bug 1735765 Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1205888 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: send only one event to the debuggerCory Perry2016-09-01
| | | | | | | | | | | | | | | | | | | | | | Event notifications on TSGs should only be sent to the channel that caused the event to happen in the first place, not evey channel in the tsg. Any more and the debugger will not be able to tell what channel actually got the event. Worse yet, if all the channels in a tsg are bound to the same debug session (as is the case with cuda-gdb), then multiple nvgpu events for the same gpu event will be triggered, causing events to be buffered and the client to get out of sync. One gpu exception, one nvgpu event per tsg. Bug 1793988 Change-Id: Ifb33b65f09f67b0e323917c7e7ea016fc3676f18 Signed-off-by: Cory Perry <cperry@nvidia.com> Reviewed-on: http://git-master/r/1194207 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:40:44 -0500