| Commit message (Collapse) | Author | Age |
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We can trigger CILP only if SM debug mode is on.
So in fecs interrupt handler, we could have graphics context
running for which SM debug mode is disabled.
And in that case we skip posting of cilp completion
events to UMD.
But since CILP event was anyways triggered, we need to post
events to UMD irrespective of SM debug mode is enabled
at that point or not
Hence remove check gk20a_gr_sm_debugger_attached() for
posting events to UMD
Bug 200243092
Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1263591
(cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600)
Reviewed-on: http://git-master/r/1264780
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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gp10b does not have an fbpa unit, although the
hw header files claim it does. Hardcode all fbpa
values to 0.
Bug 200249125
Change-Id: I6ed63b3231d7af8e31ccf5047d56bdb85f05a9d9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1256422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bug 1838549
Change-Id: I40457aebd49a02d0dd54d6dc9c965f89613ee21f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1251371
(cherry picked from commit 2c80f36830baf48bab043d7f1ebbcbe7759789c4)
Reviewed-on: http://git-master/r/1251452
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA GV11B-21
Change-Id: I3e2cb2384b6a26ba339a79d38c91dd47480fe6a6
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254876
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gp10b_ce_nonstall_isr(), we trigger a semaphore wakeup.
Currently, we clear the interrupt status register after the
wakeup is complete. There is potential for an interrupt to
come in while the wake-up operation is in progress, and it
is possible that:
1) We miss processing the interrupt in that ISR iteration AND
2) We clear the interrupt status register anyways
This change clears the status register before triggering wakeup,
so the interrupt will properly re-fire.
Bug 200244458
Change-Id: Ia3338252eeea4eb60d11c0e241279989a46dac04
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1253107
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add FBPA base addresses
Bug 200249125
Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1247802
(cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a)
Reviewed-on: http://git-master/r/1252163
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Hard code RX bias current to 0x2.
Bug 1833830
Change-Id: I1107bad52de7b38d311bc5795739777a4bb4239a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1253656
(cherry picked from commit 7e853b0c62043cc53847e3535e05886d574dc779)
Reviewed-on: http://git-master/r/1255724
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Expose the currently hard coded boot frequency, which is at the same
time the max frequency. We use it for filling in GPU characteristics.
Bug 200251486
Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252906
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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get_litter_value API is updated to use int instead of
enum type.
JIRA GV11B-21
Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1252212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent
such problems from occuring in future.
Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GPU frequencies can be set by powerhal when GPU is railgated,
and before this change that would cause EMC floors to remain
set until GPU is unrailgated.
After this change, EMC floors are not requested by the GPU
client when the GPU is railgated. It is ok to ignore the
requests, as the GPU client maxes the floor when powering
up.
Bug 1807560
Change-Id: I9a0d58b0288edbd03b2edf09580ecabd9b74f0c2
Signed-off-by: Juha Lainema <jlainema@nvidia.com>
Reviewed-on: http://git-master/r/1216233
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Cyril Raju <craju@nvidia.com>
Tested-by: Cyril Raju <craju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add regops whitelists for gp106. The whitelist is generated, and is the
same for context switched and global registers.
Bug 200239422
Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1243253
(cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db)
Reviewed-on: http://git-master/r/1247645
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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If gk20a_init_pmu() fails, go to the error path that frees pmu_sig.
Change-Id: I2f6fcb86570aba54ab45aec14ee6f341e3faebd5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249971
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Due to missing break statements, GPC base and GPC shared base were
overwritten by values in following select cases.
Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249970
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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- Define fuse macros depending on kernel version as fuse
offset got changed in K4.4 and for K4.4 fuse defines are
defined in common header file (tegra-fuse.h)
- Use fuse control read/write APIs when reading control
registers for K4.4
Bug 200243956
Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1245825
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Added PMU thermal slct RPC handling for WARN_TEMP threshold
configuration.
JIRA DNVGPU-130
Change-Id: Iac96557080907bd091217fe983d6a951d0be1da4
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1242133
(cherry picked from commit 8bca85490e716b974315093c47d0d54ec5fb7e0f)
Reviewed-on: http://git-master/r/1246213
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The following CL contains the following VBIOS thermal table parsing
and PMU interface support.
1) Thermal device table
2) Thermal channel table
JIRA DNVGPU-130
Change-Id: Ie3abab4bf099a022b1b59db96811c2ed44079519
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1240630
(cherry picked from commit 814962a4be0a8cd0cddc7bc5211c62308ab1fea2)
Reviewed-on: http://git-master/r/1246210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add implementation for PMU HAL is_pmu_supported to gp106.
JIRA GV11B-21
Change-Id: If4268465ffade7c3c8e7bb853a1d2070c0e2ae4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1246026
Tested-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Update pmu HAL to have function for
is_pmu_supported.
JIRA GV11B-21
Change-Id: Id08efa82aa04a6f92c7fea0eb5d4735db2699b5a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1243918
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-120
SRAM rail voltage needs to be picked up from SRAM
index of VF entries in CLK prog table.
Change-Id: Iabfff62edeec5aa9c2ead62d6b943fb2ebb952ed
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1227665
(cherry picked from commit 8053260438bc94397b20e74cf18453624ebeb325)
Reviewed-on: http://git-master/r/1244664
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- calculate raw period as per pwm source
- update pwm source for logic & sram rails.
JIRA DNVGPU-123
Change-Id: I50b41d51b6aba760710700522dced7859f815463
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1227626
(cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4)
Reviewed-on: http://git-master/r/1244663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Read voltage tables from VBIOS & construct
then send to PMU.
- compare & set voltage based on
mclk/gpc2clk clk, take higher voltage
between two & set.
JIRA DNVGPU-122
Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224365
(cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c)
Reviewed-on: http://git-master/r/1244657
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- changes to read voltage tables from VBIOS
& create boardobj then send to pmu
- Rail, Device & Policy objects are read from VBIOS & created boardobjs
- RPC support to load, Set & get voltage.
JIRA DNVGPU-122
Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222774
(cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac)
Reviewed-on: http://git-master/r/1244656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Parse VBIOS performance table to retrieve clock ranges.
Jira DNVGPU-125
Change-Id: Ia8e4ede158de5c5374205a510099d00b497fe1a6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1218935
(cherry picked from commit b5b7c789e98a20eb4cc5c30f0e2eb45d4a882cc4)
Reviewed-on: http://git-master/r/1232593
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added SW_THRESHOLD policy support for over power protection.
JIRA DNVGPU-70
Change-Id: I7a9d202619c997d6cab6fb750db7f3018229b2fd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1233055
(cherry picked from commit b233c74b9ba4a3802f111757aecf24a27c830fc1)
Reviewed-on: http://git-master/r/1241960
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.
JIRA DNVGPU-47
Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Implement HAL callback set_preemption_mode
Bug 200238497
JIRA VFND-2683
Change-Id: I8fca8e1ba112d8782ce18f0899eca38a1d12b512
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1236976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gm20b_init_fb already calls gm20b_init_uncompressed_kind_map()
and gm20b_init_kind_attr().
JIRA GV11B-8
Change-Id: Id72ee1ae04d3a47ae7a6a972f6d8bd7e7bda7389
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1234570
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-123
now a function can be called with GPC2CLK value
It will take care calculating slave clock values
and calling VF inject to program clock
Made programming of boot clock code to use this
newly created function.
Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1221976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235056
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JIRA DNVGPU-123
Function will copy possible clock points for
a given master clock domain to pointer passed.
pointer with NULL value and count of zero can be passed
to query number of clock points for a given domain so that
memory can be allocated and function called again to
fill clock points
Change-Id: Iec6206f23789980036be99793599e934bd221035
Reviewed-on: http://git-master/r/1218912
(cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9)
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1235055
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-123
function was added to retrieve V for F or
F for V for a given clock domain.
Clock domain can be master or slave.
F or V can be intermediate point between two
successive V or F values in VF table.
VF table should be cached before calling this function.
A F value below Fmin will return Vmin.
F > Fmax will return error
A V value above Vmax wil return F max.
A V value below Vmin will return error.
Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1211234
(cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa)
Reviewed-on: http://git-master/r/1235054
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-118
Change-Id: I5c6a919d18e6de077e03180ba70441cfc9791350
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1209849
(cherry picked from commit 469f35e3f65964a3402f7e0c49862bd44b68936a)
Reviewed-on: http://git-master/r/1233040
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Make channel_gp10b_commit_userd global, so other
gpus can re-use that function.
JIRA GV11B-11
Change-Id: Ibe03063befc2da6c67822121f880a141cad46e84
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1237738
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We need to wait for scrubber to have finished before we can allow
any accesses to memory. Do the wait in place where on iGPU we would
do FB reset.
Bug 1799537
Bug 1815139
Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235541
(cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc)
Reviewed-on: http://git-master/r/1239955
GVS: Gerrit_Virtual_Submit
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bug 200088648
sparse warning reported that the function was not
defined. This was due to a missing include
Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1237845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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* Parsing of shadow registers from VBIOS
* Partial devinit engine interpreter implementation
JIRA DNVGPU-117
Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1214956
Reviewed-on: http://git-master/r/1237293
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement gp10b and gp106 ELCG programming.
JIRA DNVGPU-74
Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1220431
(cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f)
Reviewed-on: http://git-master/r/1239422
GVS: Gerrit_Virtual_Submit
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Bug 1826768
Change-Id: I8be2b9c074868206cb95b3bc84d66ea84683b19a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1237522
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Cory Perry <cperry@nvidia.com>
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Implement the basic code to swap between PCIe bus speeds for the GPU.
Other GPUs are not supported yet. Currently the following speeds can
be used:
Gen1 (2.5 MTPS)
Gen2 (5.0 MTPS)
gp106 on DPX2 does not support Gen3.
JIRA DNVGPU-89
Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499
Reviewed-on: http://git-master/r/1218177
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1227925
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The lowest page table level may hold very few entries for mappings of
large pages, but a new page is allocated for each list of entries at the
lowest level, wasting memory and performance. Compact these so that the
new "allocation" of ptes is appended at the end of the previous
allocation, if there is space.
Bug 1736604
Change-Id: I4c7c4cad9019de202325750aee6034076e7e61c2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1222810
(cherry picked from commit 97303ecc946c17150496486a2f52bd481311dbf7)
Reviewed-on: http://git-master/r/1234995
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added current temperature reading support for gp10x.
JIRA DNVGPU-48
Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1213717
(cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b)
Reviewed-on: http://git-master/r/1234092
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Suppress error message when nvgpu tries to load VBIOS overlay, but
one is not found. This situation is normal. This is done by moving
gk20a_request_firmware() to be nvgpu generic function
nvgpu_request_firmware(), and adding a NO_WARN flag to
it.
Introduce also a NO_SOC flag to suppress attempt to load firmware
from SoC specific directory in addition to the chip specific
directory. Use it for dGPU firmware files.
Bug 200236777
Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1223839
(cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d)
Reviewed-on: http://git-master/r/1233412
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Adds P5/P8 sequences and simple debugfs API to
change from P0->P5
JIRA DNVGPU-117
Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1208655
(cherry picked from commit dd410a86263e2407e043743945cf09a77910d745)
Reviewed-on: http://git-master/r/1231035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Bootloader of PMU is changed & bootloader
takes params using flcn_bl_dmem_desc_v1
descriptor to boot PMU
JIRA DNVGPU-116
Change-Id: I005b615b2323678fa605d190c6b9b629976f0b74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1212818
(cherry picked from commit 89976a03c13cce6bbba25c99270b0da4ca0f2441)
Reviewed-on: http://git-master/r/1223842
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- Clocks params update as per r370
JIRA DNVGPU-116
Change-Id: I0aaa1e275aaa2027f2839f3fe24c9aee3e14fd8d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1212827
(cherry picked from commit 54df6ad9668d46dffb5b9d03265948a47611ff13)
Reviewed-on: http://git-master/r/1227288
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Update to sequencer script to support SKU without display.
Bug 200231242
Change-Id: Ibd983166be823370fc687eb2fe9bae3aa8c0dab7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1207096
(cherry picked from commit b573a627b3fe7697c90def46eaf83d755c5d2dee)
Reviewed-on: http://git-master/r/1227247
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-72
JIRA DNVGPU-73
Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1215915
(cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390)
Reviewed-on: http://git-master/r/1227267
GVS: Gerrit_Virtual_Submit
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Prune non-existing registers from mclk shadow register list.
Bug 1799537
Change-Id: I8034a1820ef21e550616a5135856b05c2f375d6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208018
(cherry picked from commit cb988bb28dd914ea291cedec799d055f3d71d877)
Reviewed-on: http://git-master/r/1227266
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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FB is enabled in devinit. Skip resetting it in GPU boot.
Bug 1799537
Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208715
(cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698)
Reviewed-on: http://git-master/r/1227265
GVS: Gerrit_Virtual_Submit
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* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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