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* gpu: nvgpu: unit: update unit.h for targetPhilip Elcan2018-09-24
| | | | | | | | | | | | | | | | | The directory structure is every so slightly different on target, so this handles the differences. JIRA NVGPU-1042 Change-Id: I5a0566c7d371fcb5cd541c71841e8acedfaac6e2 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837443 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: move libnvgpu-drv.soPhilip Elcan2018-09-24
| | | | | | | | | | | | | | | | | This moves the libnvgpu-drv.so file on the systemimage to nvgpu_unit/build so it is in the right spot for the unit test framework. JIRA NVGPU-1042 Change-Id: I93a483d7c6f575c05756d3cd7d7a5b5591f0b8f8 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822289 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: build posix-bitops in tmakePhilip Elcan2018-09-24
| | | | | | | | | | | | | | | | | This builds the posix-bitops unit test shared library in the tmake build system for target. The systemimage output is in nvgpu_unit/build/units/libunit-posix-bitops.so JIRA NVGPU-1042 Change-Id: Id73a1f3e7d8de4e21e3a7f5c5bd036e0ce62ad3e Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822288 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: build in tmakePhilip Elcan2018-09-24
| | | | | | | | | | | | | | | | | This builds the nvgpu userspace in the tmake build system. The shared library and the unit test binary are built for target. The output goes to the systemimage in nvgpu_unit/build. JIRA NVGPU-1042 Change-Id: I70a118bc02789caf838b2b8e9d6778e94239c56f Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822287 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move tsg code to commonKonsta Holtta2018-09-24
| | | | | | | | | | | | | | | tsg_gk20a.c doesn't depend on any specific hardware, so move it to the common directory. Rename the posix tsg file to posix-tsg.c. Jira NVGPU-967 Change-Id: I6e8908a8f6cf43132db8dffe3a99e424e4f764b1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821509 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Add mockio unit testNicolas Benech2018-09-24
| | | | | | | | | | | | | | | | | Add a unit test to make sure the posix IO mocking works corretly. JIRA NVGPU-1040 Change-Id: Iadec2f515c9dd74dc0723885b3a6560dc91ce052 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741954 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Add low level unit test IO mockingNicolas Benech2018-09-24
| | | | | | | | | | | | | | | | | | Add an interface that the unit test modules can use to interact with nvgpu IO accessors. This interface is incredibly simple but not the easiest to use. More simple wrappers will be added later. JIRA NVGPU-1040 Change-Id: I325f09a1739a58ea6bcb1c74834037d6977ce0e8 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741952 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HALs to implement pdb cache WARDeepak Nibade2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | We have a h/w bug on some chips and we need to support below additional HALs to implement a s/w WAR gops.fifo.init_pdb_cache_war() gops.fifo.deinit_pdb_cache_war() gops.fb.apply_pdb_cache_war() Add new API nvgpu_init_mm_pdb_cache_war() to initialize WAR sequence and call this from MM initialization and before setting up rest of the memory management units Deinitialize WAR while cleaning up MM support Add pdb_cache_war_mem member to gk20a to hold all the memory needed for the WAR Bug 200449545 Change-Id: Id2ac0d940c7881c7b0cf396413273c0f329a1a1f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1834901 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: read GPC mask from h/wDeepak Nibade2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate GPC mask in s/w and return to user space But this could give incorrect result as any GPC could be floorswept in h/w Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status from fuse Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w Set these HALs only for dGPUs right now. Fuse register to read GPC mask is not yet supported in simulation and hence simulation boot fails These HALs will be set for iGPU once simulation issue is resolved Use gops.gr.get_gpc_mask() if it is defined in gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask to user space Jira NVGPUT-132 Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822811 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add exports for posix-bitopPhilip Elcan2018-09-24
| | | | | | | | | | | | | | | | | This adds the exported symbols required by the posix-bitops unit test for the libnvgpu-drv shared library. JIRA NVGPU-1042 Change-Id: Ia70921f9394fce013a1871b31d5682c0301098cf Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819971 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove freeing of unused pointer for mclkDebarshi Dutta2018-09-24
| | | | | | | | | | | | | | | | | | | | | mclk is not enabled yet for IGPUs and as such we donot allocate memory and incorrectly free them in gp10b_clk_arb_cleanup. This is corrected by removing the freeing of the mclk pointers in gp10b_clk_arb_cleanup. As an addon also change gk20a/gk20a.h to <nvgpu/gk20a.h> in clk_arb_gp10b.c Bug 2061372 Change-Id: I3bba20443b9ef7beb88251779edd67a32f6c9d20 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1836553 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Prateek Sethi <prsethi@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU init sequence changeMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix entry_type value for GM20B TopTejal Kudav2018-09-24
| | | | | | | | | | | | | | | | | In hw_top.ref, the entry_type value is 3 and not 2. JIRA NVGPU-1053 Change-Id: I7de5788ae5d08a88f1734bff56acae6f2f03581a Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813267 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR code refactorMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: PMU cleanup for ACRMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | - Removed ACR support code from PMU module - Deleted ACR related ops from pmu ops - Deleted assigning of ACR related ops using pmu ops during HAL init -Removed code related to ACR bootstrap & dependent code for all chips. JIRA NVGPU-1147 Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817990 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase sync-unmap timeout to 100msRichard Zhao2018-09-21
| | | | | | | | | | | | | | | | | | | - sync-unmap timeout was observed intermittently. so doubled the timeout value. - also check ref count after last round of sleep. The polling could succeed during the last sleep. - fix error print on timeout. Bug 200434475 Change-Id: If821dfaca9b86873711f436645523dc49a5eba34 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828562 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not disable GRFIFO access when resetting GRTerje Bergstrom2018-09-21
| | | | | | | | | | | | | | | | | | gk20a_init_gr_prepare() is called only when initializing GR from reset. In those cases there is no need to disable GRFIFO access. Remove the corresponding code. It also gets rid of one extra dependency to MC registers. JIRA NVGPU-954 Change-Id: I935e65f236e0f29ab224787d20e017d8c67e69e2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822309 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"Konsta Holtta2018-09-21
| | | | | | | | | | | | | This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb. Bug 2400508 Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837223
* Revert "gpu: nvgpu: vgpu: added tsg_release for gp10b hal"Konsta Holtta2018-09-21
| | | | | | | | | | | This reverts commit a683f99252378e0923bcaf201aa17074399101c8. Bug 2400508 Change-Id: I7d0ebdb62cdb7838e3b124ec34beb05a700a35ed Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837224 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
* gpu: nvgpu: vgpu: added tsg_release for gp10b halaalex2018-09-21
| | | | | | | | | | | tsg_release hal_fn was missing in vgpu_gp10b causing proper cleanup not to happen at the rm-server. Change-Id: Ic0e57d1d37e0f92eea23087299c8c22c094199b0 Signed-off-by: aalex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830192 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove circular dependency between hal.c and gk20a/ddutta2018-09-21
| | | | | | | | | | | | | | | | | gk20a/hal.c depends on HAL init functions in all chips. But all chips also depend on gk20a. That creates a circular dependency. In order to solve the above, move gpu_init_hal and gk20a_detect_chip to common/init/hal_init.c. These methods are declared in include/nvgpu/hal_init.h. Also, the above methods are renamed to nvgpu_init_hal and nvgpu_detect_chip respectively. Jira NVGPU-613 Change-Id: Ib0df90287d4491571e4751475739b75fabd1041b Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctlaalex2018-09-21
| | | | | | | | | | | | | | | added hal layer for SM exception mask handling for taking care of vitualization case. Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544 Signed-off-by: aalex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816284 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add POSIX sanity unit testAlex Waterman2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a unit test to do sanity checks for the environment. These checks currently include: - Size of types (f.e. u32 is really 4 bytes) - Signedness of types (u32 is really unsigned) - Endianness check - Pointers fit in u64s Note: the endianness check does not fail for either detected endianness. It just prints the determined endianness. The exception to this is if the check itself is broken and does not successfully determine what endianness the underlying machine is. In that case the test fails. Unless the underlying architure is a so called middle endian machine something is horribly wrong. We will determine what to actually do about this endianness check once we determine what we need to do with BIOS fields, etc. We proabbly don't really care what the machine endianness is but we do need to make sure that we access data that may not match machine endianness correctly. JIRA NVGPU-1039 Change-Id: I5be68cf4dcea87e9e746262fcc0372380ef57df4 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816897 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix some dma.[ch] MISRA violationsAlex Waterman2018-09-20
| | | | | | | | | | | | | This doesn't correspond to a specific rule; it just cleans up the violations introduced by http://git-master/r/1799807. JIRA NVGPU-990 Change-Id: Ia20af754da9ad60f81d58ba00bf781a8c441827b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804887 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused register accessors for voltaDeepak Nibade2018-09-20
| | | | | | | | | | | | | | | | Remove some unused register/field accessors for gv100/gv11b since they are not being accessed anymore on these chips Bug 2173122 Change-Id: Ia4692a72e23024d2ee71a80b08040885af21a9ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830312 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: posix_bitops: fix fls() testsPhilip Elcan2018-09-20
| | | | | | | | | | | | | | | | The fls() test assumed fls(1)=0, but really fls(1)=1, etc. Bug found as result of JIRA NVGPU-1042. Change-Id: I8d0ffe53277f4923a970b46788165ef03b385703 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828362 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: fix implementation of fls()Philip Elcan2018-09-20
| | | | | | | | | | | | | | | | | The POSIX implementation of fls() wasn't compliant with the Linux which returns fls(0)=0 fls(1)=1, etc. Bug found as result of JIRA NVGPU-1042. Change-Id: Id0279e36332ffe236ed792c013c32f2da841f557 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828361 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: print BIOS version during dGPU bootDeepak Nibade2018-09-20
| | | | | | | | | | | | | | Printing BIOS version during dGPU boot could be helpful for debugging Change-Id: I910143f6e0008aa9fd6999d464af2d1930cfe8d5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1832949 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move lts intr servicing to separate functionsDeepak Nibade2018-09-20
| | | | | | | | | | | | | | | | | | | | | We right now service LTS interrupts as part of LTC interrupt service routine Separate out the LTS interrupt handling in separate functions e.g. gp10b_ltc_lts_isr() for gp10b and gv11b_ltc_lts_isr() for gv11b gv11b_ltc_lts_isr() now calls gp10b_ltc_lts_isr() to service legacy LTS interrupts instead of calling gp10b_ltc_isr() directly Bug 2216662 Jira NVGPU-767 Change-Id: Ia8499feca83f67ac455cee311edf32390acb83b8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821430 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: restructure vgpu clk implementationAparna Das2018-09-20
| | | | | | | | | | | | | | | | Move OS agnostic parts of vgpu clk code out of os/linux specific path. This includes implementation sending rpc commands to RM Server. Move Linux specific vgpu clk code to platform vgpu files keeping it consistent with native implementation. Bug 2363882 Jira EVLR-3254 Change-Id: I0aae014ef16415bb356c81e9bfd76bc65206d9fd Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1820674 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race condition in pmu_rpc_handlerThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | | There was a race condition between pmu_rpc_handler and nvgpu_pmu_rpc_execute. The later could free the buffer before pmu_rpc_handler could access related data. Added explicit field in rpc_payload, so that nvgpu_pmu_rpc_execute can wait until pmu_rpc_handler completes. Bug 2331655 Change-Id: Ic2653524159eff10504b9c2625b5241610b5f5f0 Reviewed-on: https://git-master.nvidia.com/r/1811299 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817582 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clear cmd bufferThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | Clear command buffer before setting up the command. Fixes PMU crash on rapid perf events. Bug 2331655 Change-Id: Ic0661cc8fef4b744f15495ab16ddff85b4d7dec6 Reviewed-on: https://git-master.nvidia.com/r/1811245 Reviewed-by: David Jarrett <djarrett@nvidia.com> Tested-by: David Jarrett <djarrett@nvidia.com> Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow a calibration parameter to be zeroThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | It is allowed for some calibration parameters to be zero, when the others are non-zero. Pass all calibration parameters to PMU. Bug 2331655 Change-Id: I953a40e37211169e1aefd80aef2545a1b6a0afa1 Reviewed-on: https://git-master.nvidia.com/r/1810994 Reviewed-by: David Jarrett <djarrett@nvidia.com> Tested-by: David Jarrett <djarrett@nvidia.com> Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817580 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set calibration type for VIN devicesThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | | | | Calibration type was not initialized for VIN devices 2.0 This was leading to using the older calibration method. Fix calibration type when parsing VBIOS. Bug 2331655 Change-Id: I935f2a1812b8934dd8d3cd7e7d9c335a979a154e Reviewed-on: https://git-master.nvidia.com/r/1810379 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: David Jarrett <djarrett@nvidia.com> Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817579 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update number of LUT entriesVaikundanathan S2018-09-20
| | | | | | | | | | | | | | CTRL_CLK_LUT_NUM_ENTRIES to 128 And fix build issues that appeared with 128 entries. Bug 2331655 Change-Id: If116bff14be9a1923e075f783fdb9a2e992208b8 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810493 Reviewed-on: https://git-master.nvidia.com/r/1813861 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add GV10x perf eventVaikundanathan S2018-09-20
| | | | | | | | | | | | | | | In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: restrict devfreq during active clk_arb set requestsDebarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | Restrict access to devfreq when there are active set requests in the clk_arbiter. We make the following changes in the patch. 1) Add a global counter in the struct gk20a named clk_arb_global_nr which is used to track the number of active set requests in the system. 2) Anytime a set request is successfully made by the userspace, clk_arb_global_nr is incremented by 1 and during the completion of request(releasing the corresponding file handle), clk_arb_global_nr is decremented by 1. 3) gk20a_scale_target(invoked by devfreq to set the new frequency based on load) atomically checks clk_arb_global_nr. If the value = 0, the code simply continue or else if its > 0, it quits thus making devfreq requests mutually exclusive with the clk_arbiter. Bug 2061372 Change-Id: I5d19de03e45520f4ff8fccb97b1f1589d04c8ab8 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add igpu support for clk_arbiter.Debarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs clk_arbiter specific code for gp10b as well as gv11b and does the necessary plumbing in the clk_arbiter code. The changes made are as follows. 1) Constructed clk_arb_gp10b.* files which add support for clk_arb related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb. This doesn't have support for debugfs nor the VFUpdateEvent yet and consequently no support for arb->notifications. 2) Added gpcclk specific variables corresponding to every gpc2clk in a given clk_arb related struct. 3) Linux specific support_clk_freq_controller is assigned true in platform_gp10b.c and platform_gv11b.c files. 4) Incremented the clk_arb_worker.put atomic variable during worker_deinit so as to allow the worker thread to be stopped. 5) Added the flag clk_arb_events_supported as part of struct nvgpu_clk_arb. This flag is used to selectively account for the extra refcounting present in OS specific code i.e. nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is reduced during nvgpu_clk_arb_release_completion_dev. Bug 2061372 Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: expose linux clock controls via HALddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | Expose the linux specific clock implementations via the HAL interface to allow nvgpu to use the controls globally. This patch does the following. 1) Implement a new ops interface and a corresponding linux specific implementation for allowing nvgpu to iterate through a list of available clock frequencies via nvgpu_linux_clk_get_f_points(). 2) Implement nvgpu_linux_clk_get_range(). Bug 2061372 Change-Id: I7ce9a999dbdcd9fafcc84301af148545f6ca97a9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774280 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: minor fixes in channel_sync.cddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | This patch comes as a follow up to commit 2517d59be282426eec7a97745b76d745ff36c388 containing minor fixes i.e. changing type of 'pos' to u32 instead of int and renaming syncpt_get_id to channel_sync_syncpt_get_id Jira NVGPU-1086 Change-Id: I8bd9271c20d88ff5f68ccfc48a0b533844bbcaaa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829832 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE APIAnup Mahindre2018-09-19
| | | | | | | | | | | | Remove the API as it has no use cases. Bug 200445906 Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gk20a: gr: MISRA 10.1 & 14.4 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in nvgpu/gk20a/gr_gk20a.c Changed instances of BIT() to BIT32() in nvgpu/gk20a/gr_pri_gk20a.h JIRA NVGPU-646 JIRA NVGPU-1019 Change-Id: I1784f8509cc87d65ac1c8c95796a4c8876626b48 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811925 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807132 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmgr: MISRA Rule 21.2 header guard fixessmadhavan2018-09-19
| | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in pmgr by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I1beda400163bfc6278763161520f918fb4a3d096 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815663 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use single lock for gpu power on-offNitin Kumbhar2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | Using two separate locks (poweron_lock and poweroff_lock) allows concurrent gpu power-on and power-off. This shall not happen as driver won't be able to maintain correct gpu state. Use a single power_lock to manage gpu power state. This lock will be used to manage gpu power state from multiple triggers like gpu idle, gpu gc-off, etc. JIRA NVGPU-1100 Change-Id: Ia9b4aeda024a5844ae9f182d453cd6341876680a Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827812 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: deref twice in qsort callbackKonsta Holtta2018-09-18
| | | | | | | | | | | | | | | | | | The compare function for qsort takes pointers to compared elements, and our elements are already pointers so the void pointer has to be cast to a pointer pointer. Dereferencing only once would compare some data that's in the array of module pointers (or past it), not the actual data where the module pointers point to. Change-Id: I65678863eddd6fc86d4ffceb621f8123944b058d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828164 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: ctrl: MISRA Rule 21.2 header guard fixessmadhavan2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in ctrl by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ia7e5bf76dd2a8689e365bdeb27eac4b6e9ca4cfd Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815657 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gv11b: MISRA Rule 21.2 header guard fixessmadhavan2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gv11b by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ibf6b54b2a0d3f4fbfacb554b78b88911341b960f Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815567 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel_sync_gk20a.* to common directoryDebarshi Dutta2018-09-18
| | | | | | | | | | | | | | | | | | | | 1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they donot program any hardware registers. Also as an add-on rename channel_sync_gk20a.* to channel_sync.* and update the headers in required files. 2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also, corresponding syncpt and semaphore versions of the struct alongwith related methods are renamed by removing "gk20a" from their names and adding "nvgpu". 3) Add misra-c cleanups Jira NVGPU-1086 Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812594 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:43:59 -0500