| Commit message (Collapse) | Author | Age |
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Add refcounting for TSGs and manage the refcounts as below :
- initialize ref when TSG is opened
- get ref when channel is bound to TSG
- drop the ref when channel is unbound (i.e. during channel close)
- drop the ref when TSG is closed
- when refcount drops to zero, we free the TSG
This refcounting makes it possible to close channels or TSG
in any order
Bug 1470692
Change-Id: Ia4b39164a4582c8169da62a91b9131094c67f5f8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/495667
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gr_gk20a.c : railgating path the crash was seen
with multiple frees happening
acr_gm20b.c : failure path, kernel panic was seen,
with multiple frees
Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/494161
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Adding support for falc_trace for ACR
Change-Id: Iad638b0de72ff122f43f2250dce6a37adab4cecb
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/494162
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.
Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698
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remove config GK20A_PHYS_PAGE_TABLES since all code
dependent on this config is now moved to runtime
selection
Change-Id: I27d2722a9ad91cf4e0537a30943675c9132d6924
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/494499
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I913b6879e0d1ac89b740c1d088d639cc9b13b9b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/494200
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
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Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/494164
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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When clearing sparse buffers, pte->ref must be cleared once the PTE
is freed.
Bug 1549451
Change-Id: Ie7d3e438ef2c43cbcf893709ae50a67823bf0c9c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/494670
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Fix order of calculation for max comptag line calculation.
Bug 1549451
Change-Id: I13bf657f0f0b8aafa4d64dacacb74d7224fed379
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/494657
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
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Fix L2 error processing to look into interrupts in each L2 and slice.
Enable L2 error interrupts.
Bug 1549451
Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/494656
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Enable gpu rail gating with INT_MAX delay. This will allow
teams to experiment with different rail-gate entry delay.
Change-Id: I8c696140aba2374c797365282999b6589432047c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/491615
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Display the Falcon Trace prints in the right format.
Embedd the parameters in the string instead of printing it separately.
Bug NA
Change-Id: Ia61fc43384cf6e44a867c7aa9cbb828127146099
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: http://git-master/r/488757
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1500195
Change-Id: Ie2253f2650844cbc707a3083cc2f6b5150c4a17b
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/488508
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1500195
Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/488507
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Moved detection of idempotent GPCPLL operations from set_pll_freq()
function to its callers, e.g., explicitly check when enable operation
is called on already enabled PLL, instead of passing same frequency
to set_pll_freq() in such case. Similarly explicitly check when disable
operation is called on already disabled PLL.
Also moved check for GPU powered on from set_pll_freq() to callers,
and skip call to set interface if not.
Added last GPCPLL configuration structure updated after successful
completion of set_pll_freq() function.
Bug 1450787
Change-Id: I8c14b8cab2a8548e98c9b2d223c465c68fb87b61
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488027
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Change-Id: Ia9ab5ef8fbe3244b44c911d8808123e0aaf860cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/488611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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The cde shader will only read data from the global compbit backing
store. Map it as read-only to enforce this.
Change-Id: If5be44b8daedd5e7fdee650a6e76befa7bdecfd6
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/486679
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based on the config setting and fuse secure no non secure boot is done
Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/487684
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Passed pll structure to GM20b clk_slide_gpc_pll() function instead of
just feedback divider N value.
Change-Id: Ic99d23895ae27e48ccd5a12de99a58bab320df16
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488025
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Passed pll structure to GM20b clk_lock_gpc_pll_under_bypass() function
instead of individual M/N/PL dividers values.
Change-Id: I4881f6fad0e4be63a0eefb7277894d6900e9bb13
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488024
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Passed pll structure to GM20b clk_program_gpc_pll() function instead
of enclosing clock structure.
Change-Id: I81a3a3c03365f4b6997c17894c5210ebdadcbca6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488023
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Added direct read and write debugfs access to GM20b GPCPLL registers.
Change-Id: I203621906ee094991eecd5c18fd5b6c70b20a4c1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/487314
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Change-Id: I955fe300702f268e5403aab6f47859dd113f92a3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/487301
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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In gk20a_do_idle(), to get pointer to platform_device of gk20a,
we use bus_find_device_by_name() and pass "gk20a.0" to it
But this hard coding fails on gm20b since GPU device name
there is "gpu"
Hence to fix this add a static pointer handle "gk20a_handle"
to struct gk20a in gk20a.c
Now we can access this global pointer inside do_idle()
to get gk20a pointer and from that we can get pointer to
platform_device
Change-Id: I1a65588e34ad36efed0fa587bb365f0ee81e253d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/486887
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Currently cde reinitialises the context each time before submitting
work to the channel. This was done to ensure that we are able to
get clean context for the shader during development phase. However,
as the shader has been tested to work w/o reinitialising the context,
we can remove the reinitialisation to gain better performance.
Change-Id: If0b0e03133058528da943faaeb72ca500d3ddb14
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/486673
Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com>
Tested-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
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Disabled GM20b idle clock slowdown during rate measurements.
Change-Id: I20127c1f2816b7a8fe2f208eb21d2decc986d727
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/486324
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Added clock idle slowdown register. Fixed duplicated/overlapping
therm_peakpower_config8_r and therm_peakpower_config1_r definitions.
Change-Id: I37dad714ce5a6730a2f0b7c1b31b509bb1823975
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/486323
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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LTC interrputs were set to random values at boot. For now, disable
all interrupts.
Change-Id: Ibb032cac91d3ea9a951fd8c2eb62a783af5bd1a1
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/482639
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
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Do not force GM20b GPCPLL post divider to 1:2 settings before switching
to bypass clock if PLL output frequency is increased as a result. Move
this step under bypass. However, this step is still needed in case when
PLL can be configured without switch to bypass.
Bug 1450787
Change-Id: Iab81b0e5a71f44f738a64e15b05df41fdbd61ebe
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456505
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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The code took reference to gk20a by using gk20a_busy_noresume(). This
function takes pm runtime reference only to the GPU, however, the code
dropped the reference by calling gk20a_idle() which also drops the
reference to the platform dependencies (host1x).
This patch modifies gm20b_mm_mmu_vpr_info_fetch_wait() to drop only
the GPU reference.
Change-Id: Ied59381fa302452356768ed59e8ad9af18284e3d
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/482721
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The nvgpu driver now supports using the Tegra graphics virtualization
interfaces to support gk20a in a virtualized environment.
Bug 1509608
Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440122
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Current implementation is based on config GK20A_PHYS_PAGE_TABLES
to have APIs to create/free/map/unmap phys pages
Remove this config based implementaion and move the APIs so that
they are called at runtime based on tegra_platform_is_linsim()
In generic APIs, we first check if platform is linsim and if it
is then we forward the call to phys page specific APIs
Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/488843
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tegra graphics virtualization (host1x syncpoint and gpu) is now
exposed to client drivers (nvhost and nvgpu). These interfaces
rely on a communication framework to communicate with the server
driver that actually implements the back-end routines.
Bug 1509608
Change-Id: I5277f4b024953772a2215d33afa178162f5f9232
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440120
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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PB timeout has been removed in gm20b, so write it only in gk20a.
Change-Id: I2aab92fe7d1d5de151dad768f8b3f6901ec0bbb0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/486358
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
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Simulation does not model rails, so do not try to control them.
Change-Id: I52ec12e7865e18764274dd9ce7a2fbd196b6b9d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/482181
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
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Add powergate/powerungate callbacks for gm20b configuration.
Change-Id: Ieb681b74de7ea19d172922ef68260be81b675a56
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/457352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when
powering down GPU.
Bug 1450787
Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456504
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
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Modify the 3d.emc policy to use a formula based on bandwidth and
utilization instead of the current sku-dependent policy.
Bug 1364894
Change-Id: Id97f765a48f0aa9f5ebeb0c82bccb22db474a1ae
Signed-off-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-on: http://git-master/r/453586
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for multiple GPCs/TPCs to the GPC/TPC
exception handling code.
Change-Id: Ifb4b53a016e90cb54c4d985a9e17760f87c6046f
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/411660
Reviewed-by: Automatic_Commit_Validation_User
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Bug 1534793
Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/441377
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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PBDMA timeout can cause stale data in FIFO. Default value equals 1ms.
Increase it to max.
Bug 1537636
Change-Id: I1c6c6b10abaece3a64b77b9b3ef77ff726ff67cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457047
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Chang <allchang@nvidia.com>
Tested-by: Allen Chang <allchang@nvidia.com>
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Gk20a unmaps the addresses binding to dummy page to clear sparse.
On Gm20b, we need to free the allocated page table entry for sparse
memory.
Bug 1538384
Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/448645
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add below ioctl to force channel reset/recovery.
NVHOST_IOCTL_CHANNEL_FORCE_RESET
This recovery/reset is initiated by triggering
mmu fault on channel so as to force the channel
out (as oppose to waiting until channel is
preempted)
Bug 200027958
Change-Id: Idd3c10ef5fa691d746e34a8b890bd79aca815a20
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/456084
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1450798
Change-Id: I371537d086ce1088c6d007676c1fe1e2770dd4e3
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403877
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Retrieve which TPC is floorswept.
Bug 1450798
Change-Id: I3ea60703695448c68cd3435f443b280d5b2f0995
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403876
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Updated aelpg parameter APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT
default value to 200
Bug 1536384
Change-Id: I090e50d0025f16c006429455d161bee26fc64173
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/455440
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Disable cyclestats register whitelist check if allow_all is
enabled through sysfs.
bug 1523403
bug 1490388
Change-Id: Iaa1cf9a8fed18f1a379cac28128793fb33567f35
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/454932
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: Idf1261fe6561477f5dceea54de63326ef8a4a1b3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/455041
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Through this sysfs entry, the register space becomes accessible.
This is be accessible root-only.
Bug 1523403
Change-Id: Ia46f130a0cfd8324c5b675d19e7cbfba9dcb17ca
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/454198
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Currently cde swizzling application forces upper limit to surface
size. The limitation is artificial (i.e. nothing prevents shader
handling larger surfaces). Therefore, make the error condition a
warning.
Change-Id: I8f0cda7f2e9e9ecc90589e5a4b4091abcb513482
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/454591
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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