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* gpu: nvgpu: gv11b: whitelist regs generated for HW CL 39455624Seema Khowala2017-11-22
| | | | | | | | | | | | Bug 2010624 Change-Id: I8da53867b8551f502632df4ad2ef2386db591567 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599837 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: header generated for HW CL 39455624Seema Khowala2017-11-22
| | | | | | | | | | | | Bug 2010624 Change-Id: Ibf23c8e8f13291f61580478924cd13c1c75c8cd5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599836 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't run cde shader for 0 ctaglinesKonsta Holtta2017-11-22
| | | | | | | | | | | | | | | If the associated buffer is not compressed, it would be invalid to call the cde swizzler shader with zero lines. The fences in PREPARE_COMPRESSIBLE_READ still need to be managed, so just do a dummy submit with zero entries when lines is zero for the buffer. Bug 1856088 Change-Id: Ia68c2ffff21e5e8077d5c550b0ca44090f88bf80 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add check_priv_security fuse opsSeema Khowala2017-11-22
| | | | | | | | | | | | | | | | | | | | | | | -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: CONFIG_TEGRA_ACR is supported by defaultSeema Khowala2017-11-22
| | | | | | | | | | | | TEGRA_ACR config is supposed to be enabled maxwell onwards. Since gk20a support is no longer supported, delete code that is not under TEGRA_ACR config Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595437 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon interface updateMahantesh Kumbar2017-11-20
| | | | | | | | | | | | | | | | | | | | | | | | -Added nvgpu_flcn_mem_scrub_wait() to falcon interface layer to poll imem/dmem scrubbing status complete check for 1msec with status check interval of 10usec. -Called nvgpu_flcn_mem_scrub_wait() in falcon reset interface to check scrubbing status upon falcon/engine reset. -Replaced mem scrubbing wait check code in pmu_enable_hw() by calling nvgpu_flcn_mem_scrub_wait() Bug 200346134 Change-Id: Iac68e24dea466f6dd5facc371947269db64d238d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Dump falcon status upon boot failureMahantesh Kumbar2017-11-20
| | | | | | | | | | | | | | | - Dump PMU/SEC2 falcon status upon ACR boot failure Bug 200346134 Change-Id: I90b6dac5d3109adf85e1fcb50f114d74caa43164 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582601 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Kill pg init thread if pmu boot failsMahantesh Kumbar2017-11-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Created nvgpu_kill_task_pg_init() method to set pmu state to PMU_STATE_EXIT & make thread stop, and poll to confirm thread stopped. - Check for PMU/SEC2 ACR secure boot completion status & initiate pg init thread kill if ACR boot exits with error, which fails to validate & boot LS-PMU. - Set pmu state to PMU_STATE_OFF after thread kill during ACR boot failure. Issue: pg init task blocks if PMU boot fails & cause kernel to show message "task nvgpu_pg_init_g:2120 blocked for more than 120 seconds" Bug 200346134 Change-Id: I5270426080dcd628ccca4df798005294c19767a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582593 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove separation of t18x codeTerje Bergstrom2017-11-17
| | | | | | | | | | | Remove separation of t18x specific code and fields and the associated ifdefs. We can build T18x code in always. Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add translation for NVGPU MM flagsAlex Waterman2017-11-17
| | | | | | | | | | | | | | | | | | | | | | | Add a translation layer to convert from the NVGPU_AS_* flags to to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags. This allows the common MM code to not depend on the UAPI header defined for Linux. In addition to this change a couple of other small changes were made: 1. Deprecate, print a warning, and ignore usage of the NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag. 2. Move the t19x IO coherence flag from the t19x UAPI header to the regular UAPI header. JIRA NVGPU-293 Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move vgpu code to linuxDeepak Nibade2017-11-17
| | | | | | | | | | | | | | | | | | | | Most of VGPU code is linux specific but lies in common code So until VGPU code is properly abstracted and made os-independent, move all of VGPU code to linux specific directory Handle corresponding Makefile changes Update all #includes to reflect new paths Add GPL license to newly added linux files Jira NVGPU-387 Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599472 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix some barrier usageAlex Waterman2017-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | Commit 81868a187fa3b217368206f17b19309846e8e7fb updated barrier usage to use the nvgpu wrappers and in doing so downgraded many plain barriers {mb(), wmb(), rmb()} to the SMP versions of these barriers. The SMP version of the barriers in question are only issued when running on an SMP machine. In most of the cases mentioned above this is fine since the barriers are present to faciliate proper ordering across CPUs. A single CPU is always coherent with itself, so on a non-SMP case we don't need those barriers. However, there are a few places where the barriers in use (GMMU page table programming, IO accessors, userd) where the barrier usage is for communicating and establishing ordering for the GPU. We need these barriers for both SMP machines and non-SMP machines. Therefor we must use the plain barrier versions. Change-Id: I376129840b7dc64af8f3f23f88057e4e81360f89 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599744 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not include UAPI in gr_gk20a.hTerje Bergstrom2017-11-16
| | | | | | | | | | | | | | | | Remove #include of <uapi/linux/nvgpu.h> from gr_gk20a.h. vgpu_mm_gp10b.c uses UAPI definitions, so add an explicit #include there. JIRA NVGPU-363 Change-Id: Ieabd7240d62495d2719d7fdbc25cc238de13c75e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598981 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Forward declare nvgpu_ctxsw_trace_filterTerje Bergstrom2017-11-16
| | | | | | | | | | | | | | gk20a.h refers to nvgpu_ctxsw_trace_filter, which is defined in another header. Add a forward declare to remove the dependency. JIRA NVGPU-363 Change-Id: I537b6005eb65c4d44799d0f72deced5ec54bc99b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598980 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change reg_op_is_* into normal funcsTerje Bergstrom2017-11-16
| | | | | | | | | | | | | | | | reg_op_is_* static inline force a dependency to UAPI in regops_gk20a.h. Change the implementation to be functions in .c file. JIRA NVGPU-388 Change-Id: If5cae1ad011a26ee5ff23e1e39aac3d88fd5bb98 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598979 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Mark nvgpu_pde_phys_addr staticAlex Waterman2017-11-16
| | | | | | | | | | | | | | | | | | nvgpu_pde_phys_addr() is only used in gmmu.c and as such can be marked static. JIRA NVGPU-402 Change-Id: I7adba6f54ebd4e06d176f23b9a959c04a8770338 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599040 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove dma_buf forward decAlex Waterman2017-11-16
| | | | | | | | | | | | | | | | | | Remove a forward declaration of dma_buf in <nvgpu/vm.h>. This forward declaration is no longer necessary since all usage of dma_bufs has been removed from common code! JIRA NVGPU-224 JIRA NVGPU-30 Change-Id: I0948d8b99efc6429f7a6d122ef3655d670205d75 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598934 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Always allocate zeroed DMA memAlex Waterman2017-11-16
| | | | | | | | | | | | | | | | | | Always allocate explicitly zeroed DMA memory and remove the unnecessary memset() from the alloc path for memory with a kernel mapping. JIRA NVGPU-418 Change-Id: I5a3df6e6969e2586df41b72325d1bff1e40206e6 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598933 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: move to use is_valid_gfx/compute_class opsRichard Zhao2017-11-16
| | | | | | | | | | | | | | It'll make the code be able to apply to gv11b too. Jira EVLR-1671 Change-Id: I9a960fd1aaa9adc6bb39aa2c730049e75006fea7 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1597379 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: abort the channel right after force reset itRichard Zhao2017-11-16
| | | | | | | | | | | | | | | | For gp10b and previous chips, RM server will issue fake mmu fault to reset the channel. And the mmu fault event will be sent to vgpu client, which will cause the client to abort the channel or tsg. But on gv11b, RM server doesn't issue fake mmu fault any more. So I need to abort it right after the force reset is finished. Jira EVLR-1671 Change-Id: I11399fda84d31086ba1d4ffde5948e409cde2a28 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1597378 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove nvgpu-t19x includesDeepak Nibade2017-11-16
| | | | | | | | | | | | | | | | We no longer use code in nvgpu-t19x or t19x repo, so remove obsolete includes from Makefile Bug 200363166 Change-Id: I29e78931e90e0afffecf756bf7479ed8784dbc25 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599470 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Merge remote-tracking branch 'remotes/origin/dev/linux-nvgpu-t19x' into ↵Deepak Nibade2017-11-16
|\ | | | | | | | | | | | | | | | | linux-nvgpu Bug 200363166 Change-Id: Ic662d7b44b673db28dc0aeba338ae67cf2a43d64 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
| * gpu: nvgpu: gv11b: modify dma alloc flagsseshendra Gadagottu2017-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call nvgpu_dma_alloc_flags_sys without NVGPU_DMA_NO_KERNEL_MAPPING flags, since it makes CMA memory handling simple in t194 and fixes error during subcontext header free: [ 340.378910] trying to free invalid coherent area: ffffffc0135ba000^M [ 340.378921] ------------[ cut here ]------------^M [ 340.378933] WARNING: CPU: 0 PID: 1618 at /code/volta/kernel/kernel-4.9/arch/arm64/mm/dma-mapping.c:1442 __arm_dma_free.isra.4+0x160/0x168^M [ 340.378950] Modules linked in: nvgpu^M [ 340.378958] ^M [ 340.378966] CPU: 0 PID: 1618 Comm: nvogtest Tainted: G W 4.9.52-tegra-g170e0c4 #20^M [ 340.378979] Hardware name: t194pre_si (DT)^M [ 340.378988] task: ffffffc018930d80 task.stack: ffffffc017e08000^M [ 340.378999] PC is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379009] LR is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379020] pc : [<ffffff800809cfd0>] lr : [<ffffff800809cfd0>] pstate: 60400045^M [ 340.379032] sp : ffffffc017e0bbe0^M [ 340.379039] x29: ffffffc017e0bbe0 x28: 00000000935ba000 ^M [ 340.379051] x27: 0000000000001000 x26: ffffffc0135b9580 ^M [ 340.379063] x25: ffffff8009ced1b0 x24: 0000000000000010 ^M [ 340.379075] x23: ffffffc070746010 x22: 0000000080000000 ^M [ 340.379088] x21: ffffffbf004d6e80 x20: ffffffc0135ba000 ^M [ 340.379100] x19: 0000000000001000 x18: ffffffffffffffff ^M [ 340.379112] x17: 0000007fa4d8fc60 x16: ffffff800823e370 ^M [ 340.379124] x15: ffffff8009cd8690 x14: ffffff8089fb34bf ^M [ 340.379135] x13: ffffff8009fb34cd x12: 0000000000000007 ^M [ 340.379147] x11: 0000000000000325 x10: 0000000005f5e0ff ^M [ 340.379159] x9 : 0000000000000326 x8 : 3331306366666666 ^M [ 340.379172] x7 : 6666203a61657261 x6 : ffffff8009fb3505 ^M [ 340.379184] x5 : 0000000000000012 x4 : 0000000000000000 ^M [ 340.379196] x3 : 0000000000010000 x2 : 0000000000040934 ^M [ 340.379207] x1 : 0000000000000000 x0 : 0000000000000036 ^M [ 340.379219] ^M [ 340.379224] ---[ end trace 9e7ab41f55eb32d2 ]---^M [ 340.379232] Call trace:^M [ 340.379241] [<ffffff800809cfd0>] __arm_dma_free.isra.4+0x160/0x168^M [ 340.379254] [<ffffff800809e3a0>] arm_dma_free+0x48/0x60^M [ 340.379827] [<ffffff8000f01250>] nvgpu_dma_free+0x260/0x410 [nvgpu]^M [ 340.380403] [<ffffff8000fb2fac>] gv11b_free_subctx_header+0x5c/0x80 [nvgpu]^M [ 340.380980] [<ffffff8000f3ed2c>] gk20a_free_channel_ctx+0x3c/0x150 [nvgpu]^M After changing dma alloc flags to none, this issue got fixed. Bug 1930032 Change-Id: I002236373c6a3ae5d7ec80a35f166429821662b7 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598193 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLsDeepak Nibade2017-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: detect stall intr during preemptionSeema Khowala2017-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check for interrupts or hangs while waiting for the preempt to complete. During pbdma/eng preempt done polling, any stalling interrupts relating to the runlist must be detected and handled in order for the preemption to complete. When PBDMA fault or CE fault occurs, the PBDMA will save out automatically. TSG related to the context in which the fault occurred will not be scheduled again until the fault is handled. In the case of some other issue requiring the engine to be reset, TSG will need to be manually preempted. In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to switch out. SW must handle these interrupts according to the relevant handling procedure before the PBDMA preempt can complete. Opt for eng reset instead of waiting for preemption to be finished when there is any stall interrupt pending during engine context preempt completion. Bug 200277163 Bug 1945121 Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522914 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Tested-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: mc_elpg_enable & soc credit init moved to bpmpSeema Khowala2017-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Program mc_elpg_enable and mss nvlink soc credits only when bpmp is not running or bpmp is running but underlying platorm is simulation. For simulation, bpmp does not execute hot reset sequence. As part of gpu unpowergate, bpmp will program mc_elpg_enable and also set mss nvlink soc credits after bringing mss nvlink out of reset -Remove updating mc_enable as writes to this register has no effect -Remove fifo_fb_iface_r read/write. This hack was added during initial bring up of emulation platforms Bug 2018223 Bug 200269361 Change-Id: Ie09c259e48295a93c6d15376308186152db973fa Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594495 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: define final netlistSeema Khowala2017-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use NETD firmware on gv11b. GV11B_NETLIST_IMAGE_FW_NAME set to GK20A_NETLIST_IMAGE_D Change-Id: I0301999851ffb14713beaf61b5b2cc97efac74eb Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1597290 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: define preemption modes in common codeDeepak Nibade2017-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | | Use common preemption modes in common code instead of using linux specific definitions Jira NVGPU-392 Change-Id: Iff65ab4278973f2e2d7db33f6fedb561b2164c42 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1596931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: ctx_patch_write fixesPeter Daifuku2017-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update commit_global_timeslice to remove unused patch parameter - Update calls to ctx_patch_write_begin/end to add update_patch_count param JIRA ESRM-74 Bug 2012077 Change-Id: Ie2e640dfa0ab7193a062a58f588575f220e5efd3 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594791 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Include UAPI explicitlyTerje Bergstrom2017-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add explicit #includes for <uapi/linux/nvgpu.h> for source code files that depend on it. JIRA NVGPU-388 Change-Id: I5d834e6f3b413cee9b1e4e055d710fc9f2c8f7c2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1596246 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: vgpu: Delete extra error printTerje Bergstrom2017-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vgpu printed GPU characteristics flags at probe time. Delete the print in order to be able to remove GPU characteristics field. JIRA NVGPU-388 Change-Id: Ib08325e7a67598a4f6734f7e839d1b96ba10bd55 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1596245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: Do not assign GPU classes in vgpu HALTerje Bergstrom2017-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GPU class ids were moved to get_litter_value API, but vgpu was not updated to remove assigning them in HAL initialization. Remove the duplicate assignments. JIRA NVGPU-388 Change-Id: If75944517d1ea813496b1f2a12a1faf03406d8d0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1596244 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Remove PTE kind code for GV100/GV11BSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: clear channel statusseshendra Gadagottu2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After unbinding channel, following fields in channel status needs to be cleared manually: ccsr_channel_enable_clr_true ccsr_channel_pbdma_faulted_reset ccsr_channel_eng_faulted_reset Unbinding channel expected to clear all other channel status fields. Bug 1972365 Change-Id: Ibfd84df2f41adc2eb437a026acde3f3d618d7758 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594671 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: update prod settingsseshendra Gadagottu2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated clock gating prod settings for HWCL # 39314184. This is corrected output after fixing issue in register generator tool. Bug 1994238 Change-Id: I646c4e1a134570016425367be636250205205005 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594605 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: Move sm_arch to nvgpu_gpu_paramsTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | Move sm_arch_* fields to nvgpu_gpu_params to make them available from common code without accessing Linux specific GPU characteristics. JIRA NVGPU-259 Change-Id: I8e7b542642b620f161d62954400777079065f49d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593692 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Return GPU classes in get_litter_valueTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: I92cbadf3bd07292a8715d30843972def879795f5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593691 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv1xx: Move fuse override DT handlingTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: vgpu: enable subctx for gv11bThomas Fleury2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add vgpu_gv11b_init_gpu_characteristics() and enable NVGPU_SUPPORT_TSG_SUBCONTEXTS Jira VFND-3797 Jira EVLR-1751 Change-Id: I288ac062e42ec399a302d693471b50b58c9a2653 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1543015 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channelThomas Fleury2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id and runqueu_sel to RM server. Use this command in gv11b's implementation of gops->fifo.tsg_bind_channel. Jira EVLR-1751 Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579840 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Switch to newer NVGPU_AS_MAP_BUFFER flagsSami Kiminki2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch two cases using the old NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_* flags to the newer definitions, that is, NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE. The legacy NVGPU_MAP_BUFFER_FLAGS_* definitions have been deleted. Bug 1902982 Change-Id: Ifbd2678b10005b4af2375600888469b01dd09f4e Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1592655 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * nvgpu: gv11b: implement railgate/unrailgateSeema Khowala2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement gv11b platform specific rail gating functions by calling relevant powergate and unpowergate functions and linux clock frmework functions: gv11b_tegra_is_railgated gv11b_tegra_railgate gv11b_tegra_unrailgate These calls will take care of hot reset sequence required for gpu powergate and gpu unpowergate. Bug 200269361 Bug 200273571 Change-Id: Ib1825e4324d51fc508b3b5dc9e5e2fdb252eeff4 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589509 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: move platform_gk20a.h to linuxDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix #includes in all the files to include platform_gk20a.h file with correct path NVGPU-316 Change-Id: Icb26d3c75076b8fdc8da992f751e1cfea22996be Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589939 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: use struct gk20a for create_gr_sysfsDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | API gr_gv11b_create_sysfs() and GR HAL create_gr_sysfs() right now receive linux specific struct device But since this function is called from/declared in common code, we need to remove linux dependency from it Hence update the API and GR HAL to receive struct gk20a pointer instead of device pointer Jira NVGPU-259 Change-Id: I65d717ad9f263f0397f8efa5761c64e55c7846eb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588465 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: Kernel iface for Dynamic TPC-PGDeepak Goyal2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds kernel interface for dynamic TPC-PG feature. User-space needs to send TPC-PG args to kernel via ioctl. Dynamic TPC-PG feature will allow every context to specify the number of TPC's it will use to run its workload. This way, graphics driver can power off non-required TPC's if a particular context has light to medium workload. JIRA GPUT19x-16 Change-Id: Id4846245a6414b719599d04784cbe2ca5282f4ad Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Split ctxsw_trace API into non-Linux componentAlex Waterman2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: vgpu: modify tsg enable sequenceAparna Das2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TSG enable sequence in native has been modified due to a hardware bug requiring enabling all channels with NEXT and CTX_RELOAD set in a TSG, and then enabling rest of channels.However it is not possible to check if NEXT and CTX_RELOAD is set in vgpu. Have a separate implementation for enabling tsg sequence in vgpu till the fix for hardware bug is implemented for virtualized configuration. Bug 200348087 Change-Id: I8e6c2ba8722531563de65e51e3d6af6acb7af213 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588739 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: Add GPU arch and impl to common structureTerje Bergstrom2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | Add GPU architecture and implementation to a new struct nvgpu_gpu_params which is defined in common header file gk20a/gk20.h. JIRA NVGPU-259 Change-Id: Idde2caded75fcb1e03e95be11f6aa2ec33a0962b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588033 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: use nvgpu_* APIs to allocate/free memoryDeepak Nibade2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use nvgpu specific nvgpu_kcalloc()/nvgpu_kfree() calls instead of linux specific kcalloc()/kfree() Jira NVGPU-259 Change-Id: I73034ea23561d1269230b9ac10360f8b171b8d41 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588221 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * gpu: nvgpu: gv11b: replay invalid pte faults onlySeema Khowala2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Try to fix invalid pte type repalayable faults only. All other replayable faults will be cancelled so that next mmu fault for same fault address will be triggered as non-replayable fault and ch/tsg teardown will take place. Bug 1958308 Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566576 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:13:42 -0500