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* gpu: nvgpu: add GK20A_PM_QOS Kconfig optionDebarshi Dutta2018-07-11
| | | | | | | | | | | | | | | | | | | | | GK20A_DEVFREQ scaling depends on Nvidia downstream kernel modifications to PM QoS framework. To break that dependency and to allow devfreq based scaling to work without those changes, introduce a Kconfig option to conditionally enable the PM Qos based constraints. Bug 200414723 Bug 200414600 Change-Id: If39a144dfb322176c2d0e6c17d57d0cd6d885c41 Signed-off-by: Timo Alho <talho@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762987 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Simplify FB hub intr enableTerje Bergstrom2018-07-11
| | | | | | | | | | | | Hard code flags for enabling and disabling FB hub interrupts. JIRA NVGPU-714 Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769853 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gcc 7.3 warning fixesStephen Warren2018-07-11
| | | | | | | | | | | | | | | | | | | gcc-7 warns about switch statements without a break statement unless a comment is present to indicate a deliberate fall through. Add such a comment to allow compilation with gcc-7.3. Bug 2224634 Change-Id: I27feec62100983e211ffd430f013d30ca56909b9 Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769564 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize hwpm perfmons (engine_sel)Vaibhav Kachore2018-07-10
| | | | | | | | | | | | | | - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable HWPM Mode-E context switchVaibhav Kachore2018-07-10
| | | | | | | | | | | | | | | | | | - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon code cleanupMahantesh Kumbar2018-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created common falcon function nvgpu_flcn_bl_bootstrap() to bootstrap falcon bootloader -Created HAL gk20a_falcon_bl_bootstrap() which does actual bootloader bootstrap by fetching parameters and loading code/parameters as needed. -Created HAL ops bl_bootstrap under nvgpu_falcon_ops. -Created struct nvgpu_falcon_bl_info to hold info required for bootloader to pass to common function -Removed falcons bootstrap code in multiple file & made changes to fill struct nvgpu_falcon_bl_info & call nvgpu_flcn_bl_bootstrap(). Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756104 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB MMU query to FB HALTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming FB phys access to FBTerje Bergstrom2018-07-09
| | | | | | | | | | | | | FB physical access register for simulation was programmed in GR implementation. Move it to FB where it belongs. JIRA NVGPU-714 Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: ring doorbell after enabling TSGAparna Das2018-07-09
| | | | | | | | | | | | | | | | | | | | | | | In some use cases client will disable and preempt TSG and then re-enable it using IOCTLs provided In case there is only one context getting re-enabled and there is no other job submission in parallel runlist fetcher will just sleep until doorbell is received next time This causes above mentioned test cases to stall after re-enabling TSG until some one submits a new job and triggers a doorbell Fix this by explicitly triggering doorbell in vgpu code after we enable all channels in TSG. Bug 2205192 Change-Id: I25d643e06152adc6aaf874baf610316f6cd8f13f Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772948 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Conditional enable for replayable faultTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | | | Enable replayable fault only for contexts where they are requested. This required moving the code to initialize subcontexts to happen later. Fix signedness issues in definition of flags. JIRA NVGPU-714 Change-Id: I472004e13b1ea46c1bd202f9b12d2ce221b756f9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not enable replayable fault for contextTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | | | Do not allow enabling replayable page faults in instace block. JIRA NVGPU-714 Change-Id: I9c48497e31798ab354a86d460a299e65774b388a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772863 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove Pascal replayable fault supportTerje Bergstrom2018-07-09
| | | | | | | | | | | | | We do not utilize or test replayable page faults in Pascal. Remove the code related to that. JIRA NVGPU-714 Change-Id: I2415bde347f8b018ebf99c3f9038d47c649d9464 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Call handle_replayable_fault via HALTerje Bergstrom2018-07-08
| | | | | | | | | | | | | | gr_gv11b.c had a direct dependency to fb_gv11b.c because it calls FB to process replayable faults while waiting for SM lockdown. Redirect that call via HAL to remove the dependency. JIRA NVGPU-714 Change-Id: Ie6df3658f06b1f867893bc98fe581c95813f0431 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772884 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gv11b specific BAR2 deinitTerje Bergstrom2018-07-07
| | | | | | | | | | | | | | | | | gp10b and gv11b variants of remove_bar2_vm are now identical, so delete the gv11b version and use only gp10b version. JIRA NVGPU-714 Change-Id: Ie98cb29803358ddcad8aae2cf865f3baeddebfb1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773007 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NULL check for enable/disable_shadow_rom HALsDeepak Nibade2018-07-06
| | | | | | | | | | | | | | | | | | gops.xve.enable_shadow_rom and gops.xve.disable_shadow_rom HALs could be NULL on some platforms Execute them only if they are defined Jira NVGPUT-120 Change-Id: I683d74a850372f442291a419951a2376805eb1e5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772559 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu: Fix pmu_state state updateDeepak Bhosale2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Commit c61e21c868246faf7a9ffc812590941fc362af17 fixed race codition in PMU state transition. - The race condition is such that PMU response(intr callback for messages) can run faster than kthread posting commands to PMU and thus PMU message callback may skip important pmu state change. - Commit c61e21c868246faf7a9ffc812590941fc362af17 introduced a fix where PMU state change was only updated from callback while other places can only update pmu_state variable - However, this commit introduced a regression as follows: - When PMU state is PMU_STATE_INIT_RECEIVED, we loop over every engine supported by GPU --> If state = PMU_STATE_INIT_RECEIVED, change the state to PMU_STATE_ELPG_BOOTING and init ELPG else If state != PMU_STATE_INIT_RECEIVED throw an error saying "PMU INIT not received" - Now, if GPU supports multiple engines, first engine will check that pmu_state is PMU_STATE_INIT_RECEIVED and change it to PMU_STATE_ELPG_BOOTING However, from second engine onwards, since state is already changed to PMU_STATE_ELPG_BOOTING, all engines except first engine start throwing error "PMU INIT not received" - This patch fixes the issue by changing pmu state from PMU_STATE_INIT_RECEIVED to PMU_STATE_ELPG_BOOTING only once. Bug 200372838 JIRA EVLR-2164 Change-Id: Ic8c954d14acb1d6ec3adcbc4bcf4d4745542d9f0 Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769814 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use devm variants to ioremapNitin Kumbhar2018-07-06
| | | | | | | | | | | | | | | | | | | | | | While removing nvgpu driver, devm mapped reg mappings are released on driver_unregister. For iGPU, these regs are explicitly unmapped with iounmap(). This results in "Trying to vfree() nonexistent vm area" warnings on driver removal. Address this by using devm* variants to map all IO regions of both iGPU and dGPU and let the driver unregister release these mappings. Also, lock out GPU regs in driver removal path. Bug 1987855 Change-Id: I0388daf90bea3eaf8752255059cfd3ceabf66e7d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730539 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ring doorbell after enabling TSGDeepak Nibade2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | In some use cases client will disable and preempt TSG and then re-enable it using IOCTLs provided In case there is only one context getting re-enabled and there is no other job submission in parallel runlist fetcher will just sleep until doorbell is received next time This causes above mentioned test cases to stall after re-enabling TSG until some one submits a new job and triggers a doorbell Fix this by explicitly triggering doorbell from gv11b_fifo_enable_tsg() after we enable all channels in TSG Bug 2205192 Change-Id: I08e70e3d0f7e4dc6471e63809e246430cc4200c1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772378 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set NVGPU_DEFAULT_DBG_MASK for dgpuNitin Kumbhar2018-07-06
| | | | | | | | | | | | | | | | | During probe of the driver, set g->log_mask to the default value of log_mask i.e. NVGPU_DEFAULT_DBG_MASK. Bug 1987855 Change-Id: Ia92fff2427e10f4fa9828b7b8d95f8f7b0276915 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770805 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add error check for init_runlistNitin Kumbhar2018-07-06
| | | | | | | | | | | | | | | | | | Allocations in init_runlist can fail. Check for such a failure during fifo setup is being done. Bug 1987855 Change-Id: I1771a15ebeac81ab2e3ebc9a75363445a0b6f20d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770801 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update dma dbg to report callerNitin Kumbhar2018-07-06
| | | | | | | | | | | | | __dma_dbg() logs func and line details of itself. Update it to report caller details. Bug 1987855 Change-Id: I51913b0c57c12e11880699caed557da9491304cf Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1771511 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine the fault buffer deinit seqsTerje Bergstrom2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | gv11b_mm_fault_info_mem_destroy() and gv11b_mm_mmu_hw_fault_buf_deinit() serve a similar purpose of disabling hub interrupts and deinitializing memory related to MMU fault handling. Out of the two the latter was called from BAR2 deinitialization, and the former from nvgpu_remove_mm_support(). Combine the functions and leave the call from nvgpu_remove_mm_support(). This way BAR2 deinitialization can be combined with gp10b version. JIRA NVGPU-714 Change-Id: I4050865eaba404b049c621ac2ce54c963e1aea44 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769627 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Rename Linux specific vidmem codeTerje Bergstrom2018-07-06
| | | | | | | | | | | | | | | | Rename os/linux/vidmem.c to os/linux/dmabuf_vidmem.c. The code is mainly dealing with interfacing with Linux dmabuf framework and its responsibilities got confused with common/mm/vidmem.c. Also move the header include/nvgpu/linux/vidmem.h to os/linux/dmabuf_vidmem.h. It does not expose any interface to outside Linux code. Change-Id: I2cb1057a8934d5cb5c5860023aa12f8f048a6684 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768261 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Clean up include/nvgpu/vidmem.hTerje Bergstrom2018-07-06
| | | | | | | | | | | | | | | | | vidmem.h had a forward declaration for a Linux specific struct work_struct. Removed that. vidmem.h also #included nvgpu_mem.h even though there was no use for it. As a follow-up css_gr_gk20a.h did refer to nvgpu_mem but did not #include it, so added that. Change-Id: Ifea88adae86ed95302465641821fbb107d7cc233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768260 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Clean up ioctl_dbg.hTerje Bergstrom2018-07-06
| | | | | | | | | | | | | | | ioctl_dbg.h contained several unnecessary #includes. Replace them with forward declarations. Also move all definitions only used by ioctl_dbg.h to ioctl_dbg.c. Change-Id: I799c8574e985f394eb653a7b7c54816ff409b058 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768259 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused declarationKonsta Holtta2018-07-05
| | | | | | | | | | | | | The function nvgpu_sgt_create() does not exist; we never create empty nvgpu_sgts. Delete its declaration. Change-Id: Ib3ea975b442ffd8d50e6e1002ace10d5642f3613 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770666 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix active fbpa mask calculationDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | In gr_gv100_get_active_fpba_mask(), we currently use num_fbpas passed by the caller which is usually litter (max possible on h/w) value We should instead read the number of FBPAs from h/w instead of reading litter value Jira NVGPUT-117 Change-Id: I6ecd4db0fd939e1dfebf31d27e0022ae02809399 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762721 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix pending bytes check for vidmemDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | | | In nvgpu_dma_alloc_flags_vid_at(), we check pending bytes of vidmem which are yet to be cleared by reading g->mm.vidmem.bytes_pending.atomic_var If there is something to be cleared we return EAGAIN otherwise we return ENOMEM But to store above variable we use "int before_pending" which evaluates to zero for sizes like 4GB and we end up returning ENOMEM instead of EAGAIN Fix this by declaring before_pending variable as u64 Bug 200427361 Change-Id: I6ffe977e3663a5135fa17699ecafe78ac90d9314 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770384 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to invalidate replay mmu faultDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | Add new HAL gops.fb.mmu_invalidate_replay() to invalidate replay mmu fault Use existing API gv11b_fb_mmu_invalidate_replay() to set to this HAL on all Volta chips Bug 2228914 Jira NVGPU-838 Jira NVGPUT-73 Change-Id: I394901857d41499f3ea44023393fe271fb664260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767970 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix ppc broadcast address splitDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_split_ppc_broadcast_addr() we convert a PPC broadcast address to its corresponding unicast address list But we consider gr.pe_count_per_gpc instead of actual number of PPCs and that leads to generating incorrect list of addresses Fix this by using gr.gpc_ppc_count[gpc_num] which gives correct number of PPC count Jira NVGPUT-117 Change-Id: If7e7c19244b90cb3c405dcba4ae7a86c782972f7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767838 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 SEC2 falcon code updateMahantesh Kumbar2018-07-05
| | | | | | | | | | | | | | | | | | - Added prefix gp106_ to sec2_wait_for_halt() & sec2_clear_halt_interrupt_status() for gp106 SEC2 HAL - Made changes to gp106_sec2_wait_for_halt() to read SEC2 falcon mailbox using common falcon mailbox access functions. - Add define for falcon mailbox - These changes are done to reuse gp106 HAL's for GPU_NEXT. Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1755618 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: SEC2 reset using common falcon HALMahantesh Kumbar2018-07-05
| | | | | | | | | | | | | | | | | | -Do sec2 reset using common falcon HAL nvgpu_flcn_reset() by passing sec2_flcn struct which holds base address of SEC2 falcon as per chip specific. JIRA NVGPUT-111 Change-Id: I2b95262a93644bbefed5b6c46dc73200afd97730 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1755617 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to get offset in gpccs segmentDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_find_priv_offset_in_buffer() we right now calculate offset of a register in gpccs segment based on register address type Separate out sequence to find offset in gpccs segment and move it to new API gr_gk20a_get_offset_in_gpccs_segment() Introduce new HAL gops.gr.get_offset_in_gpccs_segment() and set above API to this HAL Call HAL from gr_gk20a_find_priv_offset_in_buffer() instead of calling direct API Jira NVGPUT-118 Change-Id: I0df798456cf63e3c3a43131f3c4ca7990b89ede0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761669 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: expose CAN_RAILGATE in characteristicsKonsta Holtta2018-07-04
| | | | | | | | | | | | | | | Bug 200327089 Change-Id: Id7bd2795647f1e29dabe41acb20d0994cdd07958 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764267 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move can_railgate to enabled.hKonsta Holtta2018-07-04
| | | | | | | | | | | | | The g->can_railgate flag is a global constant-ish property like the rest of the flags behind nvgpu_is_enabled() API, so move it there. Bug 200327089 Change-Id: Id1f2f16ea1975a03fb56f10c2f3c8c705574e341 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reject submits when usermode is onKonsta Holtta2018-07-03
| | | | | | | | | | | | | | | | | Kernel mode submits conflict with user submits, so don't allow them if a channel user has asked for usermode submit support. Bug 200145225 Change-Id: I3a99222b09260a1b3e116c6aa86d8da5d380d903 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767907 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU_NEXT PMU ucode version updateMahantesh Kumbar2018-07-02
| | | | | | | | | | | | | | | | | - Enable ECC interrupt in Falcon interrupt source - Enable routing of ECC interrupt to HOST. code CL: https://git-master.nvidia.com/r/#/c/1758176/ p4 CL# 24408680 Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1758175 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement common nvgpu_mem_rd* functionsTerje Bergstrom2018-07-02
| | | | | | | | | | | | | | | | | nvgpu_mem_rd*() functions were implemented per OS. They also used nvgpu_pramin_access_batched() and implemented a big portion of logic for using PRAMIN in OS specific code. Make the implementation for the functions generic. Move all PRAMIN logic to PRAMIN and simplify the interface provided by PRAMIN. Change-Id: I1acb9e8d7d424325dc73314d5738cb2c9ebf7692 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753708 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix missing max frequencyVishruth2018-07-02
| | | | | | | | | | | | | | | | | | | The last frequency in the local array with all frequencies was missed as the index was used as count. This caused max frequency to be not listed among available frequencies, when few frequencies were configured in BPMPFW-DT. Bug 200381453 Change-Id: I72d000ed1842c41555f2de36209fa4e12188c325 Signed-off-by: Vishruth <vishruthj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767642 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make sure gpc2clk is greater than DVCO minThomas Fleury2018-07-01
| | | | | | | | | | | | | | | | | For V/f point with gpc2clk exactly equal to DVCO min, we observe lower than expected effective clock. Make sure min frequency for gpc2clk is greater than DVCO min. Bug 200412996 Change-Id: I85c33852c56c7a642aa5c85987d2da4147e73c22 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764923 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: adjust gpc2clk to nearest V/f pointThomas Fleury2018-07-01
| | | | | | | | | | | | | | | | | | | When requesting a gpc2clck below lowest V/f point, clock arbiter did not properly adjust target value to nearest V/f point. This could lead to lower than expected effective frequency. Fixed the logic to adjust to nearest V/f point. Bug 200412996 Change-Id: I36c24b4c081931e2ac54da14d49e46fcb14503e3 (cherry picked from commit 7ed1f8fb39f76208922daa91d00905cdb96b2304) Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763641 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove gk20a_channel_sync::incr_wfiKonsta Holtta2018-06-29
| | | | | | | | | | | | | | This explicit incr_wfi has not been used since commit 06be77da376f ("gpu: nvgpu: Do not send WFI when finishing channel"). Change-Id: I0213b0f728f83b483a7dbbef252912555b06815f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1765407 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move the unlock in nvgpu_vm_area_free againAlex Waterman2018-06-29
| | | | | | | | | | | | | | | | Move the lock release to cover the g->ops.mm.gmmu_unmap() call as well since this too must be called under the VM lock. Bug 2156667 Change-Id: I17d819d1341e211a3d0bd0ecb7cf09884eaca767 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764598 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove legacy comment noteKonsta Holtta2018-06-29
| | | | | | | | | | | | | | | | gk20a_channel_clean_up_jobs hasn't needed a barrier since commit d20a501dcbf2 ("gpu: nvgpu: simplify job semaphore release in abort"). Bug 200327089 Change-Id: I64b9e3b7970de232ac553f570b8fd41aec3b7e21 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764309 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: filter frequencies only when requiredVishruth2018-06-29
| | | | | | | | | | | | | | | | the logic used for selecting frequencies from achievable frequencies of the GPU clk is selecting one in a set of 8 frequencies. This reduces the number of available frequencies when the number of achievable frequencies is small. Change this implementation to choose all frequencies when the achievable frequency list is small. Bug 200381453 Change-Id: Ib280d7ccf9b75f88f6c7c6d2666f05e92a0343bd Signed-off-by: Vishruth <vishruthj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753289 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use explicit phys address for pci simulationDeepak Nibade2018-06-29
| | | | | | | | | | | | | | | | | | | | nvgpu_mem_get_addr() gets virtual/phys address depending on the platform. But we need to explicitly use physical addresses to configure PCI simulation support since simulator expects physical address only Hence use nvgpu_mem_get_phys_addr() explicitly to configure msg/send/recv buffers needed for pci simulation support Jira NVGPUT-41 Change-Id: I6870feef35fe81d43189fa048dc2f7052926bcc4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756843 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Keep lock while unreffing mappingsAlex Waterman2018-06-28
| | | | | | | | | | | | | | | | | | In the vm_area free code, when unreffing the mappings owned by the vm_area, we need to continue holding the VM lock. Also add a comment specifying this requirement in the VM code. Bug 2156667 Change-Id: If0b430f045e4c585fcba2d3176163e5b19be8326 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763235 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove nvgpu_mem_{begin,end}()Konsta Holtta2018-06-28
| | | | | | | | | | | | | | | The NVGPU_DMA_NO_KERNEL_MAPPING flag is going away, and these functions are no longer used. Delete them. Change-Id: I0084d64c92783dd65306871e5cf6bd6366087caf Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761581 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't nvgpu_mem_{begin,end}() sim bufsKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | nvgpu_dma_alloc_sys() gives cpu-mapped memory by default. Remove the explicit calls to map and unmap the sim buffers. Change-Id: Icf71961c16a8b2f5dae24382cc927c7a802a769a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761580 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove {map,unmap}_gmmu_pages()Konsta Holtta2018-06-28
| | | | | | | | | | | | | | | The GPU page tables are always mapped to the CPU now, so they don't need the nvgpu_mem_{begin,end}() calls. Change-Id: Ic48eeed3a6f002c78f89ef07922cddf835337de3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761579 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 01:41:15 -0500