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* gpu: nvgpu: Use common VM deinitTerje Bergstrom2015-04-04
| | | | | | Change-Id: Ia9aa9cfaaad9e43820fc47f6620bf01c435dad23 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/718726
* gpu: nvgpu: Allow sparse buffers on small pagesTerje Bergstrom2015-04-04
| | | | | | | | | | | Sparse buffers were allowed only with big pages. That restriction is not necessary, so remove it. Bug 1605769 Change-Id: I92efc0efe80edccead47b47d33fd9a75c921ca9a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725763
* gpu: nvgpu: Use common allocator for contextTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I10c226e2377aa867a5cf11be61d08a9d67206b1d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720507
* gpu: nvgpu: don't idle if busy fail in set zbc tblKonsta Holtta2015-04-04
| | | | | | | | | | Move gk20a_idle() under error check in NVGPU_GPU_IOCTL_ZBC_SET_TABLE so that if gk20a_busy fails, the idle is skipped properly. Change-Id: Iffde3734f7fb121e1bc7838a67bfee3dacfd0a46 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/726104 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add priv ring error spewTerje Bergstrom2015-04-04
| | | | | | | | Spew debug lines in case we get a priv ring error. Change-Id: Iba46813a355b5d2d192614a9e146397688e130a7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660850
* gpu: nvgpu: Regenerate HW headersTerje Bergstrom2015-04-04
| | | | | | | | Added fuse for FBP and DS exception register. Change-Id: Ie38a84eac40ca2d8cf3ac8f19ed6bad0d6bc1dd9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/722846
* gpu: nvgpu: Fix the GPFIFO submit conditionGagan Grover2015-04-04
| | | | | | | | | | | | | | | | GPFIFO HW with fifo size N can actually accept N-1 entries. Also, kernel can insert two extra entries, before and after the user GPFIFOs. So, GPFIFO with N size can accept max N-3 user gpfifos. Bug 1613125 Change-Id: I173526afb70dddf1b2b9ec0a99890335c81f0e02 Signed-off-by: Gagan Grover <ggrover@nvidia.com> Reviewed-on: http://git-master/r/725380 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix invalid "reset initiated" printsDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | Improve the error path and return values from function gk20a_fifo_handle_sched_error() - return true, when we trigger the recovery in this function - otherwise, return false No need to reset the scheduler error register in this function, since we anyway clear the interrupt in fifo_error_isr() Also, fix the typo "reset initated" -> "reset initiated" Bug 200089043 Change-Id: Ibfc2fd2133982a268699d08682bcd6f044a3196a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/722711 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use sg_alloc_table_for_pagesTerje Bergstrom2015-04-04
| | | | | | | | | | | | | Use sg_alloc_table_for_pages to create sg_table for buffers allocated with NO_KERNEL_MAPPING. The old code returned always an sg_table with one chunk. sg_alloc_table_for_pages returns an sg_table which describes the actual physical chunks of the buffer. Bug 1605769 Change-Id: I412c0151d830fa0f53dbbb08ba8cc9ebce6699e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/723696
* gpu: nvgpu: Fix error paths in init vmTerje Bergstrom2015-04-04
| | | | | | | | Error paths called the wrong cleanup sections. Change-Id: I603af77bf8e3981c029bcf6d582882e51847f137 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/722949
* gpu: nvgpu: Increase GPFIFO priv cmd queue sizeTerje Bergstrom2015-04-04
| | | | | | | | | We're doing two sync point increments, so we need to allocate space for it. Change-Id: I663abb18a930eb3955379d5f8dd1b08c8fa56897 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719884
* gpu: nvgpu: fix sparse tool warningsSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: -drivers/gpu/nvgpu/gk20a/gr_gk20a.c:6028:6: warning: symbol 'gr_gk20a_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gk20a.c:6174:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gk20a.c:6184:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? -gr_gm20b.c:465:6: warning: symbol 'gr_gm20b_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gm20b.c:476:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gm20b.c:486:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? Bug 200067946 Change-Id: Ic14080e94e343386f4fef379152a623c402984fd Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/723518 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Fix offset of PC sampling fieldTerje Bergstrom2015-04-04
| | | | | | | | | | | Fix offset of PM word when changing PC sampling field. Bug 1517458 Bug 1573150 Change-Id: I2b8489b1d3c05f3a20416fc1a46ac1827f453cbc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721032
* gpu: nvgpu: add platform specific get_iova_addr()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add platform specific API pointer (*get_iova_addr)() which can be used to get iova/physical address from given scatterlist and flags Use this API with g->ops.mm.get_iova_addr() instead of calling API gk20a_mm_iova_addr() which makes it platform specific Bug 1605653 Change-Id: I798763db1501bd0b16e84daab68f6093a83caac2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713089 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: improve error print in check_gp_put()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | Improve error print in check_gp_put() and dump put pointer stored in channel's gpfifo structure and the put pointer that we read from memory Bug 200089835 Change-Id: I7e854398811330a43d9d9bf86bf29c5986ab22b7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/722536 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix comptag index in traceTerje Bergstrom2015-04-04
| | | | | | | | | Instead of comptag index we were dumping an offset in buffer. Change-Id: Iaa07919c8d87009227556eacbcb6dcbd83954c7d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/718597 Reviewed-by: Automatic_Commit_Validation_User
* tegra: gpu: disable touch boost for gpuSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | Gpu boosting with input events is causing more gpu power consumption than required. To avoid this, touch boot for gpu is disabled by not registering gpu device for cfboost frame work. Current rail gate entry/exit latencies are fast enough to give smooth user experience. Bug 200087243 Change-Id: I18673d9c95a44ce9bee87e860b4edb29212dc766 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/721989 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use common allocator for compbit storeTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I7c1662b669ed8c86465254f6001e536141051ee5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720435
* gpu: nvgpu: Helper for no kernel mapping allocTerje Bergstrom2015-04-04
| | | | | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by introducing a variant of allocation helper that does not map the allocated buffer to kernel address space. NO_KERNEL_MAPPING allocations return a struct page **, so store the results of allocation in a new field of mem_desc. Bug 1605769 Change-Id: Ib760b9e6d34b229b04d1fb4f3abf10648670fc69 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721029
* gpu: nvgpu: Use common allocator for GPFIFOTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I81701427ae29b298039a77f1634af9c14237812e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719872
* gpu: nvgpu: Use common allocator for cmd queueTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: If93063acbbfaa92aef530208241988427b5df8eb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719871
* gpu: nvgpu: Skip debug dump on stuck syncpointTerje Bergstrom2015-04-04
| | | | | | | | Skip dumping full debug spew on stuck syncpoint. Change-Id: I22c019bac23c4530229e20c0f8ce00806e23d9a1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719876
* gpu: nvgpu: Catch DS exceptionTerje Bergstrom2015-04-04
| | | | | | | | Catch DS exception and write an error to UART. Change-Id: Iaad9813c48191f0d3d734d4af264b976a3818672 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679142
* gpu: nvgpu: GM20B extended buffer definitionSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | Update extended buffer definition for Maxwell. On GM20B only PERF_CONTROL0 and PERF_CONTROL5 registers are restored in extended buffer. They are needed for stopping the counters as late as possible during ctx save and start them as early as possible during context restore. On Maxwell, these registers contain the enable/disable bit. Bug 200086767 Change-Id: I59125a2f04bd0975be8a1ccecf993c9370f20337 Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/717421 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set default timeout to 5sTerje Bergstrom2015-04-04
| | | | | | | | | | 10s is a too long timeout. Set it to 5s. Change-Id: I7093a8ee5bb27828f27cd06a5b3899a4f2df6280 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717042 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: tegra gpu to emc frequency mappingAnders Kugler2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | o emc clock scaling Only take the gpu load into account for gpu frequencies below fmax @ Vmin. The granularity of frequency steps is much larger in the gpu frequency range below fmax @ Vmin than in the upper frequency range. Above fmax @ Vmin, keep the gpu unblocked and disregard the gpu load when evaluating the emc target. o tegra_postscale() Round the new emc target to nearest discrete frequency. Set the emc frequency only if the new emc target is different from the previously requested emc frequency to avoid the penalty of the locks inside clk_set_rate(). Bug 1591643 Change-Id: I1a1a8734a74569c4d57b6e2bda4c11b2bda3f5f3 Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/680937 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Infinite syncpt wait on presiliconTerje Bergstrom2015-04-04
| | | | | | | | | On presilicon, syncpt waits should have infinite timeout. Change-Id: Ifa9b2fa0ef164e2f87a631bca77941e995b06ad4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717947 Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
* gpu: nvgpu: Cache channel state before dumpingTerje Bergstrom2015-04-04
| | | | | | | | | | | Split channel debug dump into two phases. In first phase we just copy the data to a temporary buffer, and in second phase we dump the state from the temporary buffer. Change-Id: I2578b9fdaaa76f1230df7badbca9fcb5f3854e56 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717886 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Use gk20a_mem_phys instead of sg_physTerje Bergstrom2015-04-04
| | | | | | | | | There were still a couple of places using sg_phys directly. Use new gk20a_mem_phys() to make the code shorter. Change-Id: I6eb9b14e0c14a27ec39bacd06ab24e31e99769ca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/717502
* gpu: nvgpu: Do not touch gr status maskTerje Bergstrom2015-04-04
| | | | | | | | | GR status disable mask was never set, so driver always disabled all engines from status rollup. Change-Id: I500a127be9253294f73d1f42ce89b886471a9117 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719141
* gpu: nvgpu: zbc: disable activity only from ioctlKonsta Holtta2015-04-04
| | | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: Ia3d768b7ad2d829416a1144486e6788d3177eb04 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715195 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make the local function staticAmit Sharma (SW-TEGRA)2015-04-04
| | | | | | | | | | | | | | | | | | | Fixed the following sparse warnings by making below APIs static: - gk20a.c: warning: symbol 'gk20a_pm_restore_debug_setting' was not declared. Should it be static? - gr_gk20a.c: warning: symbol 'gr_gk20a_rop_l2_en_mask' was not declared. Should it be static? - gr_gm20b.c: warning: symbol 'gr_gm20b_rop_l2_en_mask' was not declared. Should it be static? Bug 200067946 Change-Id: I334893bb6614171bff835d270716a7dd262c9ba7 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/718756 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: use vmalloc for temp gpfifo in submitKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | Use vmalloc instead of kzalloc for the temporary gpfifo buffer copied from userspace in the ioctl when submitting gpfifos. The data may be too big for kzalloc, and it doesn't need to be physically contiguous. Bug 1617747 Bug 200081843 Change-Id: I66a43d17eb13a2783bc1f0598a38abbf330b2ba6 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715207 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: 3d.emc frequency scalingAnders Kugler2015-04-04
| | | | | | | | | | | | | | | | | | | | o QoS notifier Refresh the gpu load query because we may update the emc target if gpu load changed. o tegra_postscale() Scaling the emc clock to a new target may be necessary if the gpu load changed at low gpu frequencies. Bug 1591643 Change-Id: Ibc6f73c02eaf6cedb7f0f579d5f4d90c735d354a Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/680929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: vgpu: add new attributesAingara Paramakuru2015-04-04
| | | | | | | | | | | | Add support for reading num FBPs and FBP enable mask. Bug 1621056 Change-Id: I92ec1123373308ed280d4ffd30fe77ae6073ac45 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/715826 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reduce gr delaysSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | The delay value used in gr usleep_range calls is too high. We can start at a much lower value. Change-Id: Id141df70b8892bc1ed1b49623c4aa125d541a636 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/715928 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: print also fifo_intr in reset logKonsta Holtta2015-04-04
| | | | | | | | | | | | Print the interrupt code for diagnostics when logging the message about channel reset in fifo_error_isr. Change-Id: I44e9eb818af7264671f1c804d9a77b14c197457d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715804 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: wake-up gpu for rail gating delay settingSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | Currently new gpu rail gating delay is not effective until next gpu rail gate and ungate. To make new rail gate delay effective immediately, wakeup gpu after setting new delay. Change-Id: I80889687e9d3d577ea783cdf5688074c06d602cf Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/714961 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement common allocator and mem_descTerje Bergstrom2015-04-04
| | | | | | | | | | Introduce mem_desc, which holds all information needed for a buffer. Implement helper functions for allocation and freeing that use this data type. Change-Id: I82c88595d058d4fb8c5c5fbf19d13269e48e422f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712699
* gpu: nvgpu: Skip reg read of gpc2clkSupriya2015-04-04
| | | | | | | | | | | | | | Bug 200066741 As we are just getting out of reset and this reg is not written before, so we dont stand the risk of loosing any data Change-Id: Ifc1bcaa3c224038e4e2a47882a4523f7633cb660 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/715652 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Correct irq and elpg disable sequenceSupriya2015-04-04
| | | | | | | | | Bug 200066741 Change-Id: I873835c8aff0c53ac475090d727754ce1ccca0ee Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/715632 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Gpu characterstics enhancementsujeet baranwal2015-04-04
| | | | | | | | | | | New members are added in nvgpu_gpu_characterstics to export more information required specially from CUDA tools. Change-Id: I907f3bcbd272405a13f47ef6236bc2cff01c6c80 Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/679202 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Removal of regops from CUDA driversujeet baranwal2015-04-04
| | | | | | | | | | | | | | | | The current CUDA drivers have been using the regops to directly accessing the GPU registers from user space through the dbg node. This is a security hole and needs to be avoided. The patch alternatively implements the similar functionality in the kernel and provide an ioctl for it. Bug 200083334 Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/711758 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu: add support for unmapped ptesSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | Add support for unmapped ptes during gmmu map. Bug 1587825 Change-Id: I6e42ef58bae70ce29e5b82852f77057855ca9971 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/696507 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: do not enable unhandled exceptionsDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | | We currently have below exceptions enabled but we do not have any handler for them. So if any of these exception is raised, we do not clear it. NV_PGRAPH_EXCEPTION_PD NV_PGRAPH_EXCEPTION_SCC NV_PGRAPH_EXCEPTION_DS NV_PGRAPH_EXCEPTION_MME NV_PGRAPH_EXCEPTION_SKED Hence do not enable above exceptions. Bug 200078514 Change-Id: I0dd3a2299f80f3fe06994818f64151e7cc83a84e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/714166 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle memfmt exceptionDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | In gk20a_gr_isr(), handle memfmt exception as below : - read NV_PGRAPH_PRI_MEMFMT_HWW_ESR - debug print for contents of above register - write same value back to NV_PGRAPH_PRI_MEMFMT_HWW_ESR and clear the exception Bug 200078514 Change-Id: I5b9afacd7f99b5a37de953041582b3a53b863642 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713713 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* sync: Support timestamp passingMichael Frydrych2015-04-04
| | | | | | | | | | | | | | | | | Timestamps read in an interrupt handler and when fence state is being updated can differ by variable amount. That add unnecessary jitter to original interrupt times. This patch adds support for passing timestamp from the device driver thereby allowing more accurate timestamps. Bug 1543760 Change-Id: Idcfd5cb435b0bd585e3c16cd299c6f456d4509c4 Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/360939
* gpu: nvgpu: Add DT support for gpu power-domainSumit Singh2015-04-04
| | | | | | | | | | | | | First, defining a new structure to support gk20a power domain. Then making necessary modifications to add so as to add DT support for gpu power-domain. bug 200070810 Change-Id: I29e1c24b181e14743d3969103abfd1882d171f07 Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/668973 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: support for dumping vpr/wpr infoSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | | Added support for dumping vpr/wpr info for gm20b. This dump info called when ever gk20a_mm_fb_flush is timed-out. Bug 200082817 Change-Id: I21b0372d0e3f976a189c9c428c015165b715bf88 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/711439 (cherry picked from commit b69897d71c8f6119b49ceb8d3273cdb354178cc5) Reviewed-on: http://git-master/r/712675 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Use busy looping for flush operationsSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | | | | | | | Use busy looping for l2 tag flush and elpg flush operations. This is making total flash time more accurate and reduced overall time compared with usleep. Also added trace points to measure performance for these operations. Also corrected timeout error check for non-silicon platforms. Bug 200081799 Change-Id: I63410bb7528db9258501633996fbdee5fdec1c74 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/710472 (cherry picked from commit 18684cf9d5d6870a1a1fd5711c4fc2d733caad20) Reviewed-on: http://git-master/r/710986 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 00:17:10 -0500