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* gpu: nvgpu: Add uapi support for NVGPU_GPU_IOCTL_GET_ENGINE_INFOLakshmanan M2016-06-10
| | | | | | | | | | | | | | | | Implement NVGPU_GPU_IOCTL_GET_ENGINE_INFO for retrieving the list of supported engines and their corresponding run list id:s. JIRA DNVGPU-25 Change-Id: I8703388660190f7dcb509c0676f283ca4b820b6f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1160939 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsLakshmanan M2016-06-10
| | | | | | | | | | | | | | | | | | | | Fixed the following sparse warnings: - warning: symbol 'gm206_ce_isr' was not declared. Should it be static? - warning: symbol ''gm206_ce_nonstall_isr' was not declared. Should it be static? Bug 200088648 Change-Id: I30f66ba4225d5544d6110bc4a70235234ad4001d Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161604 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix event id pollingDeepak Nibade2016-06-10
| | | | | | | | | | | | | | | | | | | In gk20a_event_id_poll(), we always set the mask value and return it. This causes poll() from UMD to be always successful irrespective of event is really generated or not Fix this by adding a flag event_posted for each event Set this flag while posting the event In gk20a_event_id_poll(), set the mask value only if this flag is set. If flag is set, set mask and clear the flag Bug 200089620 Change-Id: If14236547c611fe4bfa1410ff5b69c9fa02d43bb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1160253 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR interface updateMahantesh Kumbar2016-06-09
| | | | | | | | | | | | | | | - ACR interface update to support next GPU chip ACR boot - Udpate falcon ID JIRA DNVGPU-34 Change-Id: Ic9e5e1f9bd965dbb65b4feaadcf63e457b49263b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161695 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update PMU version, interface & codeMahantesh Kumbar2016-06-09
| | | | | | | | | | | | | | | | | - update PMU interface/code to support latest version of secure boot FW - Add PMU FW version for next GPU support - can_elpg check in pmu_setup_hw helps to fix queue error JIRA DNVGPU-34 Change-Id: Iecf47fbc5b71cbf0f4bcdfeafad5c635cb6bff82 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161107 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add general event supportRichard Zhao2016-06-09
| | | | | | | | | | | | | | | | Events like bpt int/pause will help cuda work properly. Bug 200173403 VFND-1568 Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159621 (cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda) Reviewed-on: http://git-master/r/1152154 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel enable supportRichard Zhao2016-06-09
| | | | | | | | | | | | | | Bug 200173403 VFND-1568 Change-Id: I3636a77bbbbd719e961dce5ca7ca7bdd5aa33881 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159620 (cherry picked from commit b22fb6518da15a09c3e298213af5e60b8e6907a2) Reviewed-on: http://git-master/r/1155403 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel force resetSachit Kadle2016-06-09
| | | | | | | | | | | | | | | | Add forced channel reset support for vgpu Bug 200187507 JIRA EVLR-337 Change-Id: I48e3e2b430f3a4ae94244225232902a8c037cb07 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1154781 (cherry picked from commit abd6688801fe76c822d6f67f554c18705d9f23d6) Reviewed-on: http://git-master/r/1161259 GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: take power refcount in ISR"Terje Bergstrom2016-06-09
| | | | | | | | | This reverts commit 2219f38727ffa17291e15c1898bd3e65f43d09fd. It leaves GPU in on state for some tests that require powering down GPU. Change-Id: I79d44fed729e98692021c57bbeff6a0ef2e8c983 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1161846
* gpu: nvgpu: include matching header in mm_gm106.cKonsta Holtta2016-06-09
| | | | | | | | | | | | | Include mm_gm106.h in mm_gm106.c to bring function declarations visible and to fix a Sparse warning. Bug 200088648 Change-Id: Ifbedafdd75ce0ee019b39d507b8b113cccdc8918 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1161608 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: detect vidmem configuration from HWKonsta Holtta2016-06-08
| | | | | | | | | | | | | Read video memory size from hardware during initialization for devices that support it. JIRA DNVGPU-14 Change-Id: If190f2d89f7148520ee274ca674f972987c8056d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157215 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: take power refcount in ISRDeepak Nibade2016-06-08
| | | | | | | | | | | | | | | | | | | | | | | | We sometimes see race conditions where power refcount is zero during ISR or bottom half. If bottom half calls gk20a_busy(), it will lead to boot up of GPU, but it is also possible that we are already trying to poweroff GPU since power refcount is zero Fix this by taking a power refcount with gk20a_busy_noresume() in ISR and then dropping this refcount at the end of bottom half Add new API gk20a_idle_nosuspend() to drop a refcount without initiating suspend Bug 200198908 Bug 1770522 Change-Id: Iec3d4dc8d468f49b71919d2bbc327da48b97bcab Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1160035 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Update PMU version for gk20aSupriya2016-06-07
| | | | | | | | | | | | | | | | | -T124 P4 Cl for the change 20824361 -P4 CL Removes accesses to ZBC L2 save/restore -during ELPG Bug 1746047 Bug 200204625 Change-Id: I5a52de7de51e723eae02f82c6c6fc9a213f9cd0e Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1159464 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add call back for get_cur_freqsreenivasulu velpula2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | | When thermal throttling triggers gpcclk clock changes, devfreq driver need to have call back for get_cur_freq to get current gpu frequency. With out this change, "17000000.gp10b/cur_freq" interface won't show the current gpcclk frequency, when thermal throttling triggers gpcclk frequency changes. Bug 1740309 Change-Id: I2484728094883abc285b2a3808bb2cef26a4ea96 Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com> Reviewed-on: http://git-master/r/1145912 (cherry picked from commit 0a6ef7b121d1b8aeba42cefa6e8b090b1ccd15e7) Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1147652 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove clockgate_delay paramSeshendra Gadagottu2016-06-07
| | | | | | | | | | | | Removed platform data parameter clockgate_delay, since it is not really used for gpu clock gating any more. Also use railgate_delay as autosuspend delay instead of clockgate_delay. Change-Id: I5b594b5a0e84295ed9971ecdf4865dc1a7dd936d Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1159593 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cache whole bar0_window for mem accessesKonsta Holtta2016-06-07
| | | | | | | | | | | | | | Save the whole bar0 window register that encodes also the target aperture (vid/sys mem) instead of only the base address that could overlap between the two. JIRA DNVGPU-23 Change-Id: I2ccbea0e1f7c7310c1ca6b158afafe8fd974a615 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1159523 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu: add sysfs nodes for ptimer freqSeshendra Gadagottu2016-06-06
| | | | | | | | | | | | | | | | | | | | | | With current ptimer_scale_factor sysfs node, some precision is lost while converting scaling factor to floating point and similarly more precision will be lost while converting back to fixed point. To avoid this, kernel will export following two sysfs nodes: ptimer_ref_freq : ptimer reference frequency( in hz) ptimer_src_freq : ptimer source frequency (in hz) in current chip architecture. Client will apply proper scaling factor by doing ptimer_ref_freq / ptimer_src_freq. Change-Id: I84516e235cc3fffe4cb9a73903416478f4050a9a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1139985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: vgpu: add support for max_freqPeter Daifuku2016-06-06
| | | | | | | | | | | | | | | | | | Add vgpu support for max_freq characteristic Bug 200182714 JIRASW VFND-1570 Change-Id: Ibeddfbba1bf0529d6f576cefcb82978dbae315d1 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1149216 (cherry picked from commit 8e8b5979e87268401d5b0fc658a73589710a2e09) Reviewed-on: http://git-master/r/1155416 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: return if no fecs intrDeepak Nibade2016-06-06
| | | | | | | | | | | | | | | In gk20a_gr_handle_fecs_error(), if we do not see any error interrupt from gr_fecs_host_int_status_r(), just return immediately Bug 1646259 Change-Id: Iea037e0dab57111d2a0fb41c5c19529b7d6c83c0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1158591 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu; pmu version updateMahantesh Kumbar2016-06-06
| | | | | | | | | | | | | | | | | - P4 CL 20527959 - pmu version update for idle slowdown ucode CL http://git-master/r/#/c/1029404/ - configure LDIV slowdown factor to BY16 using linear slowdown NV_THERM_FPDIV_BY16-0x1e value Bug 200144583 Change-Id: Id15441a88ca980ab3f4f8a70e86cae5e59976829 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1159232 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix calculation of timeoutTerje Bergstrom2016-06-05
| | | | | | | | | | | Fix calculation of timeout in multiple places. The #defines GR_IDLE_CHECK_DEFAULT and GR_IDLE_CHECK_MAX are meant to be used only for defining the frequency of checking for timeout. Using them for actual timeouts makes the timeout really short. Change-Id: I3d0f8cbc91d619be8e5a9168ee1ab1d6298f129b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1158269
* gpu: nvgpu: enable gm204/gm206 GPMU secure bootMahantesh Kumbar2016-06-05
| | | | | | | | | | | | enable gm204/gm206 GPMU secure boot & build. JIRA DNVGPU-11 Change-Id: I3502d227d0baad9e3a27f46d1d6b0d2a83503b6c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156331 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU support for gm204/gm206Mahantesh Kumbar2016-06-05
| | | | | | | | | | | | | | Adding PMU modules to boot & comunicate with PMU F/W JIRA DNVGPU-11 Change-Id: I5afc9209f70fc13376268f9c94daef6b75527c71 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156028 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU interface's for gm204/gm206Mahantesh Kumbar2016-06-05
| | | | | | | | | | | | | | Adding PMU interface's to support gm206/gm204 JIRA DNVGPU-11 Change-Id: I55671239cdb44804e7dd740d5e22a54e668005f4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1155940 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add gm204/gm206 ACR BL supoortMahantesh Kumbar2016-06-05
| | | | | | | | | | | | Update ACR BL desc & support for ACR boot. JIRA DNVGPU-10 Change-Id: Iced2e10695439b2e1b47835f5c3c8a5d274e4b1e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1155027 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add context reset at golden context initTerje Bergstrom2016-06-04
| | | | | | | | | | | | | | | | | | Part of golden context initialization is in powerup sequence, and part done as part of first channel creation. The sequence is missing a context reset, which causes initialization of golden context to fail on dGPU. Just moving the code to golden context initialization does not work, because iGPU can be rail gated, and part of the sequence is required in GPU boot. Thus a part of context initialization is replicated to golden context init after a context reset. Change-Id: Ife1b167447018317d3a692b706880e0eda073e43 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1130698
* gpu: nvgpu: WPR & PMU interface updateMahantesh Kumbar2016-06-04
| | | | | | | | | | | | | Update WPR interface & PMU interface to support latest ACR/PMU ucode versions Change-Id: I4d1bd7a5c43751e96c1db58832cd316006d56954 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1158070 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct config for t19xSeshendra Gadagottu2016-06-03
| | | | | | | | | | | | | | | Use TEGRA_19x_GPU config instead of ARCH_TEGRA_19x_SOC for t19x functionality. This config will defined only when gpu repository for t19x is available. Bug 1757988 Change-Id: I53421f31cbed49a2fb24085c150599c78b8158c0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1158183 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: source t19x specific KconfigSeshendra Gadagottu2016-06-02
| | | | | | | | | | Bug 1757988 Change-Id: I3efc3368cadd83c8334868d19c63f464e4925b27 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1157319 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add t19x functionality conditionallySeshendra Gadagottu2016-06-02
| | | | | | | | | | | | | | Include t19x functionality only when config TEGRA_T19x_GPU is enabled. Bug 1757988 Change-Id: I049f134d92c4ffdeeed2bc513579f7d9d396ff41 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1155297 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: include makefiles conditionallySeshendra Gadagottu2016-06-01
| | | | | | | | | | | | | | Include chip specific makefiles, only if they are present in current source tree. Bug 1757988 Change-Id: I60a468bce6e0d20459aa643ccbce9bacbcd163bf Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1154761 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix TSG abort sequenceDeepak Nibade2016-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_fifo_abort_tsg(), we loop through channels of TSG and call gk20a_channel_abort() for each channel This is incorrect since we disable and preempt each channel separately, whereas we should disable all channels at once and use TSG specific API to preempt TSG Fix this with below sequence : - gk20a_disable_tsg() to disable all channels - preempt tsg if required - for each channel in TSG - set has_timedout flag - call gk20a_channel_abort_clean_up() to clean up channel state Also, separate out common gk20a_channel_abort_clean_up() API which can be called from both channel and TSG abort routines In gk20a_channel_abort(), call gk20a_fifo_abort_tsg() if the channel is part of TSG Add new argument "preempt" to gk20a_fifo_abort_tsg() and preempt TSG if flag is set Bug 200205041 Change-Id: I4eff5394d26fbb53996f2d30b35140b75450f338 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157190 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct APIs for disable and preemptDeepak Nibade2016-06-01
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_ctx_zcull_setup(), gr_gk20a_update_smpc_ctxsw_mode(), and in gk20a_channel_suspend(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above functions which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: Ieed378dac4ad2322b35f9102706176ec326d386c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157189 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update HAL of ACR BLMahantesh Kumbar2016-06-01
| | | | | | | | | | | | | -update HAL of ACR BL which can support gm204/gm206 and DMATRFBASE method to global JIRA DNVGPU-10 Change-Id: I56fc7ce040dadb6473f6f375ee6ce90783a046ad Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154954 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fixing sparse error/warningMahantesh Kumbar2016-06-01
| | | | | | | | | | | | | | | | | - nvgpu/gm20b/acr_gm20b.c:88:6: warning: symbol 'gm20b_wpr_info' was not declared. Should it be static? - nvgpu/gm20b/acr_gm20b.c:1052:5: warning: symbol 'gm20b_bootstrap_hs_flcn' was not declared. Should it be static? Bug 200067946 Change-Id: I600f06055bd896a88eed5f5549310aa057f86e19 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1156054 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pid retrieval on tsg resetThomas Fleury2016-05-31
| | | | | | | | | | | | | | | | | | | On engine reset, an event is generate for FECS trace. In case a TSG context is currentlu loaded on GR engine, we retrieve the pid of the TSG from the first channel in the ch_list. Fixed invalid invocation of list_entry that led to crash. Bug 200193891 Change-Id: I79358bbb6685748cde68396ce220ab7b660d414d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1154811 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix timeout on FECS trace flushThomas Fleury2016-05-31
| | | | | | | | | | | | | | | When resetting GR engine flush FECS trace before halting the pipeline. Otherwise FECS remains in sideband method processing loop, and we get a timeout on FECS trace flush Bug 200193891 Change-Id: I137ea20eb1fb4ef6d618cd01cd3c096471eb8fb0 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1155240 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix bug in CHANNEL_FORCE_RESETAingara Paramakuru2016-05-31
| | | | | | | | | | | | | Channels belonging to a TSG did not have their error notifier set correctly. This was due to using an incorrect TSG id. Bug 1617046 Change-Id: Icb6911c7d79a9d02d7713bb47a7cbb24c3098dc1 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1155293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Free unbound channelsTerje Bergstrom2016-05-31
| | | | | | | | | | | If a channel cannot be allocated a GPFIFO, its status will remain unbound. We still need to free the channel when the fd gets closed. Bug 1769481 Change-Id: I8a9170f431cfa98dcf9e3cbc082393f02d2203db Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1154725
* nvgpu: vgpu: add tsg set interleave supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | added a new cmd to support setting tsg interleave level. Bug 1702773 VFND-1492 Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1145024 (cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785) Reviewed-on: http://git-master/r/1150706 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add tsg set timeslice supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | Bug 1702773 JIRA VFND-1496 Change-Id: Ice570df78d974fa59f2a932caf0e6249b13493a1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144929 (cherry picked from commit 8b6ec996f3773e497a040a8fe4148e01e8dc35fa) Reviewed-on: http://git-master/r/1150705 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add tsg support for vgpuRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | | | - make tsg_gk20a.c call HAL for enable/disable channels - add preempt_tsg HAL callbacks - add tsg bind/unbind channel HAL callbacks - add according tsg callbacks for vgpu Bug 1702773 JIRA VFND-1003 Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144932 (cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7) Reviewed-on: http://git-master/r/1126942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: manage gr_ctx as independent resourceRichard Zhao2016-05-31
| | | | | | | | | | | | | | | gr_ctx will managed as independent resource in RM server and vgpu can get a gr_ctx handle. Bug 1702773 Change-Id: I87251af61711f0d7997ce90df8a3de196a9b481a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144931 (cherry picked from commit 2efbd143adaf60570121f1c212dc6b6f3d5a1661) Reviewed-on: http://git-master/r/1150704 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add notifier for pbcrc mismatchDeepak Nibade2016-05-31
| | | | | | | | | | | | | | | | | | Add below notifier for pbcrc mismatch NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH And use this notifier value when we have pbdma pbcrc interrupt pending Bug 200179981 Change-Id: I289351e990afb0a4e002902881b99023530f6443 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1156210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: disable/preempt TSG for hwpm updateDeepak Nibade2016-05-30
| | | | | | | | | | | | | | | | | To update hwpm, we currently disable/preempt only one channel without considering if channel could be part of a TSG Hence, use proper APIs to disable/preempt/enable which will internally handle channel/TSG case Bug 200203191 Change-Id: I329a3c02d635265775f2081abba8e047f491fe7d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155838 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-05-30
| | | | | | | | | | | | | | Fix below sparse warning : $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pci.c:145:14: warning: symbol 'nvgpu_pci_class' was not declared. Should it be static? Bug 200088648 Change-Id: Ia3e8f1ae426fa72254b5204da0f6f85502b4670c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1155981 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-05-27
| | | | | | | | | | | | | Added device_info_data parsing support for maxwell GPU series. JIRA DNVGPU-26 Change-Id: I06dbec6056d4c26501e607c2c3d67ef468d206f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151602 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use correct IO register pointerTerje Bergstrom2016-05-27
| | | | | | | | | | | | | Use correct IO register pointer in cyclestats code. The code used reg_mem which is not supposed to be used. It is defined only on iGPU. Change-Id: I03cdaf5d2add2bf2c7cc6d7b3c41ac3be0f9a768 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1154708 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: align DMA base in chip HAL methodMahantesh Kumbar2016-05-27
| | | | | | | | | | | | | | | align DMA base in chip HAL method instead in generic method. Bug N/A Change-Id: I47a250380e083f393677b65c13d0c2c894214ca7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154909 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 03:18:40 -0400