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* gpu: nvgpu: fix NVGPU_COND_WAIT_INTERRUPTIBLEThomas Fleury2019-10-11
| | | | | | | | | | | | | | | | | | | | | | | | When called with timeout=0, NVGPU_COND_WAIT_INTERRUPTIBLE macro ignores the return code from wait_event_interruptible. As a result we do not detect when the call is interrupted, and the calling process hangs. Use wait_event_interruptible return code in case of infinite timeout. Bug 200384829 Bug 200543218 Change-Id: I930f0d08c73a3b91ab20a6c8faaf633a3d7aee4d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1982242 (cherry picked from commit 78c513790ac64605cea673c26e6d0d71c3d8db0a) Reviewed-on: https://git-master.nvidia.com/r/2215159 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix PMU destroy sequenceAbhiroop Kaginalkar2019-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A call to exit the PMU state machine/kthread must be prioritized over any other state change. It was possible to set the state as PMU_STATE_EXIT, signal the kthread and overwrite the state before the kthread has had the chance to exit its loop. This may lead to a "lost" signal, resulting in indefinite wait during the destroy sequence. Faulting sequence: 1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy() 2. cond_signal() 3. pmu_state = PMU_STATE_LOADING_PG_BUF 4. PMU kthread wakes up 5. PMU kthread processes PMU_STATE_LOADING_PG_BUF 6. PMU kthread sleeps 7. nvgpu_pmu_destroy() waits indefinitely This patch adds a sticky flag to indicate PMU_STATE_EXIT, irrespective of any subsequent changes to pmu_state. The PMU PG init kthread may wait on a call to NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a corresponding call to nvgpu_cond_signal_interruptible() as the core kernel code requires this task mask to wake-up an interruptible task. Bug 2658750 Bug 200532122 Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36 Signed-off-by: Abhiroop Kaginalkar <akaginalkar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2177112 (cherry picked from commit afa49fb073a324c49a820e142aaaf80e4656dcc6) Reviewed-on: https://git-master.nvidia.com/r/2190733 Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu memtest: put memory ref countBruce Xu2019-09-12
| | | | | | | | | | | | | | | | | after check failed, need release memory reference Bug 200531152 Change-Id: I6bfad867eb9bd636a48b5ceb3a4417a80994a3ec Signed-off-by: Bruce Xu <brucex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2194025 (cherry picked from commit f85504ae46d65d5346d9e2a5cc84ffb960ba9fb7) Reviewed-on: https://git-master.nvidia.com/r/2195437 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix trace ring read after invalid entryDeepak Nibade2019-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_fecs_trace_poll() right now calls gk20a_fecs_trace_ring_read() to read the trace ring buffer written by FECS gk20a_fecs_trace_ring_read() returns number of trace entries written to local buffer if successful, otherwise returns error In case there is really an invalid entry, gk20a_fecs_trace_poll() will just stop reading more entries, write current read pointer to h/w and return When gk20a_fecs_trace_poll() is called next time, we again read that invalid entry, and again skip it, and again return This keeps happening, and we never move on to read new entries Fix this by always continuing to read next entry irrespective of current entry is valid or not gk20a_fecs_trace_poll() now just prints a debug message instead of breaking the loop Bug 200491708 Bug 200542611 Reviewed-on: https://git-master.nvidia.com/r/2020167 (cherry picked from commit decbbf35041e7e551b3f354e582daaa5c8c3cc0a) Change-Id: If8b3c8af63ce662a41ada93a6986fa149e34f664 Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2190151 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix enable/disable fecs traceseshendra2019-09-06
| | | | | | | | | | | | | | | | | | | | | | - This patch fixes enable/disable fecs trace logic. - Added enable_lock and enable_count to handle multiple enable/disable of fecs trace logic. - If user does trace disable twice, enable_count will become negative and when user tries to re-enable it, fecs trace will not be enabled. Bug 2672760 Bug 200542611 Change-Id: Ic7d4883b899f01dcf43058d0e7c9d1223a716c9b Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189371 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enabling/disabling FECS trace supportseshendra2019-09-06
| | | | | | | | | | | | | | | | | | | - To enable FECS trace support, nvgpu should set the MSB of the read pointer (MAILBOX1). - The ucode will check if the feature is enabled/disabled before writing a record into the circular buffer. If the feature is disabled, it will not write the record. - If the feature is enabled and the buffer is not allocated, HW will throw a page fault error. Bug 2459186 Bug 200542611 Change-Id: I6f181643737d1cf1bda02077eaa714a3f4ef3d8c Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: Fix the race between runtime PM and L2 flush"Debarshi Dutta2019-09-05
| | | | | | | | | | | | | | | This patch results in a flaw that doesn't clear the GPU cache. This reverts commit 47f6bc0c2e85d0a8ff943b88c81108ca1bfc588e. Bug 2687410 Change-Id: If78bd7ca29eb5621d4369cbddf21320e2a77a41a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2186886 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct handling of pbdma rcDebarshi Dutta2019-09-04
| | | | | | | | | | | | | | | | | | | | | | | The current code reads the pbdma_status info after clearing the interrupt. Other interrupts/sleep can cause enough delay between clearing the interrupt and pbdma switching the channel leading to invalid channel/tsg ID. Correct that by reading the pbdma_status info register before clearing of the pbdma interrupt to correctly read the context information before the pbdma can switch out the context. Bug 200533450 Change-Id: Ic2f0682526e00d14ad58f0411472f34388183f2b Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2165047 (cherry-picked from 0ef96e4b1a7979d2bae0e52924e976515cb87400 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2188861 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for XPU rail splitDebarshi Dutta2019-09-04
| | | | | | | | | | | | | | | | | | | | | | Check if CPU/GPU rails are joint, disable railgating if they are. Add the DT support for T194 and T186 platforms. Disable railgate_enable sysfs node update in the above condition. Bug 200546450 Bug 200545711 Change-Id: I002488f6418805569b0ef0fc3032b58297adeafb Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2185221 Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: don't report max load when counter overflowLeon Yu2019-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is to prevent GPU (and thus EMC) frequency from being boosted from time to time when system is completely idle. It's caused by max GPU load being incorrectly reported by perfmon. When the issue happens, it can be observed that max load is reported but busy_cycles read from PMU is actually zero. Even though busy and total cycles returned by PMU may not be completely accurate when counter overflows, the counters accumulated so far still have some value that we shouldn't ignore. OTOH, returning max load could be the least accurate approximation in such cases. So let's just clear the interrupt status and let rest of the code handle the exception cases. Bug 200545546 Change-Id: I6882ae265029e881f5417fb2b82005b0112b0fda Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180771 Reviewed-by: Peng Liu <pengliu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mubushir Rahman <mubushirr@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use vpr resize APIVedashree Vidwans2019-08-30
| | | | | | | | | | | | | | | | | | | | This patch adds nvgpu API in linux and qnx to query vpr resize. The new API nvgpu_is_vpr_resize_enabled() is used in nvgpu_submit_channel_gpfifo(). Previously, if non-deterministic channel has timeout disabled and GPU cannot railgate on some platform, then channel doesn't power ref count and results in video freeze. This requires non-determinstic channel job tracking to be enabled if vpr resize is supported or if GPU can railgate. Bug 200532122 Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167082 Reviewed-on: https://git-master.nvidia.com/r/2180581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race for channel sync read/writeVedashree Vidwans2019-08-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTS test dEQP-VK.api.object_management.max_concurrent.device_group crashes with invalid userspace memory access. Currently, nvgpu_submit_prepare_syncs() races with gk20a_channel_clean_up_jobs() and this race condition is exposed when aggressive_sync_destroy_thresh is set to non-zero value. nvgpu_submit_prepare_syncs() gets ref for c->sync to submit job and releases channel sync_lock immediately. Meanwhile, gk20a_channel_worker_process() triggers gk20a_channel_clean_up_jobs(), which destroys ref'd c->sync pointer. Channel sync is deleted by gk20a_channel_clean_up_jobs() only if aggressive_sync_destroy_thresh is non-zero. So, gk20a_channel_clean_up_jobs() and nvgpu_submit_prepare_syncs() will race only in this scenario. Hence, if aggressive_sync_destroy_thresh value is non-zero, this patch protects channel's sync pointer by holding channel sync_lock during complete execution of nvgpu_submit_prepare_syncs(). Bug 2613870 Change-Id: I6f3d48aff361d1cb38c30d2ce5de276d0c55fb6f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180550 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: support usermode submitKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Use usermode_base HAL from gv11b and turn on NVGPU_SUPPORT_USERMODE_SUBMIT for gv100. Bug 200145225 Bug 200541476 Change-Id: I9f60a1fb07ae19ee9e0de9e28d56789fe282907f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1924509 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit a39d91b591d79827fc315218393b03365cc6e502 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170622 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mark usermode submit supported for gv11bKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | Mark usermode submit supported in gv11b and add the characteristics flag to expose the capability to userspace. Bug 200145225 Bug 200541476 Change-Id: Id9dcb0c71c020bd509fbdbffb94a756c69377f20 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795822 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 37659f5c8e0571655178c50a6296b68e3ebdc4cb in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2170604 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support usermode submit buffersKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import userd and gpfifo buffers from userspace if provided via NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token (i.e., the hw channel id) to userspace. To keep the buffers alive, store their dmabuf and attachment/sgt handles in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for buffers that are mainly in kernel use. The buffers are freed via a new API in the os_channel interface. Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the usermode gpfifo buffer. Bug 200145225 Bug 200541476 Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795821 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 99b1c6dcdf328efcfe47338ad1b71a114ab7f272 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170603 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add FOREIGN_SGT mem flagKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Add an internal flag NVGPU_MEM_FLAG_FOREIGN_SGT to specify that the sgt member of an nvgpu_mem must not be freed when the nvgpu_mem is freed. Bug 200145225 Bug 200541476 Change-Id: I044fb91a5f9d148f38fb0cbf63d0cdfd64a070ce Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819801 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 9de6d20abb8fef0cd11c22676846d809ee3f9afc in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170602 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: provide usermode region via mmapKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | Add a mmap callback on the control device node for mapping the usermode register region to userspace. Each such mapping is removed when the GPU railgates, and brought back again on unrailgate. The mapping offset must be 0 and its size must be 4 KB. Bug 200145225 Bug 200541476 Change-Id: Ie8d3758da745b958376292691d7d1d02a24e7815 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795819 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit f33935f426c46b70b7aee33a1e52d5fdae5ca376 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170035 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: track opened Linux ctrl filesKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | An upcoming patch will need to enumerate opened ctrl nodes; track them in a list, protected by a mutex. Bug 200145225 Bug 200541476 Change-Id: I50dc15056832a3bb53fbdd7bd2bffcdaecc7b21c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811840 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit d53495400e15fdef80be2f04a9f2312b81d2bd6d in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170005 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add usermode_base HALKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Add a HAL function pointer to fifo to for reading the usermode_cfg0 register and implement it for gv11b. Bug 200145225 Bug 200541476 Change-Id: I5f77b15d3b502d9370b1f14129314eaf51a9d7d1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811839 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit fddb2969240652e1a56089b249684b55430d45c5 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170004 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: store bus addr of gpu regsKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | Usermode submit needs to access the usermode region of registers from userspace. Store the start address of register resource in struct nvgpu_os_linux to be used in remap to userspace. Bug 200145225 Bug 200541476 Change-Id: I3796b6bf67942af0cc16c86accb82a013032bfc8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811838 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 38c11db264f776fa495a3ba74caadf4262062b78 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2169921 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add CHANNEL_SETUP_BIND IOCTLDebarshi Dutta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | | For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much more than just gpfifo allocation, and its signature does not match support that's needed soon. Add a new one called SETUP_BIND to hopefully cover our future needs and deprecate ALLOC_GPFIFO_EX. Change nvgpu internals to match this new naming as well. Bug 200145225 Bug 200541476 Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1835186 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from e0c8a16c8d474eac6723fea3980833873ab921a6 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2169882 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use TPC_PG_MASK to powergate the TPCDivya Singhatwaria2019-08-02
| | | | | | | | | | | | | | | | | | | | | | | - In GV11B, read fuse_status_opt_tpc_gpc register to read which TPCs are floorswept. - The driver will also read sysfs node: tpc_pg_mask - Based on these two values "can_tpc_powergate" will be set to true or false and mask will be used to write to fuse_ctrl_opt_tpc_gpc register to powergate the TPC. - can_tpc_powergate = true indicates that the mask value sent from userspace is valid and can be used to power gate the desired TPC - can_tpc_powergate = false indicates that the mask value sent from userspace is not valid and cannot be used to power gate the desired TPC. Bug 200532639 Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2159219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix the race between runtime PM and L2 flushDebarshi Dutta2019-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | gk20a_mm_l2_flush flushes the L2 cache when "struct gk20a->power_on" is true. But it doesn't acquire power lock when doing that, which creates a race that runtime PM might suspend the GPU in the middle of L2 flush. The FB flush looks having the same issue with L2 flushing. This patch fixes that by calling pm_runtime_get_if_in_use at the beginning of the ioctl. This API from PM does a compare and add to the usage count. If the device was not in use, it simply returns without incrementing the usage count as its unnecessary to wake up the GPU(using e.g. a call to gk20a_busy()) as the caches are flushed when the device would be resumed anyways. Bug 2643951 Change-Id: I2417f7ca3223c722dcb4d9057d32a7e065b9e574 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2151532 GVS: Gerrit_Virtual_Submit Reviewed-by: Mark Zhang <markz@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add missing ops assignmentDebarshi Dutta2019-08-01
| | | | | | | | | | | | | | | | | | fecs_trace is not enabled in rel-32 for gm20b due to a missing assignment of gops->fecs_trace from gm20b->fecs_trace. This patch corrects this by adding the required line. Bug 2052906 Change-Id: I90c360d170373534270b0125a5905bee512d5316 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2164991 GVS: Gerrit_Virtual_Submit Reviewed-by: Jonathan Mccaffrey <jmccaffrey@nvidia.com> Tested-by: Jonathan Mccaffrey <jmccaffrey@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove reversed ordering for deadlockJeremy Ho2019-07-16
| | | | | | | | | | | | | | | | | | | | | | | In some cases, we would get deadlock issue due to there are two locks acquisition on common clk driver's lock and nvgpu driver's locks. At the bug, inconsistent lock ordering problem will come with one thread gets "nvgpu lock -> clk lock" and the other thread gets "clk lock -> nvgpu lock". Slove the latter path with one-time initializing clk_parent entry and use cached data afterward. Bug 2555115 Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8 Signed-off-by: Jeremy Ho <jeremyh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2146727 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: align size to page size in vgpu mapPeter Daifuku2019-06-25
| | | | | | | | | | | | | | | | | | | | | | Align size to the page size in vgpu_gp10b_locked_gmmu_map before setting up the memory descriptors being passed to the RM server Bug 2212569 Bug 200528973 Change-Id: I7149f3116c2c4c909f77cd791f5954ad8c486073 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1953444 (cherry picked from commit 0babd46eb49d9d1b2f8562cea17a419677619b0e) Reviewed-on: https://git-master.nvidia.com/r/2140963 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Steinle <tsteinle@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set channel to serviceable after it is bound to tsgSeema Khowala2019-06-15
| | | | | | | | | | | | | | | | | Channel's unserviceable status should to set to false only after channel is bound to tsg. Bug 200460037 Change-Id: I24976c673b3b08cc652d2c203b9fc1f3aaed403f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2135923 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: correct param to sysfs_attr_initsumitg2019-06-11
| | | | | | | | | | | | | | | | | | | | | Pass correct attr parameter to sysfs_attr_init(). This fixes the compilation error on enabling debug lock alloc. error: ‘struct device_attribute’ has no member named ‘key’ Bug 200464909 Bug 2604007 Change-Id: Ia0d2672b1c8fe9eb4807b4809892dcdc0cff2669 Signed-off-by: sumitg <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2034954 (cherry picked from commit daa4d7e42b3dcb0dc590b1b3c3356259ee0423d6) Reviewed-on: https://git-master.nvidia.com/r/2132154 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Phoenix Jung <pjung@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add check for "vm->num_user_mapped_buffers"Kary Jin2019-05-31
| | | | | | | | | | | | | | | | | | | | The "nvgpu_big_zalloc()" will be failed if the passed-in argument "vm->num_user_mapped_buffers" is zero. The returned value is 16 which will bypass the NULL-check and then causes the panic. This patch adds a check on the "vm->num_user_mapped_buffers" to avoid the zero is passed-in the "nvgpu_big_zalloc()". Bug 2603292 Change-Id: I399eecf72a288e13992730651a34a6cea1ef56d1 Signed-off-by: Kary Jin <karyj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123499 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add DT support for TPC_PG_POWERGATEDebarshi Dutta2019-05-15
| | | | | | | | | | | | | | | | | | Added support for TPC_PG_POWERGATE during probe for nvgpu via DT. A new DT binding GV11B_FUSE_OPT_TPC_DISABLE is supported by nvgpu driver that checks for valid masks and updates the global tpc_pg_mask flag. Bug 200518434 Change-Id: Ia65ae518b48e36d28de5e9375bc994232f6a9438 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2117783 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fecs ctxsw trace for gm20bDebarshi Dutta2019-05-14
| | | | | | | | | | | | | | | | | | Register gk20a non-arch-specific functions for gm20b gpu_ops.fecs_trace, Register nvgpu_os_linux_ops.fecs_trace.init_debugfs gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed. Bug 2052906 Change-Id: I245c91ae8e6015b87bafeb3ec023b98fe4c57501 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115247 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: cache gpu clk rate"Peng Liu2019-05-10
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit e9a6d179a42e ("gpu: nvgpu: cache gpu clk rate") - Real clock rate doesn't always equal clock rate requested by caller - call of clk_set_rate() and update of cached_rate are not atomic - Real root cause for Bug 2051688 is in bpmp and gboost design Bug 2538692 Change-Id: I9248e0c69e2271ed2d0070587db59afa6f8160f2 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109708 (cherry picked from commit cc70f89bb4efd106b81c2da5ecd6cbeb69c990d8) Reviewed-on: https://git-master.nvidia.com/r/2113647 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix synchronization in nvgpu_vm_mapShih-hsin Li2019-05-09
| | | | | | | | | | | | | | | | | | | | | | The mapping early returned from nvgpu_vm_map might already be unmapped during channel clean up. Increase refcount of an already mapped buffer inside the scope of update_gmmu_lock mutex to avoid this race. Bug 200494150 Change-Id: I66d9272e42c40cd3aae7ba3bb8106ec37691bf8e Signed-off-by: Shih-hsin Li <seasonl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2114163 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect recovery with engines_reset_mutexDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename gr_reset_mutex to engines_reset_mutex and acquire it before initiating recovery. Recovery running in parallel with engine reset is not recommended. On hitting engine reset, h/w drops the ctxsw_status to INVALID in fifo_engine_status register. Also while the engine is held in reset h/w passes busy/idle straight through. fifo_engine_status registers are correct in that there is no context switch outstanding as the CTXSW is aborted when reset is asserted. Use deferred_reset_mutex to protect deferred_reset_pending variable If deferred_reset_pending is true then acquire engines_reset_mutex and call gk20a_fifo_deferred_reset. gk20a_fifo_deferred_reset would also check the value of deferred_reset_pending before initiating reset process Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I47de669a6203e0b2e9a8237ec4e4747339b9837c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2022373 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from cb91bf1e13740023903282d1c2271d9154e940ba in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2024901 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: wait for gr.initialized before changing cg/pgDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | set gr.initialized to false in the beginning of gk20a_gr_reset() and set it to true at the end of successful execution of gk20a_gr_reset. Use gk20a_gr_wait_initialized() to enable/disable cg/pg functions to make sure engine is out of reset and initialized. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: Ic7b0b71382c6d852a625c603dad8609c43b7f20f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from 7e2f124fd12caf37172f12da8de65093622941a5 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2111038 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable elpg before ctxsw_disableDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | if fecs is sent stop_ctxsw method, elpg entry/exit cannot happen and may timeout. It could manifest as different error signatures depending on when stop_ctxsw fecs method gets sent with respect to pmu elpg sequence. It could come as pmu halt or abort or maybe ext error too. If ctxsw failed to disable, do not read engine info and just abort tsg. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I5f3ba07663bcafd3f0083d44c603420b0ccf6945 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2014914 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2018156 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add cg and pg functionDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Change the path in the dependent filesAnuj Gangwar2019-05-03
| | | | | | | | | | | | | | | | | | | | changes in path because we move the nvhost linux user-interface from include/linux/ to include/uapi/linux depends on I2e116dc8f6c33f53c03fb56b923931b6e600b534 Bug 2062672 Change-Id: If2e165852432d5795cf6680cfeb5d4b661fdee74 Signed-off-by: Anuj Gangwar <anujg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1953731 (cherry picked from commit 4e7333967da9cc5a5e4c01288cbc3dd6a25b9fe1) Reviewed-on: https://git-master.nvidia.com/r/2110254 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change err to info print if failing eng id is -1Seema Khowala2019-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For handle_sched_error, change err to info print for failing eng id returned as -1 i.e. FIFO_INVAL_ENGINE_ID as no engine is found busy doing ctxsw. May be ctxsw already finished for the context for which ctxsw timeout intr was triggered. Possible Causes: a) On hitting engine reset, h/w drops the ctxsw_status to INVALID in fifo_engine_status register. Also while the engine is held in reset h/w passes busy/idle straight through. fifo_engine_status registers are correct in that there is no context switch outstanding as the CTXSW is aborted when reset is asserted. This is just a side effect of how gv100 and earlier versions of ctxsw_timeout behave. With gv10b and later, h/w snaps the context at the point of error so that s/w can see the tsg_id which caused the HW timeout. b) If engines are not busy and ctxsw state is valid then intr occurred in the past and if the ctxsw state has moved on to VALID from LOAD or SAVE, it means that whatever timed out eventually finished anyways. The problem with this is that s/w cannot conclude which context caused the problem as maybe more switches occurred before intr is handled. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: Ia79bee6e860fb179ee39024c963671d4f8245227 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2030866 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from d27f875d2c7839d3b1ec7db80d83594509ff2ea8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2076126 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not do timeout_debug_dump for non fifo_error_idle_timeoutSeema Khowala2019-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | Any recovery that goes through gk20a_fifo_recover path e.g. gr error, mmu fault or any recovery that involves engine recovery as well, will still dump the full debug dump. This change will just avoid dumping debug dump for force reset channels and pbdma intr if they do not involve engine recovery. For FIFO_ERROR_IDLE_TIMEOUT error notifiers that involves tsg recovery only, debug_dump will happen only if timeout_debug_dump is set. timeout_debug_dump by default is set to true but can be changed using NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX. Bug 2092051 Change-Id: Ibbf3cd2c44c586d9deb9e61ffbf37945b8d9e428 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2033068 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 5222d0ff4f8d31b02267eb8926b5d00835f39508 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2076117 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add hal to mask/unmask intr during teardownSeema Khowala2019-05-02
| | | | | | | | | | | | | | | | | | | | | | ctxsw timeout error prevents recovery as it can get triggered periodically. Disable ctxsw timeout interrupt to allow recovery. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I47470e13968d8b26cdaf519b62fd510bc7ea05d9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2019645 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 68c13e2f0447118d7391807c9b9269749d09a4ec in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2024899 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: add missing tsg_mark_errorSeema Khowala2019-04-16
| | | | | | | | | | | | | | | | | | | | | | nvgpu_tsg_mark_error is missing in teardown path for aborting tsg. Without this, channels corresponding to tsg being aborted will not be set to timedout (unserviceable) and also notifier_wq and semaphore_wq will not be woken up. Bug 2092051 Bug 2429295 Bug 2484211 Change-Id: Ie71c9a3b7a7fd1aa8cb9ec5d0dc30ccaeadfeae5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1999026 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 7fed0c19379139081162536ead3682ab747775db in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2086594 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: using pmu counters for load estimatePeng Liu2019-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix invalid TSG pointerDeepak Nibade2019-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | In gr_gp10b_set_cilp_preempt_pending() we already extract TSG pointer by calling tsg_gk20a_from_ch() which safely returns correct TSG or NULL in error case But before calling g->ops.fifo.post_event_id() we again extract TSG by directly accessing g->fifo.tsg array, and this could result in getting invalid TSG pointer Fix this by removing direct TSG extraction through g->fifo.tsg Bug 2444819 Jira NVGPU-1601 Change-Id: I9d49b5309c74e162828e7cb7d97556aae939a07c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1984954 (cherry picked from commit dcd3778b5ea4e01ab1e5d2dab2b087b8da67b21e) Reviewed-on: https://git-master.nvidia.com/r/2077313 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix channel reference leak in error caseDeepak Nibade2019-04-01
| | | | | | | | | | | | | | | | | | | In gr_gp10b_get_cilp_preempt_pending_chid(), we leak the channel reference if tsg_gk20a_from_ch() returns NULL Fix this by calling gk20a_channel_put() in error case Bug 2444819 Jira NVGPU-1601 Change-Id: Ic5d036c6d043b0b95dd2a564afcc0add67c1ca02 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1984953 (cherry picked from commit 2322cb131c3478c1a7e3d8b29810f1c7001d4c44) Reviewed-on: https://git-master.nvidia.com/r/2077312 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: tsg: ensure unbound channel is disabledPeter Daifuku2019-03-29
| | | | | | | | | | | | | | | | | | | Multiple threads could be unbinding different channels from the same tsg at the same time. At the point where we remove the channel from the tsg's channel list, call disable_channel again, in case another thread had re-enabled the channel after we had disabled it. Bug 200404549 Change-Id: I9abbc08dc11fe1f7a0abada88376c0ef96b56610 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083337 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove gk20a_is_channel_marked_as_tsgSeema Khowala2019-03-18
| | | | | | | | | | | | | | | | | | | | | Use tsg_gk20a_from_ch to get tsg pointer for tsgid of a channel. For invalid tsgid, tsg pointer will be NULL Bug 2092051 Bug 2429295 Bug 2484211 Change-Id: I82cd6a2dc5fab4acb147202af667ca97a2842a73 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2006722 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 13f37f9c70b9ae2e0d179830cded93a0a6f86494 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2025507 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: typedefs page_table and dma_mapping.Preetham Chandru R2019-03-13
| | | | | | | | | | | | | | | | | typedef nvidia_p2p_page_table to nvidia_p2p_page_table_t and typedef nvidia_p2p_dma_mapping to nvidia_p2p_dma_mapping_t. Bug 200438879 Change-Id: I1278c4022990fdedb668e7b20ae35631d2da6089 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2033843 (cherry picked from commit ad351f17be2ce1aa7c5146e6022d02f3bc2de600) Reviewed-on: https://git-master.nvidia.com/r/2071428 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add compatibility versionPreetham Chandru R2019-03-13
| | | | | | | | | | | | | | | | | Add compatibility version to page table and dma mapping structure. Bug 200438879 Change-Id: I04b4601f71ae2b3e75843f39f5445ecca2b16677 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029086 (cherry picked from commit 8bbbd09caa06f7c0f17a48e129d4fd07ce6fa9be) Reviewed-on: https://git-master.nvidia.com/r/2071427 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: more changes to clean loading/unloadingDmitry Pervushin2019-03-11
| | | | | | | | | | | | | | Bug 200487652 Change-Id: Ib52cc6a85a19ea0396c8ab584c5ce9970f93085a Signed-off-by: Dmitry Pervushin <dpervushin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2020386 (cherry picked from commit 617dff478c3687a08ed5b77f4ac2073b290c57ea) Reviewed-on: https://git-master.nvidia.com/r/2035720 GVS: Gerrit_Virtual_Submit Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 21:34:05 -0500