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* gpu: nvgpu: make gv11b fifo function staticSourab Gupta2018-01-08
| | | | | | | | | | | | The patch makes 'gv11b_fifo_get_eng_method_buffer_size' function as static since it is being used only in this file. Otherwise, QNX throws compilation error. Change-Id: I96feaad8e77d11eabc78843d7dc29f749b55edab Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626399 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace usleep_range with nvgpu_usleep_rangeSourab Gupta2018-01-08
| | | | | | | | | | | The patch replaces the linux specific usleep_range usage with nvgpu_usleep_range OS agnostic function, in fifo_gv11b.c Change-Id: I8ada3ffc1b70caa571cbabe5c3973f37e819538b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626398 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove dma-buf.h include in channelSourab Gupta2018-01-08
| | | | | | | | | | | | | | The patch removes the dma-buf.h include from channel_gk20a.c, now that there are no references to dma_buf present here. Change-Id: I079c3c3763e7ac4f91e43a4bc54a23ec8d5a23fa Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626396 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* DNI: gpu: nvgpu: Increase GV100 ctxsw timeoutsDavid Nieto2018-01-05
| | | | | | | | | | | | | | | During bringup and before nvlink is up GV100 on the DDPX platform operates with a very, very slow sysmem link. In order to get sysmem test to pass it is neccesary to significantly increase most timeouts by an order the magnitude. Bug 2040544 Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627417 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix L2 ROP maskDavid Nieto2018-01-05
| | | | | | | | | | | | | | | | | L2 mask was assuming FS units contain valid information, but they do not. The new code checks if the L2 is FS before reading the L2/ROP mask Bug 2040328 Change-Id: Id07cc630e65cfc71ab8084a3700d884b6cd3430f Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627327 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: no hv support for write_sm_error_statePeter Daifuku2018-01-04
| | | | | | | | | | | | | | | | | There is no current need for a virtualized version of nvgpu_dbg_gpu_ioctl_write_single_sm_error_state, so return -ENOSYS when virtual. Bug 200331110 Change-Id: I223a6298eb4c891859f1c8252049f9a83d84ccb5 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631270 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not disable ELPG when committing buffersTerje Bergstrom2018-01-04
| | | | | | | | | | | | | Committing buffer addresses only writes to the memory. There's no need to disable ELPG for the duration, so drop the ELPG protection. Change-Id: I8d8d08506387197e4737e0311df4a20085496056 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631149 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a specific optimizationTerje Bergstrom2018-01-04
| | | | | | | | | | | Remove compute optimization specific to gk20a. We do not support gk20a anymore. Change-Id: Ibd548eee8d891a667f28a451d586fcfaac7f026a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631144 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix erroneous gk20a_put() callDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | With a recent rework we moved gk20a_get() call to nvgpu_ioctl_tsg_open(), but corresponding gk20a_put() call remained in gk20a_tsg_release() So if a TSG is opened and released from within kernel with APIs gk20a_tsg_open()/gk20a_tsg_release() we mistakenly drop extra refcount through gk20a_put() Fix this by moving gk20a_put() call to nvgpu_ioctl_tsg_release() which balances gk20a_get() call in nvgpu_ioctl_tsg_open() Bug 200374011 Change-Id: Id0cec0426e6231309dc530ab5c934dacaba9f8da Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630969 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: return error code in failure casesDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | In gk20a_ce_create_context(), if gk20a_tsg_open() or gk20a_open_new_channel() fails, we bail out from the function without setting the error code This could mislead the caller and report incorrect success Fix this by setting error code explicitly in failure cases Bug 200374011 Change-Id: Idf6cba4a57740107bada698295745352f7b5d5ac Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631506 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix TSG leak from CE codeDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | In gk20a_ce_delete_gpu_context(), we unbind the channel from TSG and close the channel. But we do not drop the TSG refcount leaking the TSG reference Fix this by explicitly dropping TSG refcount Also, do not explicitly unbind the channel from TSG gk20a_channel_close() will internally unbind the channel from TSG Bug 200374011 Change-Id: Ie4aa32f1d0bff4231f41aa2b33743cdc63e967c7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1629972 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: return error if TSG allocation failsDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | In gk20a_cde_load(), if TSG allocation fails we bail out the function without setting the error code and caller of this functions assumes CDE load is successful Fix this by setting explicit error code if TSG allocation fails Bug 200374011 Change-Id: I6e7bcb325fb0062605fa2f696da4abdeb34e241a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix TSG leak from CDE codeDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | | In gk20a_cde_remove_ctx(), we unbind the channel from TSG and close the channel. But we do not drop the TSG refcount leaking the TSG reference After allocating sufficient contexts, we see TSG creation fails as below nvgpu: 17000000.gp10b: gk20a_cde_load:1286 [ERR] cde: could not create TSG Fix this by explicitly dropping TSG refcount Also, do not explicitly unbind the channel from TSG gk20a_channel_close() will internally unbind the channel from TSG Bug 200374011 Change-Id: If6d75b20d5e03d710c0597d7a320d1157206a2a5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627116 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add golden_img_loaded flag to gr ctx descSourab Gupta2018-01-04
| | | | | | | | | | | | | | | The patch adds the boolean flag 'golden_img_loaded' to gr ctx desc. This is needed for refactoring the ctx initialization. Change-Id: I6d6df273e764a4cd06d062d59427dd33f4669778 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617174 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set low_hole to 64K for bar1 vmSourab Gupta2018-01-04
| | | | | | | | | | | | | The patch sets low_hole value to 64K for bar1 vm to align to potential 64KB native page size. JIRA NVGPU-454 Change-Id: I994dfd6824d3a2e8a09433798bb101af88ecb5ca Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617173 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add guest_managed field in vm_gk20aSourab Gupta2018-01-04
| | | | | | | | | | | | | | | | | | | Add a field in vm_gk20a to identify guest managed VM, with the corresponding checks to ensure that there's no kernel section for guest managed VMs. Also make the __nvgpu_vm_init function available globally, so that the vm can be allocated elsewhere, requisite fields set, and passed to the function to initialize the vm. Change-Id: Iad841d1b8ff9c894fe9d350dc43d74247e9c5512 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617171 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enable secure alloc for GV11bSami Kiminki2018-01-03
| | | | | | | | | | | | | | | Kernel needs to be able to allocate VPR memory for buffers for protected contexts. So, let's call gk20a_tegra_init_secure_alloc and enable VPR for GV11B. Bug 2039456 Bug 2040513 Change-Id: Ie27d8f04b1a414c36b42516ce3147d38d8472d54 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove bare channel schedulingTerje Bergstrom2018-01-02
| | | | | | | | | | | | | | | | Remove scheduling IOCTL implementations for bare channels. Also removes code that constructs bare channels in runlist. Bug 1842197 Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627326 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove TSG required flagTerje Bergstrom2018-01-02
| | | | | | | | | | | | | | | | | | Remove nvgpu internal flag indicating that TSGs are required. We now require TSGs always. This also fixes a regression where CE channels were back to using bare channels on gp106. Bug 1842197 Change-Id: Id359e5a455fb324278636bb8994b583936490ffd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628481 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add io coherency supportAparna Das2017-12-30
| | | | | | | | | | | | | Modify command message parameter to support io coherency. Jira EVLR-2025 Change-Id: I38b21c72d85f559555c4d97dab73d0f715ecc655 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614388 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize CE once channels resumedTerje Bergstrom2017-12-29
| | | | | | | | | | | | | | Initialize CE channels and vidmem clearer only once channels have been enabled. Change-Id: Id4c870ee7d4632044b97cead5d0d7b8317170430 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628167 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Wait for ECC scrubbing on all TPCsTerje Bergstrom2017-12-29
| | | | | | | | | | | | | | | | | We send a broadcast request to invoke scrubbing on all TPCs, but we check only TPC0 for scrubbing to finish. This likely produces correct results, because each TPC should take exactly the same number of cycles for scrubbing, but it's not certain. Change the polling loop to check all TPCs to make sure there are no timing glitches. Change-Id: Id3add77069743890379099a44aec8994f59d9a5e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1625349 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement abstraction for finding TIDTerje Bergstrom2017-12-28
| | | | | | | | | | | | | Implement abstraction for finding the thread ID of thread currently being run. This is tracked for context switch tracing. In Linux kernel this is implemented by returning PID. Change-Id: Id46a318894f9a2ff3c85d2c8ef0b02c52783f122 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627239 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable speed change in GV100David Nieto2017-12-28
| | | | | | | | | | | | | | | Disable for now as speed change needs to be adapted to support GV100+Xavier configuration Bug 2040925 Change-Id: Ibce0811879aa2d2b8335e30d7fdb77fb933bc696 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624259 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for GV100 SKU 250David Nieto2017-12-28
| | | | | | | | | | | | Bug 2040925 Change-Id: Ied06b199fd87411847b9987496c56276f8ebf89c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1623709 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Report LTC errors per sliceDavid Nieto2017-12-28
| | | | | | | | | | | | | | | | | | | | | Add support to report ltc ecc errors per slice (1) use new logic to detect subunits (2) store size of array and check before comparison to prevent out of bounds derefencing (3) use new hashing to prevent collisions or entries with permuted names bug 2037425 Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620854 GVS: Gerrit_Virtual_Submit Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for channel eventsTerje Bergstrom2017-12-28
| | | | | | | | | | | | | | Remove support for events for bare channels. All users have already moved to TSGs and TSG events. Bug 1842197 Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1618906 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for bare channelsTerje Bergstrom2017-12-28
| | | | | | | | | | | | | | | Remove remaining support for bare channels. All users of bare channels have already moved to TSGs. Bug 1842197 Change-Id: I1ff12677253b160dac9bebe6925ad0839ea07cfc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1618905 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix crash on read fail of mc_boot_0_rSupriya2017-12-28
| | | | | | | | | | | | | | | | | | | | | This CL handles - erroneous use of boot_0 function pointer before being assigned in __nvgpu_check_gpu_state - And proper handling of error returned from gk20a_readl in gk20a_mc_boot_0 With these fixes crash is not seen in case mc_boot_0 read returns 0 in gk20a_mc_boot_0 - And also this handles the recursion caused by mc.boot_0() calling nvgpu_readl and nvgpu_readl in turn calling mc.boot_0 in case of read failure Bug 2010966 Change-Id: Ia087811c67d88948b7fc5fff35e0fabc6ea91989 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement abstraction for finding TGIDTerje Bergstrom2017-12-27
| | | | | | | | | | | | | | | Implement abstraction for finding the process ID of thread currently being run. This is tracked for context switch tracing. In Linux kernel this is implemented by returning TGID. Change-Id: Ia6bcbd92c8cc25467694a35476e5d5f717194105 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615985 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.dgoyal@nvidia.com2017-12-27
| | | | | | | | | | | | | | | | | | - Enabled ECC interrupt to host. - Fix to ignore IDLE_SNAP during ELPG_ENTRY. - Production signatures. Change-Id: Ie9e549a123b3fbdcde69fa1d4d2ea3ac20e3fa64 Signed-off-by: y <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: scrub more fileds for sm l1 tagseshendra Gadagottu2017-12-27
| | | | | | | | | | | | | | | | | | | | | SM L1 tag needs to scrub for following additional fields: sm_l1_tag_ecc_control_scrub_pixprf sm_l1_tag_ecc_control_scrub_miss_fifo With this SM L1 TAG DBE errors after railgate/ungate are fixed. Bug 2039629 Change-Id: I10ce1d1dd28102f4c2f3fe2fe81801db67b76a21 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626748 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do channel resume after hw initseshendra Gadagottu2017-12-26
| | | | | | | | | | | | | | | | | | | | During finalize power on, resume channels only after complete hw initialization is done. Otherwise it will cause issues with unexpected usage of hw. During first boot will not see these issues because there will no channels. But after rail gate/ungate or suspend/resume these issues can be seen if channels are present before rail-gate/suspend. Bug 2039195 Change-Id: Ie96e2f2b91902ba18b37e9a167344eeae07ba8c2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1625506 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove cde supportSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624087 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: host1x probed only if syncpoints supportedSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I645f272f8fc3fffda95a82716558c081e323aed0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624097 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use hard coded tpc count maskDeepak Nibade2017-12-22
| | | | | | | | | | | | | | | | | | | | | | | In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on number of TPCs But since we could change number of TPCs runtime, we would end up calulating incorrect tpc_count_mask Hence instead of calculating tpc_count_mask, just hard code it to width of fuse register i.e. hard code tpc_count_mask to 4-bit value Bug 2031635 Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617917 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix non-IOMMU mappingsDeepak Nibade2017-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | In __nvgpu_gmmu_do_update_page_table(), and in case of non-IOMMU mappings, we call nvgpu_sgt_get_phys() to get physical address But this API ignores mapping attributes including l3_alloc attribute specified by user space, and this breaks L3 cache allocations Fix this by using g->ops.mm.gpu_phys_addr() which also considers the mapping attributes and returns appropriate physical address Jira GPUT19X-10 Bug 200279508 Change-Id: Ibc0d29f7cb576a9d6893a97b1912d9ff4bc78e02 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1621245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: convert tpc id to non-PES-awareseshendra Gadagottu2017-12-18
| | | | | | | | | | | | | | | Convert tpc number from pes-aware to non-pes-aware number. tpc id is converted to one that is numbered in order starting from the active tpcs within PES0 followed by the active tpcs in subsequent PESs. Bug 1842197 Change-Id: I18d4b20ee4998e5a2ca5439793fe2479b4326c1a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615419 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Skip disabling vdc_4to2Terje Bergstrom2017-12-17
| | | | | | | | | | | | | | | | | | | | gr_gv11b_init_fs_state() calls gr_gm20b_init_fs_state() which disables vdc_4to2. This should no longer be done on gv11b, so instead of calling gr_gm20b_init_fs_state() copy the relevant lines to gr_gv11b_init_fs_state() and drop vdc_4to2 disable. gv11b_ltc_init_fs_state() also disables it to match the state. Remove that disable, too. Change-Id: I3a3fd87a3e8836e495cb818570c971b3d29a6dd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1619966 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gv11b: update thermal settingsseshendra Gadagottu2017-12-14
| | | | | | | | | | | | | | | For gv11b, update thermal settings as per hw POR: 1.Created gv11b specific HAL for init_therm_setup_hw 2.Update steps for gradual slowdown to 1x,1.5x,2x,4x,8x,16x,32x. 3.Modified gradual step duration cycles to 4. Bug 200365110 Change-Id: I93c28a3394857aacdf3d304103c9e7c25d4ad344 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616600 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: allow disabling of ctxsw tracingThomas Fleury2017-12-14
| | | | | | | | | | | | | | | | | | | Fixed build failure that occurred when disabling FECS ctxsw tracing using CONFIG_GK20A_CTXSW_TRACE. JIRA EVLR-2162 Change-Id: I751eba835c5f3f527571167e8b05fadb9687c64d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Dennis Kou <dkou@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Require TSGs for CE alwaysTerje Bergstrom2017-12-14
| | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CE channels to TSGs. Bug 1842197 Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616693
* gpu: nvgpu: gv11b: implement ecc scrubberDeepak Goyal2017-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | Check the availability of ecc units by checking relevant ecc fuse and fuse overrides. During gpu boot, initialize ecc units by scrubbing individual ecc units available. ECC initialization should be done before gr initialization. Following ecc units are scrubbed: SM LRF SM L1 DATA SM L1 TAG SM CBU SM ICACHE Bug 200339497 Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612734 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: get syncpt aperture only if host1x is presentSeema Khowala2017-12-14
| | | | | | | | | | | | | nvgpu_get_nvhost_dev will not return error if host1x field within gv11b device tree is not present. It will just set has_syncpoints in gk20a struct to false. syncpt_unit_interface* should be called only if g->has_syncpoints is set to true. Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615973 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use TSG for CDE channelsTerje Bergstrom2017-12-13
| | | | | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CDE channels to TSGs. Bug 1842197 Change-Id: I20b68c81b47e0d742e5922e7b85ac5cba75984b0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616698 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disallow use of bare channelsTerje Bergstrom2017-12-12
| | | | | | | | | | | | | All channels need to now be wrapped in TSGs. Disallow use of bare channels by preventing creation of GPFIFO for them. Bug 1842197 Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove PMU setup in gv11b halRichard Zhao2017-12-11
| | | | | | | | | | | | | | | | | vgpu doesn't care about pmu. pmu is managed by RM server. It also fixed the dump caused by reading fuse register. Jira EVLR-1934 Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612774 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: PMU parity HWW ECC supportDavid Nieto2017-12-11
| | | | | | | | | | | | | | | Adding support for ISR handling of ECC parity errors for PMU unit and setting the initial IRQDST mask to deliver ECC interrupts to host in the non-stall PMU irq path JIRA: GPUT19X-83 Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef Signed-off-by: David Nieto <dmartineznie@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611625 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use device_is_iommuable() only for iGPUTerje Bergstrom2017-12-11
| | | | | | | | | | | | | | device_is_iommuable() is defined only in Tegra kernel. There is no explicit config option to check for its existance, so skip building that code when Tegra iGPU is not supported. Change-Id: I50dc47070fa416181d458beabf5a2f2373931331 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612649 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_vzalloc() instead of vzalloc()Terje Bergstrom2017-12-11
| | | | | | | | | | | | | | debug_fifo.c uses vzalloc(), but frees the allocation with nvgpu_vfree(). Change the vzalloc() into nvgpu_vzalloc() for consistency. Change-Id: I86facf81752def3dd10fd0cf4cd30e652099f8a5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612647 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:05:50 -0500