| Commit message (Collapse) | Author | Age |
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Compbit backing store did not take into account number of GOBS
per comptagline per slice.
Bug 1604102
Change-Id: I42666e72ea54697b6fbc7318e65a6a09d867f5b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/754706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
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This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85
since the issue seen with bug 200106514 is fixed with change
http://git-master/r/#/c/752080/.
Bug 200112195
Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/752504
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Kick channel off PBDMA before writing new sync point id to allowed
sync points.
Bug 1648297
Bug 1646477
Change-Id: I7c686d474c403fdd54bc64cff63b7d049feecb4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/750981
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Expose CILP and GFXP flags to user space ioctl
NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX.
Bug 200111328
Change-Id: I10931db2babd3222e308fd491824d95204355ff3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/748932
GVS: Gerrit_Virtual_Submit
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Change-Id: Ic71ff2408bd01a1bf5cf1354453a2fe715438cf0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/751555
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Change for new VA space allocator is being reverted with
http://git-master/r/#/c/749291/ but only for Kernel3.18
In Kernel3.10, we support the new VA allocator
Since we support both the kernel versions as of now,
use a KERNEL_VERSION based mechanism to select
appropriate call
Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10
where we want to use new allocator
Bug 200106514
Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/751353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enable re-playable faults based on characteristics
flags passed in channel_setup_ramfc.
Bug 1645628
Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/743382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The produced wrappers for HW PM registers access which are required for
cyclestats support for snapshot buffers mapping.
See commit 589e7a9ffe2a5a70f8803a88fcf8429f553e2fba for tools:nvhost
generators update.
Bug 1573150
Bug 1517458
Change-Id: I9c9332a55f2282c0c626bc8ddbcfdce1289f778b
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/747717
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ZBC is safe to update and GPU is safe to rail gate when units are
in preempted or empty state. Idle may never be reached in case of
graphics preemption, so relax the ZBC update wait condition.
Bug 1640378
Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745655
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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We were dropping the part of address that span word bounary. The register
generator does not know how to real with multi-word fields, to edit things
in manually.
Bug 1646531
Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/747468
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This reverts commit 30e5947fa1f26ed6bb4f137fd76c8869e91b9829.
The original commit was actually fine.
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: I0454415981d29ed0b877f7a21db6f54bc4c30470
Reviewed-on: http://git-master/r/743302
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 3a4f0285c7e9212b394b2c1b151987a7084de927.
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I886e434ce98e85f99b0a77749179e31c0bd00620
Reviewed-on: http://git-master/r/741468
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
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The comptag allocator is made in the chip-specific init code
for the comptags. Thus, a t18x change needs to be made to make
sure the new allocator code compiles and works on t18x.
Change-Id: I57a34f3c61ebd31f875caa577378e829812f2d4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/721171
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bug 200080684
Change-Id: I5888939017877a50b9bd596393ee8ad1547c18e5
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/732535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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VPR allocator needs to be used when allocating graphics context for
VPR channels. Define it for gp10b.
Bug 1625090
Change-Id: Ie2e3a865c310c34c629627891ac0b579f299983f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737846
Reviewed-by: Automatic_Commit_Validation_User
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Used 128k comptag spacing, when 64k is the correct one.
Bug 1525976
Change-Id: Ie2f926929fa89cf715b86a57ffbf4dd1e4920473
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737947
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Enable new page table format for all platforms.
Bug 1525976
Change-Id: I9a3cfabdef7dc6ec33e18a8a4f32063c40f680fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737364
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Fix caching attribute on 5-level page tables.
Bug 1525976
Change-Id: I5c5bf336d87c642f42a387206a55a889e6e07ba6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737923
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Calculate GFXP attrib cb buffer size from the global buffer size.
Bug 1628352
Change-Id: If4edfbf5700334b791dbf8e5cf38fd0208ee7fa1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/735717
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If betacb size has been given via debugfs, use that instead of the
calculated number.
Bug 1628352
Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733332
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Change-Id: I05b2554588e5e1001cdbb54551cf8a064ea531bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/711303
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: I222bebd958e29b3a95d161f05a3052389200fc10
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/736663
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Change-Id: I1fcc7e93d3e31bfbb5d540b43b655566f6dc13cd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/732010
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Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/731494
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Augment new page mapping code to be aware of scattered
buffers.
Bug 1605769
Change-Id: Ifdb326563d28ccf07fc4d3d76a24492a68493fe3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/734355
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- Added final elpg sequencing value
- by default elpg is disabled.
Bug 1525971
Change-Id: I2c306d9f03e361560a95fcfa723eafe14d004191
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732574
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- set "privsecurity" to 1 to enable secure boot else
set to 0.
Bug 200085428
Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/729101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-method gm20b_pmu_init_acr() used for gp10b
acr init wpr region
Bug 200085428
Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732213
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement the 5-level Pascal page table format. It is enabled
only for simulation.
Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/682114
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Add a missing bitmask for clearing existing bits before setting a new
value, and shift the value the correct amount. Also format register
needs to be rounded down.
Bug 200087330
Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/726265
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Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Remove the requirement that srcdir is called kernel.
Change-Id: I9379ef530ac34009bd0461a29d65d6d707bc8014
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/728153
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gp10b can compress 4k pages.
Bug 1605769
Change-Id: I15cf4b9ead0fefdfc430cfc4919dcb16721f5cb2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725794
GVS: Gerrit_Virtual_Submit
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Program steady state CB size to be the HW default.
Bug 1626065
Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725106
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Program a constant stream id 31 to LTC.
Bug 1610019
Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/724348
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: Id1954b6e96dbc75ab217a4b36a11a0457f9ceef1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/722845
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Add platform specific gp10b_mm_iova_addr() to get
iova/phys address for gp10b
If SMMU is not enabled and IO coherence flag is set,
set 34th bit in the physical address and return the
physical address
If SMMU is enabled, return the iova address
Bug 1605653
Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713106
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add below flag for struct nvgpu_as_map_buffer_ex_args
to specify IO coherence
NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT
Bug 1605653
Change-Id: Id5c8195c37c48cff7ec013c6b4b4d9168d972b8e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713104
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Do not clear compbit store size if max size is zero. It's already
zero at this point.
Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/720599
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Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.
Change-Id: I56e73204e288331165358fc9856390f1eb724488
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/715196
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add accessor for NV_PGRAPH_EXCEPTION_MEMFMT
Bug 200078514
Change-Id: Ibf4ce91dfac12d7f6cffb7c65873696e080ff1a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/714167
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/712836
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Offset for preemption pointer was calculated incorrectly.
Bug 1617214
Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/716528
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Use gp10b version of get_physical_addr_bits.
Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/714402
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Add below exception registers to GR dump :
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN
Bug 200078514
Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/712481
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed incorrectly encoded pointer and size.
bug 1525327
bug 1581799
Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/713209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for replayable fault buffer and enable it.
Bug 1587836
Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/661668
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for enabling replayable faults during
channel instance block binding. Also fixed register
programing sequence for setting channel pbdma timeout.
Bug 1587825
Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/681703
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for gp10b specific mm hw init.
Bug 1587825
Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/681787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update fb header with new mmu invalidate fields.
Bug 1587836
Change-Id: I33a30dc742f35d325c528a9bc73fea8cfc21e856
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/680800
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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