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* gpu: nvgpu: gv11b: scrub more fileds for sm l1 tagseshendra Gadagottu2017-12-27
| | | | | | | | | | | | | | | | | | | | | SM L1 tag needs to scrub for following additional fields: sm_l1_tag_ecc_control_scrub_pixprf sm_l1_tag_ecc_control_scrub_miss_fifo With this SM L1 TAG DBE errors after railgate/ungate are fixed. Bug 2039629 Change-Id: I10ce1d1dd28102f4c2f3fe2fe81801db67b76a21 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626748 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do channel resume after hw initseshendra Gadagottu2017-12-26
| | | | | | | | | | | | | | | | | | | | During finalize power on, resume channels only after complete hw initialization is done. Otherwise it will cause issues with unexpected usage of hw. During first boot will not see these issues because there will no channels. But after rail gate/ungate or suspend/resume these issues can be seen if channels are present before rail-gate/suspend. Bug 2039195 Change-Id: Ie96e2f2b91902ba18b37e9a167344eeae07ba8c2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1625506 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove cde supportSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624087 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: host1x probed only if syncpoints supportedSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I645f272f8fc3fffda95a82716558c081e323aed0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624097 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use hard coded tpc count maskDeepak Nibade2017-12-22
| | | | | | | | | | | | | | | | | | | | | | | In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on number of TPCs But since we could change number of TPCs runtime, we would end up calulating incorrect tpc_count_mask Hence instead of calculating tpc_count_mask, just hard code it to width of fuse register i.e. hard code tpc_count_mask to 4-bit value Bug 2031635 Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617917 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix non-IOMMU mappingsDeepak Nibade2017-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | In __nvgpu_gmmu_do_update_page_table(), and in case of non-IOMMU mappings, we call nvgpu_sgt_get_phys() to get physical address But this API ignores mapping attributes including l3_alloc attribute specified by user space, and this breaks L3 cache allocations Fix this by using g->ops.mm.gpu_phys_addr() which also considers the mapping attributes and returns appropriate physical address Jira GPUT19X-10 Bug 200279508 Change-Id: Ibc0d29f7cb576a9d6893a97b1912d9ff4bc78e02 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1621245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: convert tpc id to non-PES-awareseshendra Gadagottu2017-12-18
| | | | | | | | | | | | | | | Convert tpc number from pes-aware to non-pes-aware number. tpc id is converted to one that is numbered in order starting from the active tpcs within PES0 followed by the active tpcs in subsequent PESs. Bug 1842197 Change-Id: I18d4b20ee4998e5a2ca5439793fe2479b4326c1a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615419 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Skip disabling vdc_4to2Terje Bergstrom2017-12-17
| | | | | | | | | | | | | | | | | | | | gr_gv11b_init_fs_state() calls gr_gm20b_init_fs_state() which disables vdc_4to2. This should no longer be done on gv11b, so instead of calling gr_gm20b_init_fs_state() copy the relevant lines to gr_gv11b_init_fs_state() and drop vdc_4to2 disable. gv11b_ltc_init_fs_state() also disables it to match the state. Remove that disable, too. Change-Id: I3a3fd87a3e8836e495cb818570c971b3d29a6dd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1619966 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gv11b: update thermal settingsseshendra Gadagottu2017-12-14
| | | | | | | | | | | | | | | For gv11b, update thermal settings as per hw POR: 1.Created gv11b specific HAL for init_therm_setup_hw 2.Update steps for gradual slowdown to 1x,1.5x,2x,4x,8x,16x,32x. 3.Modified gradual step duration cycles to 4. Bug 200365110 Change-Id: I93c28a3394857aacdf3d304103c9e7c25d4ad344 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616600 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: allow disabling of ctxsw tracingThomas Fleury2017-12-14
| | | | | | | | | | | | | | | | | | | Fixed build failure that occurred when disabling FECS ctxsw tracing using CONFIG_GK20A_CTXSW_TRACE. JIRA EVLR-2162 Change-Id: I751eba835c5f3f527571167e8b05fadb9687c64d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Dennis Kou <dkou@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Require TSGs for CE alwaysTerje Bergstrom2017-12-14
| | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CE channels to TSGs. Bug 1842197 Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616693
* gpu: nvgpu: gv11b: implement ecc scrubberDeepak Goyal2017-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | Check the availability of ecc units by checking relevant ecc fuse and fuse overrides. During gpu boot, initialize ecc units by scrubbing individual ecc units available. ECC initialization should be done before gr initialization. Following ecc units are scrubbed: SM LRF SM L1 DATA SM L1 TAG SM CBU SM ICACHE Bug 200339497 Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612734 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: get syncpt aperture only if host1x is presentSeema Khowala2017-12-14
| | | | | | | | | | | | | nvgpu_get_nvhost_dev will not return error if host1x field within gv11b device tree is not present. It will just set has_syncpoints in gk20a struct to false. syncpt_unit_interface* should be called only if g->has_syncpoints is set to true. Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615973 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use TSG for CDE channelsTerje Bergstrom2017-12-13
| | | | | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CDE channels to TSGs. Bug 1842197 Change-Id: I20b68c81b47e0d742e5922e7b85ac5cba75984b0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616698 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disallow use of bare channelsTerje Bergstrom2017-12-12
| | | | | | | | | | | | | All channels need to now be wrapped in TSGs. Disallow use of bare channels by preventing creation of GPFIFO for them. Bug 1842197 Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove PMU setup in gv11b halRichard Zhao2017-12-11
| | | | | | | | | | | | | | | | | vgpu doesn't care about pmu. pmu is managed by RM server. It also fixed the dump caused by reading fuse register. Jira EVLR-1934 Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612774 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: PMU parity HWW ECC supportDavid Nieto2017-12-11
| | | | | | | | | | | | | | | Adding support for ISR handling of ECC parity errors for PMU unit and setting the initial IRQDST mask to deliver ECC interrupts to host in the non-stall PMU irq path JIRA: GPUT19X-83 Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef Signed-off-by: David Nieto <dmartineznie@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611625 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use device_is_iommuable() only for iGPUTerje Bergstrom2017-12-11
| | | | | | | | | | | | | | device_is_iommuable() is defined only in Tegra kernel. There is no explicit config option to check for its existance, so skip building that code when Tegra iGPU is not supported. Change-Id: I50dc47070fa416181d458beabf5a2f2373931331 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612649 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_vzalloc() instead of vzalloc()Terje Bergstrom2017-12-11
| | | | | | | | | | | | | | debug_fifo.c uses vzalloc(), but frees the allocation with nvgpu_vfree(). Change the vzalloc() into nvgpu_vzalloc() for consistency. Change-Id: I86facf81752def3dd10fd0cf4cd30e652099f8a5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612647 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc_tpc_mask setting for gv11bDeepak Nibade2017-12-10
| | | | | | | | | | | | | | Pre-gv11b we only had 2 TPCs in a GPC. But on gv11b we have 4 TPCs in a GPC. Hence update gr_gv11b_set_gpc_tpc_mask() as per new configuration and allow setting bits based on number of TPCs Bug 2031635 Change-Id: I44f5f6ce5f3e2501c229c9fcda36fb330ebf8bd0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614044 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add tsg release commandRichard Zhao2017-12-10
| | | | | | | | | | | | | | | | gv11b needs tsg release callback to release CE method buffer. Bug 2022929 Change-Id: I32e27a5fa49eb61b9c2fc72ea32034191a9be48e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611631 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use only standard size definesTerje Bergstrom2017-12-09
| | | | | | | | | | | | | SZ_4G is not defined in mainline Linux. Use SZ_1G*4 instead. Change-Id: I6d226d49da59e4e7b47ccef364b03b82c5758f57 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612648 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add include path for rmos sort.hDeepak Nibade2017-12-08
| | | | | | | | | | | | | | Add rmos sort.h include path in common sort.h if __KERNEL__ is undefined Jira NVGPU-447 Change-Id: I33f1e3a49ee43b1b69f9d678af77cb866dab412b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614108 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Move GR IDLE timeout definition to headerTerje Bergstrom2017-12-08
| | | | | | | | | | | | | GR IDLE timeout is defined as Kconfig. Instead of that introduce a new header file defaults.h which encapsulates any generic defaults we use in nvgpu, and move the definition there. Change-Id: I78ff1d2790d7ee3dff6df42bbd11cf683a85bf79 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612650 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmgrpmu: Reduce stack usageTerje Bergstrom2017-12-08
| | | | | | | | | | | | Allocate PMU PWRMGR structure from heap instead of stack. It is very big and can cause build errors on some compilers. Change-Id: I2727bb70d04b61c1ea43cfb7398b7b14b01e78ee Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612646 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix int declarationDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | | | | variable g->gr.ctx_vars.regs_base_index is declared as "int", but it is assigned value from unsigned int pointer Since we expect it to be unsigned at all the places, declare it as "u32" instead of "int" Jira NVGPU-449 Change-Id: I2a5b35698c655fa0caa3e38e37ed4d84569c996a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612446 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu API to check for allocated memoryDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | | | In __gr_gk20a_exec_ctx_ops(), we directly access linux specific pages to check if memory is allocated or not Since we need to remove this linux specific dependency from common code, use common API nvgpu_mem_is_valid() to check if memory is allocated or not Jira NVGPU-448 Change-Id: Iad62482ad1c0dfad3b96c6c125c2641bbe6ea596 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612445 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix unsigned int declarationDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_init_access_map(), we declare num_entries as "unsigned int" But this variable is implicitly type casted into "int" while calling subsequent functions Hence explicitly declare it as type "int" Also declare variable "w" as "int" too since we use it to compare against num_entries Jira NVGPU-446 Change-Id: I289da6951db0a9ed6b8d6bcb3ee4f6071a4ddaf0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612444 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add missing nvgpu/bug.h include in gr_gv11b.cDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | Add missing <nvgpu/bug.h> include in gr_gv11b.c This include is needed for WARN_ON() API Jira NVGPU-445 Change-Id: Iaa26900c1ecaf1d2f63f84d5b1e437d952a1b9df Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612443 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu list APIs instead of linux APIsDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling Linux specific list APIs list_for_each_entry() Jira NVGPU-444 Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612442 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update elpg init seq for gv11b.Deepak Goyal2017-12-08
| | | | | | | | | | | | | | | | This updates register address/value pairs for ELPG init sequence in GV11B. Bug 200365505. Change-Id: I62517c378c39f5025f797cf849f10e6b0eae27a8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612642 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init alloc_blob_space fn ptrSeema Khowala2017-12-06
| | | | | | | | | | | | | | | Use NVGPU_DMA_FORCE_CONTIGUOUS for non-wpr blob alloc. CPU writes some data to non WPR blob (sysmem). ACR binary executing from PMU, first copies that data to DMEM and then copies that data into WPR. Without NVGPU_DMA_FORCE_CONTIGUOUS, secure boot fails due to ACR writing wrong bootloader data to PMU DMEM. Bug 200355756 Change-Id: I18982caff62b2e7cbe64ea98c1bb935496cfe91c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1610491 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove inline keyword from css_hw_set_handled_snapshotsSourab Gupta2017-12-06
| | | | | | | | | | | | | The patch removes the inline qualifier from the 'css_hw_set_handled_snapshots' function, otherwise it leads to QNX compilation failure. Change-Id: I5c3462b61fbfb2b549e711dd2b45032b3a87089c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1610984 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix indexing in locate pte functionDavid Nieto2017-12-05
| | | | | | | | | | | | | | | | | | | The current code does not properly calculate the indexes within the PDE to access the proper entry, and it has a bug in assignement of the big page entries. This change fixes the issue by: (1) Passing a pointer to the level structure and dereferencing the index offset to the next level. (2) Changing the format of the address. (3) Ensuring big pages are only selected if their address is set. Bug 200364599 Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1610562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>
* gpu: nvgpu: Define create_from_phys when nvhost enabledTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Define __nvgpu_mem_create_from_phys only in systems with nvhost enabled. The calling code is also built only when nvhost is enabled. phys_to_page() also exists only in arm64, so using it in non-arm64 platform causes a build failure. Change-Id: Iee023b55bba863d46079796e1c49c19456c1d229 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: modify subcontext header sizeAparna Das2017-12-01
| | | | | | | | | | | | | | | | | Per veid header mode is enabled for subcontext header. Allocate only context header size for subcontext header. Jira EVLR-2073 Change-Id: I2761dcac7e8e765acb6db22241e3a9214867f885 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607627 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Increase programmed ctagline at compr page boundariesSami Kiminki2017-12-01
| | | | | | | | | | | | | | | | | Increase the ctagline that is programmed in the page tables when the buffer offset crosses the compression page boundaries. This fixes compressible-kind fixed-address mapping with 4k pages when the GPU VA is not aligned by the compression page size. Bug 1995897 Bug 2011640 Bug 2011668 Change-Id: I1f1f9750635a20a916527c9d18fda7f8aa6b1b1f Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1608465 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove extra CPU flushes in sim_gk20a.cTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Simulation does not model CPU caches, so remove extra CPU flushes. The flushes are defined only in Tegra Linux kernel, so they cause build errors on other kernels. Change-Id: I5530a9ea8beac4b7c1ac30f32524afa418110daf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607582 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix build with Tegra DVFS disabledTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Avoid using Tegra DVFS APIs when it is not built in. This is done by protecting the code using Tegra DVFS with #ifdef. Change-Id: Ia50b77aba8a085f436891e522514bb2b5b717c4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607583 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Include vmalloc.h in nvgpu_mem.cTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | nvgpu_mem.c uses vmap(), which is defined in linux/vmalloc.h, but does not include it. Add the missing #include. Change-Id: I38a44083f08f91df50e372c7f1732e2ad27c6bb1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607578 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix ioctl.c w/ disabled ctxsw tracingTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | | | ioctl.c defines file_operations structure for ctxsw tracing. The definition is not protected by the build flag CONFIG_GK20A_CTXSW_TRACE. Add the protection. Change-Id: If82d6e2436d18d72b8eb43d490111c7d5ee0b41c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607577 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add missing include in cond.hTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | include/nvgpu/linux/cond.h uses symbols from linux/sched.h, but does not include it. Add the missing include. Change-Id: Ib020ab98f0401a29628bbd0d9e0a55b294563fd5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607576 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce include/nvpgu/sizes.hTerje Bergstrom2017-12-01
| | | | | | | | | | | | We use SZ_* #defines in some parts of nvgpu, but we don't explicitly include a header that defines it. Add include/nvgpu/sizes.h that in Linux #includes linux/sizes.h. Change-Id: I8f506d85c7eaa12e649f5874a87533e2f0fe9438 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607575 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove linux dependent from pmu_gk20a.cMahantesh Kumbar2017-12-01
| | | | | | | | | | | | | | | | | | | | | - Removed Linux dependent header - Moved thermal alarm post from pmu_gk20a.c to clk_arb.c - Implemented nvgpu_clk_arb_send_thermal_alaram() method to post NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD JIRA NVGPU-403 Change-Id: Ibf85c2f3a6e704fdcc0502745fab820f7ea428f4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1608313 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Alignment check for compressible fixed-address mappingsSami Kiminki2017-11-30
| | | | | | | | | | | | | | | | | Add an alignment check for compressible-kind fixed-address mappings. If we're using page size smaller than the comptag line coverage window, the GPU VA and the physical buffer offset must be aligned in respect to that window. Bug 1995897 Bug 2011640 Bug 2011668 Change-Id: If68043ee2828d54b9398d77553d10d35cc319236 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606439 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvgpu/bug.h include to some MM filesAlex Waterman2017-11-30
| | | | | | | | | | | | | | | | | | Add <nvgpu/bug.h> to MM files that use any of the BUG, BUG_ON, WARN, WARN_ON, etc, macros but do not yet include <nvgpu/bug.h>. JIRA NVGPU-401 Change-Id: I538219683d2a52b15abf147ff4bcf6375b6cb8a0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599960 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove linux specific include from gr_*.c filesDeepak Nibade2017-11-30
| | | | | | | | | | | | | | | Remove linux specific #include "common/linux/os_linux.h" from common source files gr_gk20a.c/gr_gm20b.c/gr_gp10b.c Remove use of ZERO_OR_NULL_PTR() and simply check if pointer is NULL or not Jira NVGPU-405 Change-Id: I663fe298cc720f0b0e22beaa05697b18b375a204 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607233 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: files sim_gk20a.* are changed to sim.*Debarshi Dutta2017-11-30
| | | | | | | | | | | | | | | | | The files sim_gk20a.c and sim_gk20a.h under common/linux/ are renamed to sim.c and sim.h as the suffix gk20a is not needed. JIRA NVGPU-386 Change-Id: I79bbb8e66c4b0cf53f2b1f98a7bed5f682106a0c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606975 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: gfxp wfi timeoutseshendra Gadagottu2017-11-29
| | | | | | | | | | | | | | | | | | | | | | For gv11b, configured gfx preemption wfi timeout in usec. Set timeout unit as usec in gr_gv11b_init_preemption_state. Used default timeout as 1msec and this timeout value can be modified through sysfs node: /sys/devices/gpu.0/gfxp_wfi_timeout_count For gp10b: gfxp_wfi_timeout_count is in syclk cycles For gv11b: gfxp_wfi_timeout_count is in usec Bug 2003668 Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599658 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove soc includes from gr_gp10b.cDeepak Nibade2017-11-29
| | | | | | | | | | | | | | | | | All soc includes in gr_gp10b.c are redundant now, hence remove them Jira NVGPU-405 Change-Id: I759fbd4f54960dae7f44bd53d3c5c52d9351c950 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:07:32 -0500