| Commit message (Collapse) | Author | Age |
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Request irq at probe instead of at poweron. This allows investigating
interrupt numbers across rail gating cycles.
Change-Id: I6db4b3f1d865c6fbbd9d6a96c3df89617e169891
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/374859
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Interrupts may be needed before we have actually silenced all
channels. Few possible scenarios include channel recovery during
teardown and sw method before the channels have been suspended.
This patch modifies the teardown path so that we disable interrupts
after the channels have been suspended.
Change-Id: Ifc36dbb74b1d36bd88d1220fa50a53c4072df4d8
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/394599
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Result of top_fs_status_r() is always constant. Do not dump it
anymore.
Change-Id: Ie1cfe872d70b2c3c8a7cef4df3870dacae8f8793
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/395208
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Change-Id: I30baee4084399b8078232f31296c4d891a903d47
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/395123
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add abstraction for triggering fake MMU fault, and a gk20a
implementation. Also adds recovery to FE hardware warning
exception to make testing easier.
Bug 1495967
Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Backing store sgt needs to be mapped to gpuva to enable CDE swizzling.
This patch adds necessary code to create sgt during initialisation so
that the sgt is available when needed.
Bug 1409151
Change-Id: I9d4671386fe9204d780c2e286b5f9b2dd87af35a
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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CBC frontdoor access works incorrectly in the simulator if CBC
is allocated from IOVA. This patch makes CBC allocation to happen
from physical memory if are running in simulator.
Bug 1409151
Change-Id: Ia1d1ca35b5a0375f4707824df3ef06ad1b9117d4
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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Ensure CBC is invalidated at GPU initialization.
Bug 1409151
Change-Id: I054be20a3252e40c96baec75958918c85a5a7801
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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Bug 1409151
Change-Id: I232af159d402f818cf972498d721c3b57846ce74
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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This patch modifies the code to fall-back to 4k pages if the current
VA does not support 128k pages.
Bug 1409151
Change-Id: I94e9ca5953740388db689bc9306b0392191e29d2
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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This patch adds necessary code to store the gpu configuration into
gr structure.
Bug 1409151
Change-Id: I045b21ebdc849833380a3d953d951f8352842ac7
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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debug print "Waiting on syncpt" for gpu channel prints that
channel is waiting for the syncpt without checking the state
of the channel
hence modify this print as follows :
if channel is in "pending acquire" or "on_eng_pending_acquire"
state we print "Waiting on syncpt"
otherwise we print "Waited on syncpt"
Bug 1305024
Change-Id: Ie22db689d6e8016c63158e8961d2233042069bec
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/394715
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1494200
Bug 1492505
Change-Id: I77bbe4f775780e80de1b8f9279be82926f3ed7c9
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/393738
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
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Ensure devfreq is disabled before shutting down gk20a, to prevent
possible races with reading of gpu load, and the shutdown of gpu itself.
Bug 1492913
Change-Id: I016fdba9515120fc6cf3e771f60c61b9bf2027cb
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/394296
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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domain name should be different from device name.
Change-Id: I6c7d6927d6fc5bada203d749f107c17043233501
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/392327
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix regression caused by commit 67fa249b419d32bfd0873fe5d924f4f01d9048de
"video: tegra: host: Abstract gk20a channel synchronization".
The above change unintentionally modified the channel synchronization
logic so that an nvhost interrupt handler was scheduled also when idling
the channel in gk20a_channel_submit_wfi. That appears to cause
intermittent hangs when running CUDA tests.
Bug 1484824
Change-Id: I4a1f85dd9e6215350f93710a2be9b0bbaef24b8f
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/394127
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Free IRQs before the various subunits are suspended. This is to prevent
potential races between the IRQ thread and the suspend routine.
Bug 1437749
Change-Id: Iffef918feecae0b256be96efd02b01b2677c225d
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Queue locked variable holds entirely redundant information about the
queue status and having the variable causes a race between lock() and
unlock() functions. This patch removes the locked variable.
Bug 1495617
Change-Id: I05682bfe7a23acc77c2bfe405938ace7d2b3d081
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/393431
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This patch adds a field to the gpu capability ioctl to allow
requesting the maximum VA a single PDE entry can hold.
Bug 1456570
Change-Id: I5cf29c8816fa6ea396c36419e6821c27a805b8af
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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Bug 1443071
Change-Id: I225114835a5923061462e238395798b274cadd7b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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add valid syncpt id checks when syncpt id is
extracted from fence fd
Bug 1448825
Change-Id: I0f1722aad60e7644b8f490f24cf18a3b80f8583c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/390572
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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On 64 bit architecture, we have plenty of vmalloc space
so that we can keep all the ptes mapped always
But on 32 but architecture, vmalloc space is limited and
hence we have to map/unmap ptes when required
Hence add new APIs for arch64 and call them if
IS_ENABLED(CONFIG_ARM64) is true
Bug 1443071
Change-Id: I091d1d6a3883a1b158c5c88baeeff1882ea1fc8b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/387642
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Wait for FE idle between SW bundles.
Bug 1477234
Bug 1486347
Bug 1485069
Change-Id: I5181b1240fff73cfecd07aa3e54076cde800ea00
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/391591
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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During the ELPG initialization routine, ELPG should be explicitly
disabled before we save the zbc table. This ensures that even if there
is a preemption from some other thread that calls ELPG enable/disable,
the ref counting will ensure that ELPG remains disabled.
Bug 1490085
Change-Id: Ie8eeaf48dda4e7f810aa26926facf63753e86abe
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/382273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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After flash, kernel needs to reboot after first boot.
During reboot, devices is going to be shutdown including i2c.
But sometimes gpu driver trys to open gpu sysfs nodes and
unpowergate gpu at the same time. But i2c is already shutdown.
tegra_unpowergate_partition returns error in this case but
gk20a_tegra_unrailgate did not report the error so the error
is not handled. Return proper value in gk20a_tegra_unrailgate
to avoid this.
Bug 1488409
Change-Id: I3470ad44a0047ae9b06f5907162ccf51795a5e04
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/390688
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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nvhost_get_syncpt_host_managed() creates syncpt name based on
platform_device pointer passed to it
Passing host1x's pointer to this API results in setting gk20a
syncpt names as "host1x_0" which is conflicting
Hence to restore this pass gk20a's device pointer
which gives syncpt names as "gk20a.0_0"
Bug 1305024
Change-Id: I40325f2e4e2d9ea8de1d44e136edcb48a431e45c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/389671
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add two fb flushes after bar1 bind. This should hang the thread instead
of whole system in case there is a BAR1 hang.
Change-Id: I2385a243711219297b889daa30c9fc81106e5825
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/390183
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We poll completion of flush sequence by polling the broadcast
register. The polling should be done for a per-slice register
instead.
Bug 1457723
Change-Id: I10aba939175b6d05b05f5f26eebebcbe09d9b4a7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/382521
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Decouple the firmware selection of different gpu architecture.
Change-Id: I62bf6b3bc51a8606c5973e475988cd5987a65a1a
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/389793
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This patch moves the NVIDIA GPU driver to a new location.
Bug 1482562
Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move all channel synchronization code to new channel_sync_gk20a.c/h
files, and access all synchronization functions through function
pointers. This is groundwork for supporting semaphore based channel
synchronization.
Bug 1434573
Bug 1450122
Change-Id: Ic21709c1ee8cf85d018616787988e7eebb399fbe
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/374841
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This patch modifies gk20a driver to use its own trace events instead
of trace events of nvhost.
Bug 1468086
Change-Id: I1f40ba957ec7e25904e9f4621346cb7dc256a550
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/374289
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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