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* gpu: nvgpu: Add missing braces in nvgpu_mem.cTerje Bergstrom2018-08-11
| | | | | | | | | | | | | | | | When built with -Wmissing-braces, compiler complains about the missing braces in nvgpu_mem_rd_n, nvgpu_mem_wr_n and nvgpu_memset. Add the braces to satisfy compiler and to fix related MISRA C violations. Change-Id: Ibe3606dc59317f8230cea57cfea8d0fe5af641d6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796238 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add U64() and U32() macrosAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These macros exist to make integer literals used in certain arithmetic operations explicitly large enough to hold the results of that operation. The following is an example of this. In MISRA the destination for a bitwise shift must be able to hold the number of bits shifted. Otherwise the results are undefined. For example: 256U << 20U This is valid C code but the results of this _may_ be undefined if the size of an unsigned by default is less than 24 bits (i.e 16 bits). The MISRA misra checker sees the 256U and determines that the 256U fits in a 16 bit data type (i.e a u16). Since a u16 has 16 bits, which is less than 20, this is an issue. Of course most compilers these days use 32 bits for the default unsigned type this is not a requirement. Moreover this name problem could exist like so: 0xfffffU << 40U The 0xfffffU is a 32 bit unsigned type; but we are shifting 40 bits which overflows the 32 bit data type. So in this case we need an explicit cast to 64 bits in order to prevent undefined behavior. Change-Id: If2433fb8c44df0c714487fa3b6b056fc84570df7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795391 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove utils.h from gk20a.hVinod G2018-08-10
| | | | | | | | | | | | | | | | Removed the utils.h include from gk20a.h utils.h is included in those files which make use of the macros in utils.h JIRA NVGPU-1005 Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785952 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move exec_reg_ops() to regops HALDeepak Nibade2018-08-10
| | | | | | | | | | | | | | | | | We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations But we have separate gops.regops operations for all the regops and this would be logically correct place for exec_reg_ops() Move exec_reg_ops() from gops.dbg_session_ops to gops.regops Also rename it to exec_regops() Jira NVGPU-620 Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Add a posix-bitmap impl unit testAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | | Add a unit test to test the nvgpu-posix bitmap implementation. This unit test aims to both verify the functionality of this low level set of APIs and provide a reference for how to use the basic unit test functionality. JIRA NVGPU-525 Change-Id: Ide5263e5ce49f18f5f2a3d4a6f9e494395299386 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1695007 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Add test unit moduleAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | | | | Add a super simple tiny test unit module to test the unit test framework. This unit test has a test that deliberately fails so it obviously cannot be part of a real unit test run. Eventually this will have to be removed or otherwise skipped. JIRA NVGPU-525 Change-Id: I41532a85156445a778897bbc84bb5919deab56ae Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687095 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Sort unit tests by priorityAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort unit tests by their priority before running said unit tests. There are three available priorities: UNIT_PRIO_SELF_TEST UNIT_PRIO_POSIX_TEST UNIT_PRIO_NVGPU_TEST Which correspond to the types of testing expected to be run. In general unit tests should always just use UNIT_PRIO_NVGPU_TEST but in the case of tests for the POSIX API layer or the unit test framework the other two priorities are provided. The reason for this is that it doesn't make much sense to run a bunch of unit tests if the environment itself or the POSIX API layer is broken. By placing these tests at the front of the list of tests to run an engineer will easily be able to see if there are core problems versus nvgpu problems. This also lets users fine grain control of test order by adding or subtracting to UNIT_PRIO_NVGPU_TEST but one must be very careful about how they do this. JIRA NVGPU-525 Change-Id: I12a5b798e998f34e4d1168bb3696c579460f20b1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741953 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unit: Add unit testing FWAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | Full documentation for this is in the unit testing confluence page. JIRA NVGPU-525 Bug 2261555 Change-Id: I463e6267eb0eb12b7313f8b275266e8faabe5ccf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683915 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move xve HAL to commonTerje Bergstrom2018-08-10
| | | | | | | | | | | | Move implementation of xve HAL to common/xve. JIRA NVGPU-959 Change-Id: I27dba43253e3aa8fd11229a9c4fad97aa5cf0b59 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796147 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 15.6 violationsSrirangan2018-08-10
| | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces including single statement loop bodies. This patch fix the MISRA violations due to single statement loop bodies without braces by adding them. JIRA NVGPU-989 Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791194 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make cbc alloc os specificAparna Das2018-08-09
| | | | | | | | | | | | | | | | | | | | | CBC base needs to be aligned to 64KB. On Linux this is achieved making compbit backing size multiple of 64KB. However QNX nvmap alloc function does not allocate memory aligned to requested size and needs to overallocate to satisfy alignment requirement. Make cbc alloc function OS specific to be able to modify QNX code. Also align cbc base address to 64KB before writing to CBC BASE register. Bug 200426427 Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4 Signed-off-by: Aparna Das <aparnad@nvidia.com> (cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36) Reviewed-on: https://git-master.nvidia.com/r/1786046 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add PMU rpc replyVaikundanathan S2018-08-09
| | | | | | | | | | | | | | | | | Add reply messages for Therm, clock and Perf. Bug 200428344 Change-Id: Ifb325d546a81f6810ac88b87cc10b718d279ac82 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792825 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle error return for exec_reg_ops failure.Debarshi Dutta2018-08-09
| | | | | | | | | | | | | | The error returned from the execution of exec_reg_ops was ignored leading to not propagating the error values to the caller methods. This patch handles the error occurence in the exec_reg_ops call. Bug 2245743 Change-Id: I0d696c116fc1b2fce0e14ac7a05e1d85b5d18129 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775818 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependencyDebarshi Dutta2018-08-08
| | | | | | | | | | | | | | | | | clk_arb.h and gk20a.h has circular dependencies to each other. This is removed by forward declaring struct gk20a in clk_arb.h and removing the header gk20a.h from clk_arb.h and similarly forward declaring struct nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h alongwith putting headers in every execution unit which calls clk_arb.h related methods. JIRA NVGPU-597 Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASKVinod G2018-08-08
| | | | | | | | | | | | | | | | | Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is added to dbg session. Currently support SM_EXCEPTION_TYPE_MASK_FATAL type If this type is set then the code will skip RC recovery, instead trigger CILP preemption. bug 200412641 JIRA NVGPU-702 Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729792 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move ce2.c to common codeSourab Gupta2018-08-08
| | | | | | | | | | | | | | | | | | | ce2.c is free of all Linux'isms and can be moved to the common code, so that it can be used by other OS'es. VQRM-3705 Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792100 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 10.1 issues in gr reset codeScott Long2018-08-08
| | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations involving need_reset var in gk20a_gr_isr(). Changed type to bool and set it to true any time one of the pending condition checks returns non-zero. JIRA NVGPU-650 Change-Id: I2f87b68d455345080f7b4c68cacf515e074c671a Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793633 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass correct argument to sysfs_attr_initVince Hsu2018-08-07
| | | | | | | | | | | | | | | | | | | The sysfs_attr_init accepts pointer of struct attribute instead of struct device_attribute. This patch fixes build error when CONFIG_DEBUG_LOCK_ALLOC is enabled. Bug 200432223 Change-Id: Id655ca18102c5252485db378ba2499a66d758882 Signed-off-by: Vince Hsu <vinceh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1786590 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange some definitions from gk20a headerVinod G2018-08-07
| | | | | | | | | | | | | | | | | | Moved the gk20a_from_as and gk20a_from_pmu definitions from gk20a.h to as.h and pmu.h Correction for MISRA rule 21.1 error in as.h and pmu.h headers JIRA NVGPU-624 Change-Id: I57de604b47afc589a9778fe69e4856ffcabd9dfc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785951 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reduce verbosity of TPC PG mask and status being sameLeon Yu2018-08-06
| | | | | | | | | | | | | | | | | | | | | Once tpc_pg_mask is programmed successfully, TPC PG mask and status will be the same value afterwards and won't change. So we don't have to inform user whenever gr_gv11b_powergate_tpc() is invoked. Bug 200406784 Bug 200436857 Change-Id: I52f7bdbbbc0851b59366b1cd7d25ae7b8b9fa14e Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791008 (cherry picked from commit c8872d61a2bc40e09e137a4bb81923c4747a2dcc) Reviewed-on: https://git-master.nvidia.com/r/1791656 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Fix MISRA 15.6 violationsSrirangan2018-08-06
| | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/gk20a/ JIRA NVGPU-989 Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791019 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc_tpc_mask to use max_gpc_countRichard Zhao2018-08-06
| | | | | | | | | | | | | | | | | | gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to use max_gpc_count for any possible cases rather not gpc_count. Bug 2302005 Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790464 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Fix MISRA 15.6 violationsSrirangan2018-08-03
| | | | | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers gpu/nvgpu/gm20b/ JIRA NVGPU-989 Change-Id: Ia177bd990409500fc8e8a2a54ba013df84cb9822 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1788050 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer"Vinod Gopalakrishnakurup2018-08-02
| | | | | | | | | | This reverts commit 96d4842c0dbae051258408480b981ed034163c13. Change-Id: Ibcdf78b242c7bb9f17651b2bb9e23777c97cd436 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790634 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 10.1 issues in SIM codeScott Long2018-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations in gr_gk20a_init_ctx_vars_sim(). Instead of logically ORing alloc_xxx_list_yyy() results into the signed err variable just bail immediately if an allocation request fails. Also made changes to sync gr_gk20a_init_ctx_vars_sim() behavior with gr_gk20a_init_ctx_vars_fw() behavior: * return a valid errno on failure * free any previously allocated resources on failure JIRA NVGPU-650 Change-Id: Ie5ea78438da59896da2a9f562d01e46ffaf56dec Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787042 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow global regops before ctx is createdDeepak Nibade2018-08-02
| | | | | | | | | | | | | | | | | | | In nvgpu_ioctl_channel_reg_ops(), we right now first check if context is allocated or not and if context is not allocated we fail the regops operation But it is possible that the regops operation only includes global regops which does not need global context allocated So move this global context check from nvgpu_ioctl_channel_reg_ops() to exec_regops_gk20a() and only if we have context ops included in the regops Bug 200431958 Change-Id: Iaa4953235d95b2106d5f81a456141d3a57603fb9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1789262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: Fix MISRA 15.6 violationsSrirangan2018-08-02
| | | | | | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/common/ JIRA NVGPU-989 Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1786207 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support PCI device id 0x1efaDeepak Nibade2018-07-31
| | | | | | | | | | | | | | Add support for PCI device id 0x1efa which has same driver data as of 0x1eba device Change-Id: If3d53fe116c711bf63a10eae0e731537b3705bc1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1788694 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mask intr before gpu power offNitin Kumbhar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | once gpu is powered off i.e. power_on set to false, nvgpu isr does not handle stall/nonstall irq. Depending upon state of gpu, this can result in either of following errors: 1) irq 458: nobody cared (try booting with the "irqpoll" option) 2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is not in time. Fix these by masking all interrupts just before gpu power off as nvgpu won't be handling any irq anymore. While masking interrupts, if there are any pending interrupts, then report those with a log message. Bug 1987855 Bug 200424832 Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon queue supportMahantesh Kumbar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Renamed "struct pmu_queue" to "struct nvgpu_falcon_queue" & moved to falcon.h -Renamed pmu_queue_* functions to flcn_queue_* & moved to new file falcon_queue.c -Created ops for queue functions in struct nvgpu_falcon_queue to support different queue types like DMEM/FB-Q. -Created ops in nvgpu_falcon_engine_dependency_ops to add engine specific queue functionality & assigned correct HAL functions in hal*.c file. -Made changes in dependent functions as needed to replace struct pmu_queue & calling queue functions using nvgpu_falcon_queue data structure. -Replaced input param "struct nvgpu_pmu *pmu" with "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail & also for functions gk20a_pmu_queue_head()/ gk20a_pmu_queue_tail(). -Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue for PMU queue. -Modified Makefile to include falcon_queue.o -Modified Makefile.sources to include falcon_queue.c Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 11.6 issue with _THIS_IP_Scott Long2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | The use of the _THIS_IP_ macro in nvgpu introduces two separate MISRA Rule 11.6 violations. The first is when when the label address (which gcc generates as a void *) is cast to an unsigned long and the second is when that unsigned long is cast back to a void * in the timer and kmem code that track the value. Skipping the intermediate use of unsigned long eliminates these violations. To do this, references to _THIS_IP_ are replaced with a new (compliant) _NVGPU_GET_IP_ macro. JIRA NVGPU-895 : MISRA Rule 11.6 violations Change-Id: I5ea999d8e2b467257fa190b485fa971adcbd0a2b Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774531 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 11.6 issue with fence pool mgmtScott Long2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 11.6 prohibits the casting of an integer value to a void *. The nvgpu allocator used for the fence pool stores the base address of the associated memory as a u64 and returns it via nvgpu_alloc_base(). In gk20a_free_fence_pool() this u64 value was cast to a void * before being passed to nvgpu_vfree() (leading to the violation). This change modifies gk20a_free_fence_pool() to cast the base address back to the original struct gk20a_fence * to eliminate the violation. JIRA NVGPU-895: MISRA Rule 11.6 violations Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774530 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set preempt timeoutSeema Khowala2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | -For Si platforms, gk20a_get_gr_idle_timeout returns 3000 ms i.e. 3 sec. Currently this time is used for preempt polling and this conflicts with channel timeout if polling times out. Use fifo_eng_timeout_us converted to ms for preempt polling. -In case of preempt timeout, do not issue recovery for si platform. ctxsw timeout will trigger recovery if needed. For non si platforms, issue preempt timeout rc if preempt times out. Bug 2113657 Bug 2064553 Bug 2038366 Bug 2028993 Bug 200426402 Change-Id: I8d9f58be9ac634e94defa92a20fb737bf256d841 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762076 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: acquire/release runlist_lock during teardown/mmu_faultSeema Khowala2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Recovery can be called for various types of faults. Acquire runlist_lock for all runlists so that current teardown is done before proceeding to next one. -For legacy chips teardown is done by triggering mmu fault so make sure runlist_locks are acquired during teardown and also during handling mmu fault. -gk20a_fifo_handle_mmu_fault is renamed as gk20a_fifo_handle_mmu_fault_locked -gk20a_fifo_handle_mmu_fault called from gk20a_fifo_teardown_ch_tsg is replaced with gk20a_fifo_handle_mmu_fault_locked -gk20a_fifo_handle_mmu_fault acquires/release runlist_lock for all runlists and calls gk20a_fifo_handle_mmu_fault_locked Bug 2113657 Bug 2064553 Bug 2038366 Bug 2028993 Change-Id: I973d7ddb6924b50bae2d095152867e99c87e780a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761197 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow all sizes in access fb APIDeepak Nibade2018-07-26
| | | | | | | | | | | | | | | | | | | | | For IOCTL NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY, we do not allow size of buffer which is not 4 byte aligned Remove this hard restriction and allow non 4 byte aligned buffer sizes too since we don't really need to enforce this restriction Bug 2265535 Change-Id: Ic4d60604be3698e8629f2b289c9e2d19e20ea525 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1784511 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: shutdown nvlink in driver removeNitin Kumbhar2018-07-26
| | | | | | | | | | | | | During driver remove, if nvlink is set up, gracefully shut it down so that it can be enumerated again. Bug 1987855 Change-Id: Ibd83a5e29364b22264e689aa879569a9cccf0f79 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746073 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update regops whitelistVinod G2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | Update the regops whitelist registers. newly added whitelisted registers are NV_PERF_PMASYS_RECORD_START_TRIGGERCNT NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT Bug 2251693 Change-Id: If974e9517e1bb25cf29aed468ce0c20c23199857 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1782112 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange the static inline codeVinod G2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid the circular dependencies, rearrange the static inline functions from gk20a.h file. Moved gk20a_gr_flush_channel_tlb function to gr_gk20a.c and removed the #include gr_gk20a.h from gk20a.h Added a helper function utils.h to move all generic static inline functions which have no reference to gpu related structures. ptimer related functions are moved to ptimer.h Implementations for as and pmu are moved to corresponding files. JIRA NVGPU-624 Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781941 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: debugfs node to enable/disable ltc_illegal_compstat intrseshendra Gadagottu2018-07-24
| | | | | | | | | | | | | | | | | | | Added debugfs node under ltc directory with name: intr_illegal_compstat_enable Enabling/disabling of ltc_illegal_compstat intr is possible through debugfs node. Since ltc state is lost with rail gate, this setting is cached and will be populated during ltc initialization. Bug 2099406 Change-Id: I4bf62228dfd2bbb94f87f923f9f4f6e5ad0b07f0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774683 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv1xx: disable ltc_illegal_compstat interruptseshendra Gadagottu2018-07-24
| | | | | | | | | | | | | | Illegal compstat interrupt indicates an unexpected compression status given the kind. Since dirty tile mappings expected to have discrepancies in compbit state, so disabling illegal compstat interrupt. Bug 2099406 Change-Id: I90207c6bc8a8cfa656ea9a0b4f5605106751c12e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774572 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: tpc powergating through sysfsDeepak Goyal2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | - adds static tpc-powergating through sysfs. - active tpc count will remain till the GPU/systems is not booted again. - tpc_pg_mask can be written only after GPU probe finishes and GPU boot is triggered. Note: To be able to use this feature, we need to change boot/init scripts of the OS(used with nvgpu driver) to write to sysfs nodes before posting discover image size query to FECS. Bug 200406784 Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742422 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not access register in vidmem destroyAparna Das2018-07-20
| | | | | | | | | | | | | | | | | | | | Do vidmem destroy only if get_vidmem_size HAL op is set which will skip this for iGPU. Do not read vidmem size explicitly in vidmem destroy in shutdown path after prepare poweroff. Bug 200427479 Change-Id: Ic919b03d44b5505646b449fd74f9f5d3e9e0dfee Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776388 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable fb fault buffer in prepare poweroffAparna Das2018-07-20
| | | | | | | | | | | | | | | FB fault buffer is enabled on finalize poweron. Disable the buffer in prepare poweroff. This also eliminates the need to disable the buffer in fault info mem destroy which otherwise accesses GPU registers after these are locked in prepare poweroff. Bug 200427479 Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776387 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not disable fb hub intr in fault info mem destroyAparna Das2018-07-20
| | | | | | | | | | | | | | | | | | | | | | FB hub intr is enabled on finzalize_poweron and disabled on prepare_poweroff. There is no need to additionally disable FB hub intr in fault info mem destroy when driver refcount becomes zero since prepare_poweroff has already been called. Also prepare_poweroff locks GPU registers from CPU access so these registers should not be accessed after prepare_poweroff. Bug 200427479 Change-Id: I62c355502ea494a1d0528c8668cae63743b8957b Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776386 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rework ecc structure and sysfsRichard Zhao2018-07-19
| | | | | | | | | | | | | | | | | | | | | - create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: issue runlist preempt during teardownSeema Khowala2018-07-19
| | | | | | | | | | | | | | | | -During teardown issue runlist preempt -preempt_ch_tsg hal is removed as it is no more required. This hal was added to be called from teardown so that if there is preempt timeout, preempt timeout recovery is not triggered. Bug 200426402 Change-Id: I679e3306aa890ff0cfa211cfcc7d5405b7cb1211 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775443 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: set preempt timeoutSeema Khowala2018-07-19
| | | | | | | | | | | | | For pbdma/eng/runlist preempt polling use fifo_eng_timeout_us converted to ms. Bug 200426402 Change-Id: I2137bb9c5517d27c514ddd7ef0c601230a1ddb16 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775442 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: do not issue preempt timeout rcSeema Khowala2018-07-19
| | | | | | | | | | | | | | | | | Since preempt timeout per pbdam/eng/runlist is set to fifo_eng_timeout_us converted to ms, there could be a scenario where preempt might time out. In case of preempt time out, do not issue recovery for si platform. ctxsw timeout will trigger recovery if needed. For non si platforms, issue preempt timeout rc if preempt times out. Bug 200426402 Change-Id: Ifd921280c0443ee9eda31157aaa03b481a529239 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775441 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert: GV11B runlist preemption patches"Seema Khowala2018-07-19
| | | | | | | | | | | | | | | | | | | This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c. Originally change was reverted as it was making ap_compute test on embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg preempt with runlist preempt during teardown, preempt timeout set to 100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy chips) and not issuing preempt timeout recovery if preempt fails, helped resolve the issue. Bug 200426402 Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 14:31:15 -0500