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* gpu: nvgpu: Move max_css_buffer_size to gr_gk20aTerje Bergstrom2017-11-12
| | | | | | | | | | | | | | | | | | max_css_buffer_size was accessed directly from GPU characteristics, which added a dependency to Linux. Move the field to gr_gk20a and copy it to GPU characteristics at query time. JIRA NVGPU-259 Change-Id: Ied19e33bf1a79a9ce45e33df57fe5bbe3a3c4f9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593689 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: VM map path refactoringAlex Waterman2017-11-10
| | | | | | | | | | | | | | | | | | | | | | Final VM mapping refactoring. Move most of the logic in the VM map path to the common/mm/vm.c code and use the generic APIs previously implemented to deal with comptags and map caching. This also updates the mapped_buffer struct to finally be free of the Linux dma_buf and scatter gather table pointers. This is replaced with the nvgpu_os_buffer struct. JIRA NVGPU-30 JIRA NVGPU-71 JIRA NVGPU-224 Change-Id: If5b32886221c3e5af2f3d7ddd4fa51dd487bb981 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583987 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvgpu_os_bufferAlex Waterman2017-11-10
| | | | | | | | | | | | | | | | | | | | | | | | | Add a generic nvgpu_os_buffer type, defined by each OS, to abstract a "user" buffer. This allows the comptag interface to be used in the core code. The end goal of this patch is to allow the OS specific mapping code to call a generic mapping function that handles most of the mapping logic. The problem is a lot of the logic involves comptags which are highly dependent on the operating systems buffer management scheme. With this, each OS can implement the buffer comptag mechanics however it wishes without the core MM code caring. JIRA NVGPU-30 JIRA NVGPU-223 Change-Id: Iaf64bc52e01ef3f262b4f8f9173a84384db7dc3e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make buf alignment genericAlex Waterman2017-11-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drastically simplify and move the aligment computation for buffers getting mapped into the SGT code. An SGT is all that is needed for computing the alignment. However, this did require that a new SGT op was added: nvgpu_sgt_iommuable() This function returns true if the passed SGT is IOMMU'able and must be implemented by an SGT implementation that has IOMMU'able buffers. If this function is left as NULL then it is assumed that the buffer is not IOMMU'able. Also cleanup the parameter ordering convention among all nvgpu_sgt functions. Previously there was a mishmash of different parameter orderings. This patch now standardizes on the gk20a first approach seen everywhere else in the driver. JIRA NVGPU-30 JIRA NVGPU-246 JIRA NVGPU-71 Change-Id: Ic4ab7b752847cf795c7cfafed5a07818217bba86 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable/disable tegra fuse clockseshendra Gadagottu2017-11-10
| | | | | | | | | | | | | | | | | | | | | | | | GPU hardware block needs tegra fuse clock to mirror gpu fuses from tegra fuses to gpu domain. Tegra fuse driver provided following APIs to enable/disable tegra fuse clock: int tegra_fuse_clock_enable(void); int tegra_fuse_clock_disable(void); To ensure that tegra fuse clock is disabled by nvgpu driver when gpu hardware block is not in use by: Calling tegra_fuse_clock_enable() while doing gk20a_pm_unrailgate() and calling tegra_fuse_clock_disable() while doing gk20a_pm_railgate(). Bug 2019897 Change-Id: I61688829fd9a8b0c1ffa9d34db6393550f333866 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1595297 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove NVGPU_ALLOC_OBJ_FLAGS_* from common codeDeepak Nibade2017-11-10
| | | | | | | | | | | | | | | | | | | | In gr_gp10b_alloc_gr_ctx(), we use linux specific flags NVGPU_ALLOC_OBJ_FLAGS_* Since common code should be independent of linux specific code, define new flags NVGPU_OBJ_CTX_FLAGS_SUPPORT_* in common code and use them wherever needed Linux code will parse the user flags and send appropriate flags to g->ops.gr.alloc_obj_ctx() Also remove use of NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO since this seems to be deadcode anyways Jira NVGPU-382 Change-Id: Id82efe0d46ddc3e2c063610025ea57f283bc3510 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove NVGPU_ALLOC_GPFIFO_EX_FLAGS_* from common codeDeepak Nibade2017-11-10
| | | | | | | | | | | | | | | | | | | | | In gk20a_channel_alloc_gpfifo(), we use linux specific flags NVGPU_ALLOC_GPFIFO_EX_FLAGS_* Since common code should be independent of linux specific code, define new flags NVGPU_GPFIFO_FLAGS_SUPPORT_* in common code and use them in gk20a_channel_alloc_gpfifo() Linux code will parse the user flags and send appropriate flags to gk20a_channel_alloc_gpfifo() Jira NVGPU-381 Change-Id: Ibec51903b3407175fbba727208483b0dc36a5772 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594422 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove PTE kind logicSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | Since NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL was made mandatory, kernel does not need to know the details about the PTE kinds anymore. Thus, we can remove the kind_gk20a.h header and the code related to kind table setup, as well as simplify buffer mapping code a bit. Bug 1902982 Change-Id: Iaf798023c219a64fb0a84da09431c5ce4bc046eb Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560933 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add can_elpg check before elpg callSupriya2017-11-10
| | | | | | | | | | | | | This CL is as part of phased changes to support NO LSPMU Changes done is to add missing can_elpg check JIRA NVGPU-296 Change-Id: Ic4e5ebf208e08a0a9fce6b449f15a2e768281bb1 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1592629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move sm_arch to nvgpu_gpu_paramsTerje Bergstrom2017-11-09
| | | | | | | | | | | | | Move sm_arch_* fields to nvgpu_gpu_params to make them available from common code without accessing Linux specific GPU characteristics. JIRA NVGPU-259 Change-Id: Ieffb2ddde81b27af53dfedb9fe3972d20757cc35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return GPU classes in get_litter_valueTerje Bergstrom2017-11-09
| | | | | | | | | | | | | Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: Ife7a5cb38df3d33ce98a1caa43d3873fb1431234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593683 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse override DT handlingTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | | | | | | Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Iba64a5d53bf4eb94198c0408a462620efc2ddde4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Correct laying of terminating WPR HDRDeepak Goyal2017-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Termination WPR header is inserted in the non-wpr blob so that HS knows when to stop processing WPR headers. nvgpu_mem_wr32 is copying the terminating WPR header @ wrong offset in non-wpr blob. This caused overwriting of the LS signatures present in the non wpr region, thus leading to LS authentication failure for GPCCS falcon. Fix added for t210/t186 as well. Bug 200362639 Change-Id: I60088b2dd2304fb5de0402b28822b305b34394c2 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594862 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: use $(srctree.$(overlay))Stephen Warren2017-11-09
| | | | | | | | | | | | | Update all Makefiles to make use of the new srctree.$(overlay) variables to remove hard-coding the path to any overlays. Bug 1978395 Change-Id: I160efb55536c1d2b1e090895d9d62432a1e4c28c Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: cyclestat characteristics fixesPeter Daifuku2017-11-08
| | | | | | | | | | | | | | | | | | | | | | Fix characteristics for cyclestats: - SUPPORT_TSG and SUPPORT_CYCLE_STATS_SNAPSHOT were assigned the same value - For vgpu, SUPPORT_CYCLE_STATS was set redundantly (but differently) - For vgpu, if the css buffer size is 0, set the support flag to False JIRA ESRM-88 Bug 200296210 Change-Id: Iaf98dafec55f171b5968c2a8248290284bf30922 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593939 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use only contig CBCsAlex Waterman2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the LTC code to only use a contiguous CompBit Cache (CBC). The original code had two allocation schemes: "physical" and "virtual" - what they meant was virtually contiguous or physically contiguous. The CBC must appear contiguous to the GPU be it either from the IOMMU or from physical pages allocated contiguously. This change makes the CBC get allocated with the FORCE_CONTIGUOUS flag if the GPU is not IOMMU'able. If we can get contiguous mem with the IOMMU then no need to force the underlying pages to be contiguous. However, not all GPUs may be IOMMU'able so we do need to handle that case. Also delete the gk20a/ltc_gk20a.[ch] code. All that remained in these files was the CBC alloc functions which were completely chip agnostic. As a result these functions were consolidated and moved to common/ltc.c. Bug 2015747 Change-Id: I3f41961b4f94378b954e7502a6b27cf0bc627375 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593666 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Hard code regops max batch sizeTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | | | | | We set the regops limit in common code to a hard coded value and access it in Linux code. Change the responsibility so that regops limit is set in Linux code in the GPU characteristics query to a hard coded value and just use the same hard coded value in the IOCTL limit check. JIRA NVGPU-259 Change-Id: I2f78a7ea8f1cb68a08633a2dc74b71b3b001e5c9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Request CONTIG allocs for large PDsAlex Waterman2017-11-08
| | | | | | | | | | | | | | | | | | | | Request explicitly contiguous DMA memory for large page directory allocations. Large in this case means greater than PAGE_SIZE. This is necessary if the GPU's DMA allocator is set to, by default, allocate discontiguous memory. Bug 2015747 Change-Id: I3afe9c2990522058f6aa45f28030bc82a369ca69 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593093 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define runlist level in common codeDeepak Nibade2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux specific uapi header and used in common code But since common code should be linux-independent, move these uses out of common code Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code and use them wherever required Add new API nvgpu_get_common_runlist_level() to get common runlist level of the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_* Jira NVGPU-259 Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594327 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for legacy mappingSami Kiminki2017-11-08
| | | | | | | | | | | | | | | | | | | | Make NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL mandatory for all map IOCTLs. We'll clean up the legacy kernel code in subsequent patches. Remove support for NVGPU_AS_IOCTL_MAP_BUFFER. It has been superseded by NVGPU_AS_IOCTL_MAP_BUFFER_EX. Remove legacy definitions to nvgpu_map_buffer_args and the related flags, and update the in-kernel map calls accordingly by switching to the newer definitions. Bug 1902982 Change-Id: Ie9a7f02b8d5d0ec7c3722c4481afab6d39b4fbd0 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560932 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of linux specific powergate_mode flagDeepak Nibade2017-11-08
| | | | | | | | | | | | | | | | | | | | | In dbg_set_powergate(), we use flags NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE/ENABLE which are defined in linux specific uapi header Hence we need to remove those flags from common code Update dbg_set_powergate() to receive boolean flag to disable/enable powergate instead of NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE/ENABLE Also update corresponding HALs as per above change Jira NVGPU-259 Change-Id: I9c4eb30e29ea5ce0d8e25517a6a072fb9f0e92e5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable pbus intr for si/fpgaSeema Khowala2017-11-08
| | | | | | | | | | | | | | | | | Enable pri squash, fecs err and pri_timeout pbus interrupt for si and fpga platforms only. Bug 200350539 Change-Id: Id452edf92eac0209d3b43d98b3ff6efd0764e40a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569590 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: spew err for pbus interruptSeema Khowala2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | Spew err message for pri_squash, fecserr and pri_timeout pbus interrupts. If FECS_TGT is set in timeout_save_0, addr, write fields are not reliable. Also timeout_save_1 is unreliable. For both squash and timeout should have correct data most of the time. Even for FECS_TGT, a timeout for a read should indicate the correct transaction as Host only supports one read at a time. It's mostly just writes to FECS that have potentially incorrect information. Bug 200246808 Bug 200350539 Change-Id: I8a992d924ff6c740a8dacecaaaf4ef257756d01d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1568860 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce queries for big page sizesTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | Introduce query functions for default big page size and available big page sizes. Move initialization of GPU characteristics big page sizes to the GPU characteristics query function. JIRA NVGPU-259 Change-Id: Ie66cc2fbfcd88205593056f8d5010ac2539c8bc2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593685 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Store VBIOS version in g->biosTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | Store VBIOS version in g->bios instead of GPU characteristics. This removes a few Linux dependencies from common code, because GPU characteristics is defined in Linux IOCTL header. JIRA NVGPU-259 Change-Id: I9aab3d37b7ca000edd59c92b8601a96ee288e2bb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593684 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: change prod value for pg slcgseshendra Gadagottu2017-11-07
| | | | | | | | | | | | | | | | SW WAR to fix graphics slcg hang issue by updating prod value for slcg gating register. Bug 200349133 Change-Id: Ia9b32f6cfe79393d3c7c23f7b6880df5fd627c8e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593076 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use is_enabled flags also in vgpuTerje Bergstrom2017-11-07
| | | | | | | | | | | | | | | | One vgpu file was not changed when all nvgpu flags were moved to use nvgpu_is_enabled(). JIRA NVGPU-259 Change-Id: Ie3964ed05ce5831cb2bd3cd51c07bb19a1f1d4d3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593688 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix type defs in dbg_gpu_gk20a.hTerje Bergstrom2017-11-07
| | | | | | | | | | | | | | | | | dbg_gpu_gk20a.h used implictly definitions that it did not forward declare or #include definitions for. Also regops_whitelist fields were unused. The type itself is not defined anywhere. Delete the fields. Change-Id: I4b002247c67a4ce4cb54810720b0bbc06381bf83 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: drop user callback support in CEKonsta Holtta2017-11-07
| | | | | | | | | | | | | | | | | | | | | | | Simplify the copyengine code by deleting support for the ce_event_callback feature that has never been used. Similarly, create a channel without the finish callback to get rid of that Linux dependency, and delete the finish callback function as it now serves no purpose. Delete also the submitted_seq_number and completed_seq_number fields that are only written to. Jira NVGPU-259 Change-Id: I02d15bdcb546f4dd8895a6bfb5130caf88a104e2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589320 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add elcg/blcg/slcg enabled checksDeepak Goyal2017-11-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Power features should be enabled only if s/w flags xxcg_enabled are set for corresponding features. These flags control whether feature should be kept disabled in the hardware or not. For disable case, register programming will happen for CG registers and they will be set to disabled. For ELPG, init command will be sent to PMU, but “ELPG_ALLOW” will not be sent to PMU. Also these flags can be modified using sysfs. These flags are noop if corresponding can_xxxg flags are set to flase. S/w flags can_xxxg tell the ability of platform to support a power feature and cannot be modified by syfs. Setting these flags to false will avoid any HW register write or init sequence for the power feature from executing. For ELPG, no commands will be sent to PMU. -g->elcg_enabled flag should not be modified here. It should be modified only by sysfs. This will be cleaned up in follow up implementation where debug session will have some kind of lock where it will keep power features disabled as long as it wants to. Debugger cannot rely on this flag to keep power management disabled as these flags can be changed from sysfs. Due to this issue someone can easily break debugging session by accidentally changing something in sysfs. Proper fix for this is being tracked in NVGPU-320 Bug 1982434 Change-Id: I660ef02491f4df9910bf4dea3561ac8a0838e1b1 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587205 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix missing #includes and fw decls in Linux codeTerje Bergstrom2017-11-06
| | | | | | | | | | | | | ioctl_channel.h and cde.h referred to multiple structures that were not forward declared or explitly #included in. Add several forward declarations and #includes. Also add #include for <uapi/linux/nvgpu.h> to multiple Linux .c files that were missing it. Change-Id: Iefd52e71224d5810b5abbcc765f92bc535d7a28b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591634 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add RMOS include path for rwsem.hSourab Gupta2017-11-06
| | | | | | | | | | | | | | | | The patch adds include path for rmos header file pertaining to rwsem.h Change-Id: I7f9cfac38e971e1d78e76968911df72669598b9d Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591108 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use common destructor for boardobjgrpThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | | | | | Use boardobjgrp_super for boardobj_e255 and boardobj_32. In both cases, we want the destructor to remove and destroy related objects, as well as freeing any pmucmd buffer. JIRA EVLR-1959 Bug 200352099 Change-Id: I220d2d6b26347a36d73028db6740fcc2ef702987 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586597 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: call destructor for boardobj and boardobjgrpThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | Maintain a list of boardobj and boardobjgrp, so that we can free related objects when removing pmu support. A flag is added in boardobj so that the destructor can determine if it should free the object. This 'allocated' flag is false when the object is embedded into another structure, which should be freed through other means. JIRA EVLR-1959 Bug 200352099 Change-Id: I6a3ff3c57f7428dd145deacf98f2992a9be9796d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586596 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix dma memory leak in remove pmu supportThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | | Add missing unmap and free for seq_buf and ucode (acr & hsbl). JIRA EVLR-1959 Bug 200352009 Change-Id: I3e422ce07228b59554ab1407c29e45c70479134d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586576 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix kernel memory leak in pmu remove supportThomas Fleury2017-11-06
| | | | | | | | | | | | | | | When unbinding the driver, secure pmu firmware was not freed in nvgpu_remove_pmu_support(). Free related firmware if previously allocated. JIRA EVLR-1959 Bug 200352099 Change-Id: If9e431964837b3233ec25931b2ab61da920e5540 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582909 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g cross reference in boardobjgrpThomas Fleury2017-11-06
| | | | | | | | | | | | | | Added a pointer to GPU context in boardobjgrp, and updated constructors. It will be useful to free allocated DMA resources. JIRA EVLR-1959 Bug 200352099 Change-Id: I006e4f970c9a2525dabdfd6ad417be64e36b7b68 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586551 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support tuning per-ch deterministic optsKonsta Holtta2017-11-06
| | | | | | | | | | | | | | | | Add a new ioctl NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS to adjust deterministic options on a per-channel basis. Currently, the only supported option is to relax the no-railgating requirement on open deterministic channels. This also disallows submits on such channels, until the railgate option is reset. Bug 200327089 Change-Id: If4f0f51fd1d40ad7407d13638150d7402479aff0 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1554563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define EVENT_IDs in common codeDeepak Nibade2017-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All the event ids NVGPU_IOCTL_CHANNEL_EVENT_ID_* are defined in linux specific user header uapi/linux/nvgpu.h and can't be used in common code Hence add new definitions of type NVGPU_EVENT_ID_* for all the events in common code and use them wherever required in common code For future additions to event ids, we need to update both NVGPU_IOCTL_CHANNEL_EVENT_ID_* and NVGPU_EVENT_ID_* fields Also add new API nvgpu_event_id_to_ioctl_channel_event_id() to convert common event_id of the form NVGPU_EVENT_ID_* to Linux specific event_id of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_* Use this API in gk20a_channel/tsg_event_id_post_event() to get correct event_id Jira NVGPU-259 Change-Id: I15a7f41181fdbb8f1876f88bbcd044447d88325f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591434 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect stacktrace.h include with configDeepak Nibade2017-11-06
| | | | | | | | | | | | | | | | struct stack_trace is protected with config GK20A_CHANNEL_REFCOUNT_TRACKING and hence protect linux/stacktrace.h header include in gk20a/channel_gk20a.h with same config Jira NVGPU-259 Change-Id: I365a4faa7eb071dd559e9b27fe03377dede7484d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1592603 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix license in platform_gk20a.hDeepak Nibade2017-11-06
| | | | | | | | | | | | | | | | Since platform_gk20a.h is now in linux specific code, update it to use GPL license NVGPU-316 Change-Id: Iaee5cb306b36e10c0f1b674dfecc0d9a02bc2a2b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591433 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_udelay and optimize do while loopSeema Khowala2017-11-06
| | | | | | | | | | | | | | | | | - For interrupt context, use nvgpu_udelay() instead of nvgpu_usleep_range() - Use while loop instead of do while loop for polling as this will help minimize overall delay Bug 200350539 Change-Id: Icc05911082877df7f9e807da8f16e4d54e620cd8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1573303 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Put #includes in vgpu.h behind #ifdefTerje Bergstrom2017-11-06
| | | | | | | | | | | | | JIRA NVGPU-259 Change-Id: I6d88f652d24ff6cf418b5f3680ace733309a6fea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590126 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use a callback to free struct gk20aTerje Bergstrom2017-11-06
| | | | | | | | | | | | | | | | | struct gk20a is now part of nvgpu_os_linux in Linux builds. gk20a.c still frees struct gk20a by kfree(struct gk20a *), which is wrong. Create a new function pointer in struct gk20a for freeing the structure and call kfree(struct nvgpu_os_linux *) instead. JIRA NVGPU-259 Change-Id: I412ee993002cb2a42f0db015fc676de43418ec2f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591012 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return error code properly from nvgpu_vm_map_linuxSami Kiminki2017-11-03
| | | | | | | | | | | | | | | | | The function nvgpu_vm_map_linux() used to return GPU VA on successful map or 0 when things didn't go smoothly. However, this scheme does not propagate the actual map error back to the userspace. So, modify the function a bit: return error and return the GPU VA via pointer on success. Bug 1705731 Change-Id: I2174b5fbaf64dcb00f9567dab1c583d6ddfa5d78 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590961 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix patch buf count update for vidmem"Timo Alho2017-11-03
| | | | | | | | | | | | | | This reverts commit de399ccb0019513a5f9e8f2bcadb02486f99bc80. Bug 2012077 Change-Id: Ie608c3b41aa91f9aaed3fad240ed882a0c6f1ea2 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591423 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix patch buf count update for vidmemPeter Daifuku2017-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gr_gk20a_ctx_patch_write_begin() updates the patch buffer data_count when the associated graphics context memory buffer has been CPU-mapped; it was doing so by looking for a non-null cpu_va. However, if the graphics context has been allocated from vidmem, cpu_va is always 0, so we can't tell if nvgpu_mem_begin() was called for the context buffer or not. Instead: - add a cpu_accessible flag to the nvgpu_mem struct and set it in nvgpu_mem_begin() - return the value of that flag in nvgpu_mem_cpu_accessible() - gr_gk20a_ctx_patch_write_begin() now calls this new function instead of checking cpu_va. Bug 2012077 JIRA ESRM-74 Change-Id: I8401699f30b4ae7154111721c25c7ec3ff95d329 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587293 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: fix reserve mempool err checkingAparna Das2017-11-02
| | | | | | | | | | Bug 2016793 Change-Id: I3fe91b5c31d96bfc460624e8c4054945bee25383 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590373 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_is_enabled() for ASPMTerje Bergstrom2017-11-02
| | | | | | | | | | | | | | | | Convert disable_aspm and references to that field to use nvgpu_is_enabled(NVGPU_SUPPORT_ASPM). Initialize it from gk20a_platform struct at probe time. This removes another dependency to struct gk20a_platform. JIRA NVGPU-259 Change-Id: I32e30160f817ea275aa190dcf86c5fd594138d75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590124 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move platform_gk20a.h to linuxDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | Move gk20a/platform_gk20a.h to linux specific directory as common/linux/platform_gk20a.h since this file includes all linux specific stuff Fix #includes in all the files to include this file with correct path Remove #include of this file where it is no more needed Fix gk20a_init_sim_support() to receive struct gk20a as parameter instead of receiving linux specific struct platform_device NVGPU-316 Change-Id: I5ec08e776b753af4d39d11c11f6f068be2ac236f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589938 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 08:23:30 -0500