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* gpu: nvgpu: use nvgpu list for CDE contextsDeepak Nibade2017-04-03
| | | | | | | | | | | | | | | | Use nvgpu list APIs instead of linux list APIs to store CDE contexts in free_contexts/used_contexts lists Jira NVGPU-13 Change-Id: If1c5d8d8ca70afc90379b33232ceccf9ac4fb155 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1454009 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add nvgpu_list_move APIDeepak Nibade2017-04-03
| | | | | | | | | | | | | | Add new API to remove a node from one list and to add it to another head Jira NVGPU-13 Change-Id: I1c86cde1cdfea35bd554f175b9d270a7fd4b40e5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1454008 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu list for page chunksDeepak Nibade2017-04-03
| | | | | | | | | | | | | | | | Use nvgpu list APIs instead of linux list APIs to store chunks of page allocator Jira NVGPU-13 Change-Id: I63375fc2df683e018c48a90b76eca368438cc32f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1326814 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Split as code to as IOCTL and commonTerje Bergstrom2017-04-02
| | | | | | | | | | | | | | | | | | Split as_gk20a.c into two parts: common/linux/ioctl_as.c deals with as related devnodes and ioctls. This file contains all the Linux specific parts of as_gk20a.c. common/as.c deals with general as_gk20a maintenance and is Linux independent. JIRA NVGPU-16 Change-Id: I2d8541e0bd6ce159dc6e4de8e819dfcff0fa8f80 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1330803 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move ctrl IOCTL creation to Linux moduleTerje Bergstrom2017-04-02
| | | | | | | | | | | | Move all code related to ctrl devnode to under Linux module. JIRA NVGPU-16 Change-Id: I834b46ec4172076d7bde459168f1e6bc8c5d6c0c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1330802 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move devnode creation to Linux moduleTerje Bergstrom2017-04-02
| | | | | | | | | | | | Move Linux specific code to create devnodes to Linux module. JIRA NVGPU-16 Change-Id: I7f8f74d72f16857973da029b9f949ee8b553eb59 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1330801 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Split out pramin codeAlex Waterman2017-03-31
| | | | | | | | | | | | | Split out the pramin interface code in preparation for splitting out the mem_desc code. JIRA NVGPU-12 Change-Id: I3f03447ea213cc15669b0934fa706e7cb22599b7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323323 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use new List APIs to free channelsDeepak Nibade2017-03-31
| | | | | | | | | | | | | | | | | Use new APIs from <nvgpu/list.h> to access free channel list Define channel_gk20a_from_free_chs() to convert a list node to struct channel_gk20a Jira NVGPU-13 Change-Id: Idaf58f04be1c7fc553bea7c8de45951bf82bb340 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1303025 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: implement own list APIsDeepak Nibade2017-03-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nvgpu's own implementation of List APIs This implementation is needed to remove nvgpu's dependency on Linux specific list implementation Define a list node as struct nvgpu_list_node *node; Define below common APIs: nvgpu_init_list_node() - initialize list node nvgpu_list_add() - add new node to list nvgpu_list_add_tail() - add new node to end of list nvgpu_list_del() - delete node from list nvgpu_list_empty() - check if list is empty Define below macros to simplify access to list: nvgpu_list_entry() - convert list node to parent nvgpu_list_next_entry() - find next entry in list nvgpu_list_first_entry() - first entry in list nvgpu_list_for_each_entry() - iterator for list nvgpu_list_for_each_entry_safe() - deletion safe iterator Jira NVGPU-13 Change-Id: Icb1d27857148e96b2c6dfa3c2bd50fcff9f896cf Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1303024 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Sami Kiminki <skiminki@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: function to combine two u32 into u64Seema Khowala2017-03-30
| | | | | | | | | | | | | New function to combine two u32 values into one u64. This is introduced for t19x mmu fault handling. JIRA GPUT19X-7 Change-Id: I4cd1e5764c07f43fe96e487acfa781b6ebb7c57f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315951 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: ngpu: add fb ops for hub isrSeema Khowala2017-03-30
| | | | | | | | | | | | If supported, detect and handle hub interrupt JIRA GPUT19X-7 Change-Id: I431c92160636afb2bc94ff2677614023de595681 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in pstate.cDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in pstate.c - add new callback gk20a_deinit_pstate_support() to deinitialize pstate support - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I206bf2324e8fe95f4ed52c29ac5d8981327632b2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321296 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in mclk codeDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_mclk.c - declare new callback g->ops.pmu.mclk_deinit() to deinitialize mclk mutexes - and define this callback for gp106 - add corresponding nvgpu_mutex_destroy calls in deinitialization Jira NVGPU-13 Change-Id: I1491c084d330ac9756c9520477e6fe494560e651 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321294 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in clk codeDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_gk20a.c/clk_gm20b.c/clk_gp106.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: If6ddc2c924e1ab13274b857f904859033722479a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321293 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in sched_gk20a.cDeepak Nibade2017-03-30
| | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in sched_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I49013851e3f271b059a7b46d63816d8d385b48de Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321292 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in pmu_gk20a.cDeepak Nibade2017-03-30
| | | | | | | | | | | | | - check return value of nvgpu_mutex_init in pmu_gk20a.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: I646876d9c03be82b46db4733e3ecbd5135ab7798 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321291 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (misc)Alex Waterman2017-03-30
| | | | | | | | | | | | | | | | | | | | | Use the new kmem API functions in misc gk20a code. Some additional modifications were also made: o Add a struct gk20a pointer to gk20a_fence to enable proper kmem free usage. o Add gk20a pointer to alloc_session() in dbg_gpu_gk20a.c to use kmem API for allocating a session. o Plumb a gk20a pointer through the fence creation and deletion. o Use statically allocated buffers for names in file creation. Bug 1799159 Bug 1823380 Change-Id: I3678080e3ffa1f9bcf6934e3f4819a1bc531689b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318323 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (gk20a mm)Alex Waterman2017-03-30
| | | | | | | | | | | | | | | | | | | | Use the new kmem API functions in gk20a's mm code. Add a struct gk20a pointer to the dmabuf priv struct so that the cleanup function has access to the gk20a struct. Also add a gk20a pointer to some of the sg table functions so that they can use the nvgpu kmem APIs. Bug 1799159 Bug 1823380 Change-Id: I85a307c6bf862627c5b1af0e077283b48d78fa72 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318321 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (gk20a core)Alex Waterman2017-03-29
| | | | | | | | | | | | | | | Use the new kmem API functions in core gk20a code. Also add a struct gk20a pointer to several functions to ensure that the kmem APIs can be used. Bug 1799159 Bug 1823380 Change-Id: I41276509c4f0b68e80b989aa55cf94d8dbbdf156 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318322 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove direct HW access from ctrl_gk20a.cTerje Bergstrom2017-03-29
| | | | | | | | | | | | | | | | | ctrl_gk20a.c had some direct accesses to hardware. These violate the HAL rules, because we don't have per-GPU ctrl, and thus the code cannot be made GPU independent. Move all GR accesses to new GR HALs and use existing bus HAL for accessing timer. Remove #includes of all hardware headers. JIRA NVGPU-28 Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1327001 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of host registers to fifoTerje Bergstrom2017-03-28
| | | | | | | | | | | | | | | | | | | Move code that touches host registers and instance block to fifo HAL. This involves adding HAL ops for the fifo HAL functions that get called from outside fifo. This clears responsibility of channel by leaving it only managing channels in software and push buffers. channel had member ramfc defined, but it was not used, to remove it. pbdma_acquire_val consisted both of channel logic and hardware programming. The channel logic was moved to the caller and only hardware programming was moved. Change-Id: Id005787f6cc91276b767e8e86325caf966913de9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1322423 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove unnecessary use of dev_name()Terje Bergstrom2017-03-28
| | | | | | | | | | | | | | | Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1328534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: avoid false job timeout messageKonsta Holtta2017-03-28
| | | | | | | | | | | | | | | | | | The nvgpu timer API prints a message when the timer expires, but expiration of that does not necessarily mean here that the job has actually timed out, which is tested by comparing gp_get. Change the expiration check to just peek instead of the default which prints to log on expiration. Bug 1887569 Jira NVGPU-21 Change-Id: Ifde34cff701eaed2f3ea727dba3ec8affeef26b9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1329731 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: mark bios structures as packedVijayakumar2017-03-28
| | | | | | | | | | | | | | | volt and therm bios structures are not marked packed. In VBIOS they are packed, so trying to read them as unpacked causes mismatches. Mark the structures packed to fix the mismatches. JIRA DNVGPU-221 Change-Id: I0e24cc34e2b206fa90982305dcfa390a2452ea8f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1329124 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add and reorg reset_enable_hw fifo opsSeema Khowala2017-03-28
| | | | | | | | | | | | | | | | fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts after all the required configuration such as configuring timeouts, enabling timeout detections are taken care of. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: Id780cc11d858db18f8d748c037954ede73298506 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325351 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (gm20b/*)Alex Waterman2017-03-28
| | | | | | | | | | | | | | | | | | | | | Use the new kmem API functions in gm20b/*. Also add a struct gk20a pointer to lsfm_free_ucode_img_res() lsfm_free_nonpmu_ucode_img_res() so nvgpu_kfree() works. Bug 1799159 Bug 1823380 Change-Id: I3373600455553710adb14e0fb5743bf197095a03 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318320 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (gp106/*)Alex Waterman2017-03-28
| | | | | | | | | | | | | | | | | | | | | Use the new kmem API functions in gp106/*. Update lsfm_free_ucode_img_res() lsfm_free_nonpmu_ucode_img_res() to take a struct gk20a pointer so that the free can be done with nvgpu_kfree(). Bug 1799159 Bug 1823380 Change-Id: I101f5b87db6cfc7c47d88c8fb158e21947502e3a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318319 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (vgpu/*)Alex Waterman2017-03-28
| | | | | | | | | | | | | | | Use the new kmem API functions in vgpu/*. Also reshuffle the order of some allocs in the vgpu init code to allow usage of the nvgpu kmem APIs. Bug 1799159 Bug 1823380 Change-Id: I6c6dcff03b406a260dffbf89a59b368d31a4cb2c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318318 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NO_KERNEL_MAPPING for alloc_map_vidKonsta Holtta2017-03-27
| | | | | | | | | | | | | | | | | | Commit 8f3875393e7a6bd0fc03afdb1fa99b7e33b71576 ("abstract away dma alloc attrs") added an implicit NVGPU_DMA_NO_KERNEL_MAPPING for the function that allocates vidmem buffers, but the functions gk20a_gmmu_alloc_map_vid and gk20a_gmmu_alloc_map got overlooked and use no flags which now triggers a warning. Make those cases alloc the vidmem buffer with the no kernel mapping flag as it should have been, because kernel mappings of vidmem are not supported. Bug 1853519 Change-Id: I9f29c9d310f97c9bd5f279674decf61efb3e75ea Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1328953 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_timeout for all loopsTerje Bergstrom2017-03-27
| | | | | | | | | | | | | | | | | | | | There were still a few remaining loops where we did not use nvgpu_timeout and required Tegra specific functions for detecting if timeout should be skipped. Replace all of them with nvgpu_timeout and remove including chip-id.h where possible. FE power mode timeout loop also used wrong delay value. It always waited for the whole max timeout instead of looping with smaller increments. If SEC2 ACR boot fails to halt, we should not try to check ACR result from mailbox. Add an early return for that case. JIRA NVGPU-16 Change-Id: I9f0984250d7d01785755338e39822e6631dcaa5a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323227
* gpu: nvgpu: delete unused #includes missing in 4.9Konsta Holtta2017-03-27
| | | | | | | | | | | | | Drop old unnecessary references to clock and edp. These headers are not in kernel-4.9 (yet?). Add proper #ifdefs for #including soctherm. Bug 1853519 Change-Id: I28e829f78df356e5efcffd9bd985fd736e76d2c0 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1327659 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add INA3221 I2C info in platform dataThomas Fleury2017-03-27
| | | | | | | | | | | | Add I2C device index and address for INA3221 in platform data. Jira EVLR-1048 Change-Id: I3791f24bd6d8ab99483ea0103313b2b671dfb445 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1327047 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove MC accesses from gk20a.cTerje Bergstrom2017-03-26
| | | | | | | | | | | | | | | Clean up gk20a.c by removing direct accesses to MC and moving the accesses to happen via MC HAL. The chip detection logic has to violate the HAL and call gk20a version directly, because HAL ops cannot be set up before chip has been identified. Change-Id: I4cdd0ef3fcf7d3b561a3fca4247a8356fe8d18e1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1321576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (boardobj/*)Alex Waterman2017-03-26
| | | | | | | | | | | | | | | | | Use the new kmem API functions in boardobj/*. Add a struct gk20a pointer to the boardobj struct to provide the necessary gk20a pointer for freeing the boardobj. Bug 1799159 Bug 1823380 Change-Id: I62d93681bed2671f19435ad64343a44791a1d766 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318317 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (clk/*)Alex Waterman2017-03-26
| | | | | | | | | | | | | | | | | | | Use the new kmem API functions in clk/*. Also add a struct gk20a pointer to the following functions: nvgpu_clk_notification_queue_alloc() nvgpu_clk_notification_queue_free() Bug 1799159 Bug 1823380 Change-Id: I7eb67dc443c0bbe0d3f67dac7bf363da60e1051c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318316 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (common/*)Alex Waterman2017-03-26
| | | | | | | | | | | | | | | | | Use the new kmem API functions in common/* and common/mm/*. Add a struct gk20a pointer to struct nvgpu_allocator in order to store the gk20a pointer used for allocating memory. Bug 1799159 Bug 1823380 Change-Id: I881ea9545e8a8f0b75d77a1e35dd1812e0bb654e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318315 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: refactor teardown to support unbindDavid Nieto2017-03-25
| | | | | | | | | | | | | | | | | | | | | | | | This change refactors the teardown in remove to ensure that it is possible to unload the driver while leaving fds open. This is achieved by making sure that the SW state is kept alive till all fds are closed and by checking that subsequent calls to ioctls after the teardown fail. Normally, this would be achieved ny calls into gk20a_busy(), but in kickoff we dont call into that to reduce latency, so we need to check the driver status directly, and also in some of the functions as we need to make sure the ioctl does not dereference the device or platform struct bug 200277762 JIRA: EVLR-1023 Change-Id: I163e47a08c29d4d5b3ab79f0eb531ef234f40bde Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1320219 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: fix vbios mem table parsingVijayakumar2017-03-24
| | | | | | | | | | | | | | | | bios tables are packed data structures. keeping packed structrues inside union and assigning values from it does not work. bug 200287822 Change-Id: I1df9541495b96786412533570c51d779bfd0f43f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1326798 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable CE alwaysTerje Bergstrom2017-03-24
| | | | | | | | | | | | | All GPUs have a copy engine. So delete the flag has_ce, because it's always true. JIRA NVGPU-16 Change-Id: I89db74c7cf66b24db84301b79832862ef28100b9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1325355 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: profiler reservation supportPeter Daifuku2017-03-24
| | | | | | | | | | | | | | | | | | | | | | | Support for hwpm reservations in the virtual case: - Add session ops for checking and setting global and context reservations, and releasing reservations - in the native case, these just update reservation counts and flags - in the vgpu case, when the reservation count is 0, check with the RM server that a reservation is possible: for global reservations, no other guest can have a reservation; for context reservations, no other guest can have a global reservation - in the vgpu case, when the reservation count is decremented to 0, notify the RM server that the guest no longer has any reservations Bug 1775465 JIRA VFND-3428 Change-Id: Idf115b730e465e35d0745c96a8f8ab6b645c7cae Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1323375 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update PMU version.Deepak Goyal2017-03-24
| | | | | | | | | | | JIRA GPUT19X-30 Change-Id: I1153cea6389fbf18a3cd43ab13a2d5de4083cc42 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1302672 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: pass gk20a struct to gk20a_busyDavid Nieto2017-03-24
| | | | | | | | | | | | | | | | | After driver remove, the device structure passed in gk20a_busy can be invalid. To solve this the prototype of the function is modified to pass the gk20a struct instead of the device pointer. bug 200277762 JIRA: EVLR-1023 Change-Id: I08eb74bd3578834d45115098ed9936ebbb436fdf Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1320194 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: remove duplicated busy in debuggerDavid Nieto2017-03-24
| | | | | | | | | | | | | | | | | | | On the past, we had separate calls for platform and channel busy, but those got removed. The result is that in the debugger code we have essentially a double busy call int the powergating enable/disable. This change removes it bug 200277762 JIRA: EVLR-1023 Change-Id: Iba70b81700f27b847e1d0222fb69ed1a7a883342 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1323220 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix running condition on fifo isrDavid Nieto2017-03-23
| | | | | | | | | | | | | | | | The fifo interrupt path was reading the PBDMA interrupt status after clearing interrupts and this could lead to a situation in which the host may have advanced to another channel, leading to the recovery code resetting the wrong channel. Bug 200278729 JIRA: EVLR-1036 Change-Id: I392423d1eaa8d23acf88454bf113c015e649e13d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1326461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: *ERROR_MMU_ERR_FLT* not set for fake mmu faultsSeema Khowala2017-03-23
| | | | | | | | | | | | | For fake faults, errror notifiers are expected to be set before triggering fake mmu fault. JIRA GPUT19X-7 Change-Id: I458af8d95c5960f20693b6923e1990fe3aa59857 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1323413 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: null check for fault_chSeema Khowala2017-03-23
| | | | | | | | | | | | | gk20a_gr_get_channel_from_ctx() could return NULL as a result fault_ch could be null JIRA GPUT19X-7 Change-Id: I2c8f099f63f30e576ecd221e3bec25070b026ced Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1323252 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add function to enable/disable runlists schedSeema Khowala2017-03-23
| | | | | | | | | | | | | | | -gk20a_fifo_set_runlist_state() can be used to enable/disable runlists scheduler. This change would be needed for t19x fifo recovery too -Also delete gk20a_fifo_disable_all_engine_activity function as it is not used anywhere. JIRA GPUT19X-7 Change-Id: I6bb9a7574a473327f0e47060f32d52cd90551c6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315180 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr faults: do not depend on fake mmu fault notifierSeema Khowala2017-03-23
| | | | | | | | | | | | | | | | | | | | Currently NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT is being set in error notifier for non mmu fault too. For fake mmu faults i.e. trigger mmu fault cases, make sure proper notifiers are set and driver is not depending on sending mmu error fault notifier. This change is needed for t19x fifo recovery too. NVGPU_CHANNEL_GR_ERROR_SW_METHOD (12), NVGPU_CHANNEL_GR_EXCEPTION(13) and NVGPU_CHANNEL_FECS_ERR_UNIMP_FIRMWARE_METHOD (37) are new error notifiers. JIRA GPUT19X-7 Change-Id: Idee83e842c835bdba9eb18578aad0c372ea74c5d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add init_pbdma_intr_desc fifo opsSeema Khowala2017-03-23
| | | | | | | | | | | | | | | | | | | | | | Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks for each GPU version separately pbdma_intr_0 field differences for each GPU version:- -gk20a : bit 28 does not exists in hw -gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw -gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28, (syncpoint_illegal) added in hw but is not being handled. -gk20a/gm20b/gp10b bit 24 eng_reset and bit 25 semaphore always existed in hw but never handled JIRA GPUT19X-47 Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325402 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:54:19 -0500