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* gpu: nvgpu: FE object table has 4 elementsTerje Bergstrom2015-03-18
| | | | | | | | | Restrict reading of FE object table to the number of entries available. Change-Id: I11275ecd14e53f0b763d00d65042adb4b1e8ae6f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/449306
* gpu: nvgpu: Use polling to detect runlist switchTerje Bergstrom2015-03-18
| | | | | | | | | | | Runlist event is not sent in gm20b for updated runlist. Polling is the preferred way also for gk20a. Bug 1555239 Change-Id: I60de084db69f848f63451f1f3078f183ca51ba50 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500241
* gpu: nvgpu: implement poll() for semaphoresKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | | Add poll interface and control ioctls for waiting for GPU job completion via semaphores. Poll on a gk20a channel file waits for events from pending semaphore interrupts (stalling) of that channel. New ioctls enable and disable the events, and clear a single interrupt event so that next poll doesn't wake up for it again. Bug 1528781 Change-Id: I5c6238966b5d0900c8ab263c6a7f8f2611901f33 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/497750 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ioctl support flags in gpu characteristicsKonsta Holtta2015-03-18
| | | | | | | | | | | | | | Expose supported nvgpu ioctls to userspace via bits in the flags field of nvhost_gpu_characteristics; currently define two bits for special memory allocation support. Bug 1539747 Change-Id: I1bc9333b12825d07a00b7a4136ae9d35816a5855 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/495942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow skipping regops addr validationTerje Bergstrom2015-03-18
| | | | | | | | | | | If allow_all is set, skip regops address validation. Change-Id: I42d6c9f1a5d2c8d9bc6783adff5f6048c45350f6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/499221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Fix L2 bypass to work in gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | L2 bypass registers have moved in gm20b. Move the code to ltc_common.c, which gets compiled once per chip version. Change-Id: I0ab4dd03c78b8ad8abc7a7b18c094b6002827587 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/499220 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Add GM20B GPCPLL h/w definitionsAlex Frid2015-03-18
| | | | | | | | | | | | | Expanded GM20B GPCPLL definitions of DVFS registers. Bug 1450787 Change-Id: I51d049be70badfedd8c451019b10770b4fb31e80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499487 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gm20b: enable elpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: Ief9cf648270412f7a9f6f5b28a1fce08effdd670 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499541 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable slcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Second Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I34a3d93a98f7b784ab26fb7940d50db262b35f57 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499540 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable elcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I6f0bc565700bfd183c703fc35389188906842a4e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499539 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable blcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Block Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: Ibdd611bc2932ae9c3ce2c0d9eb847fa46a3759c7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499538 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use TSG recover APIDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use TSG specific API gk20a_fifo_recover_tsg() in following cases : - IOCTL_CHANNEL_FORCE_RESET to force reset a channel in TSG, reset all the channels - handle pbdma intr while resetting in case of pbdma intr, if channel is part of TSG, recover entire TSG - TSG preempt failure when TSG preempt times out, use TSG recover API Use preempt_tsg() API to preempt if channel is part of TSG Add below two generic APIs which will take care of preempting/ recovering either of channel or TSG as required gk20a_fifo_preempt() gk20a_fifo_force_reset_ch() Bug 1470692 Change-Id: I8d46e252af79136be85a9a2accf8b51bd924ca8c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497875 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle MMU fault for TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | - add support to handle MMU faults on a channel in TSG - first get the ID and type of channel that engine is running - if TSG, abort each channel in it - if regular channel, abort that channel - also, add two versions of API set_ctx_mmu_error(), one for regular channel and another for TSG Bug 1470692 Change-Id: Ia7b01b81739598459702ed172180adb00e345eba Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497874 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add API to recover TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add and export API "gk20a_fifo_recover_tsg()" to recover a TSG - if TSG is running on any engine, then trigger MMU fault on those engines - otherwise, abort each channel in TSG - modify channel specific API engines_on_ch() to generic engines_on_id() which will take an ID and a flag to specify whether ID is for channel or TSG and return engines running on that ID - modify channel specific API get_faulty_channel() to generic get_faulty_id_type() which will take pointers to ID and type of ID (either a regular channel or TSG) - remove runlist update from recover_ch() since no need to touch runlist during recovery - set error notifier first and then only abort the channels for TSG recovery path - also, add necessary accessors to get engine status type as TSG Bug 1470692 Change-Id: I7137f611f80916b3d256d4b0dc6e5cf1e93eef6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Change GM20B post-divider in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Restored changing GM20B GPCPLL post-divider in flight with the following limitation: post divider transition is glitch-less only if there is common "1" in binary representation of old and new settings. Transitions that may create glitch are implemented in glitch-less steps with minimum possible interim divider value (for example, 1 <=> 2 transition has interim value 3: 1 <=> 3 <=> 2). Steps allowed for glitch-less transitions may not always have frequency jump at/below VCO min/2 (in the example above 1st step jumps 2/3 of VCOmin). Enabled external linear divider at 1:2 during such steps. Used extra write of the same data when changing GM20b linear divider. Bug 1552225 Change-Id: Ie8fba2fbe44afd34ca68f5f355bd302b7426a632 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/496319 (cherry picked from commit bdd21e0003032fe664bd20f163dbab9942fd1d1d) Reviewed-on: http://git-master/r/499193 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL bypass operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | - Skipped PLL re-locking if only post-divider is changing under bypass - Added 1us delay after switch to bypass clock source - Changed wait for lock under bypass resolution from 2us to 1us Change-Id: I259581c00c417752263ef3b2ea057200bb78ecbf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495473 (cherry picked from commit d90a19b8bf59c608a2a3a891b34ca714dfe990e9) Reviewed-on: http://git-master/r/499192 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* edp: sysedp : CPU/GPU priority depends on fGPUMatt Longnecker2015-03-18
| | | | | | | | | | | | | | | | Provide sysedp_dynamic_capping with the instantaneous GPU frequency when notifying it of the GPU load. Modify the gpu/cpu priority decision logic to choose CPU priority until GPU frequency gets "near" the CPU-priority-limited-GPU-fmax. Introduce the priority_bias debugfs parameter to facilitate tuning of "near". priority_bias takes a value from 0 to 100. Change-Id: Ia2cba36b8ea024fb8b01b5ba195dcf6550e38121 Signed-off-by: Matt Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/481720 GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/498912 Reviewed-by: Timo Alho <talho@nvidia.com>
* gpu: nvgpu: Support ZBC color trackingLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | The compression state tracking user space API already accepts and returns the ZBC color used for the surface. Actually store the color in kernel so that the feature works. Bug 1536227 Bug 1524301 Change-Id: I264e1eeb90f0c4d40fe35fc2479b0ce83e19a7d7 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/497476 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Defer CDE app initializationLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | | | Defer CDE app initialization to the point where we actually need to launch the app. This allows us to use the compression state API also on T124 where we never use the CDE app. Also return the error code correctly from gk20a_prepare_compressible_read. Bug 1524301 Change-Id: If79fbe161e8dc9353b9f5fa0dfcd7f30b00d29b4 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/497351 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check dma_buf_get retval with IS_ERRKonsta Holtta2015-03-18
| | | | | | | | | | | | | dma_buf_get returns PTR_ERRs, so fix checking for null to proper IS_ERR in gk20a_vm_map_buffer. Buffer mapping from user space with ioctls would also have paniced here if an improper handle would be passed. Change-Id: I245fe41cd209e49fc9265e56340c1c8215ffb1d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/498320 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: do not bind already active channels to TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | If a channel is already scheduled as regular channel, we should not allow it to be marked as TSG since it will fail book keeping of number of active channels in a TSG This way we can force to bind the channels first and then only make them active Also, remove duplicate function declaration added during branch merge and one unnecessary comparison with zero Bug 1470692 Change-Id: I88f9678919e4b76de472c6dda21e4537520241c4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497903 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable illegal compstat access intrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Disable illegal compstat access interrupt. We access compstat backing store to handle CDE swizzling. Also change the magic number for evicted_cb to use a generated value. Change-Id: I79b299abbffcb90497690ba4fc55d8517a3dbd87 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/496444 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com>
* gpu: nvgpu: gm20b: disable slcg fbSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | copy disable values in slcg fb to the prod column to avoid hang issues with SLCG enable. Bug 1550628 Change-Id: I941c6e625cda41bca8805033b5b2a0387eed4ab5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/496122 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add refcounting for TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | Add refcounting for TSGs and manage the refcounts as below : - initialize ref when TSG is opened - get ref when channel is bound to TSG - drop the ref when channel is unbound (i.e. during channel close) - drop the ref when TSG is closed - when refcount drops to zero, we free the TSG This refcounting makes it possible to close channels or TSG in any order Bug 1470692 Change-Id: Ia4b39164a4582c8169da62a91b9131094c67f5f8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/495667 (cherry picked from commit be1e198a663d2102e9674978f3d2cca0f2327a6b) Reviewed-on: http://git-master/r/495955 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix crash in gk20a_channel_releaseAingara Paramakuru2015-03-18
| | | | | | | | | | | | | | | gk20a_channel_release() should bail if filp->private_data is NULL. This can happen as a result of gk20a_channel_release() being called when __gk20a_channel_open() fails in NVHOST_IOCTL_CHANNEL_OPEN. Bug 200014898 Change-Id: I32cc957aca46fcd4265a8052ac5be355b644b9f7 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/496138 Reviewed-by: Ken Adams <kadams@nvidia.com> Tested-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: add ioctls for TSG enable/disableDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | Add ioctls to enable/disable/preempt a TSG 1. NVGPU_IOCTL_TSG_ENABLE enable all the channels in a TSG 2. NVGPU_IOCTL_TSG_DISABLE disable all the channels in a TSG 3. NVGPU_IOCTL_TSG_PREEMPT preempt a TSG with given id Bug 1514064 Change-Id: I2db6404b8536e872243cbe57b99e7c6d14243fa5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/494671 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add API to preempt TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | Add API gk20a_fifo_preempt_tsg() which takes ID of tsg and preempts it Bug 1514064 Bug 1470692 Change-Id: I1d52c1dd7a9aecc1314b0f223fe4eedecc033629 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/495583 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove gk20a_handleDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | Remove static variable gk20a_handle used to store pointer to struct gk20a Use below device tree APIs to get pointer to platform_device and then struct gk20a device_node = of_find_matching_node() platform_device = of_find_device_by_node(device_node) Also, use two versions of do_idle()/do_unidle() APIs - one will receive void (to be used from outside GPU driver) and another will receive platform_device (to be used within GPU driver where it is available) Change-Id: I9f2c7610646c5fbcd3d99a1b03dc0364201272a8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/496508 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gk20a: check ctx valid bitMayank Kaushik2015-03-18
| | | | | | | | | | | | | | | When determining the chid for the current context, first check the ctx valid bit. Bug 1485555 Change-Id: I6c3096d800a6cef38b656d525437a2c4f8b45774 Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/496140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Geoffrey Gerfin <ggerfin@nvidia.com> Tested-by: Geoffrey Gerfin <ggerfin@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Initialize ELPG ref-count early.Neil Gabriel2015-03-18
| | | | | | | | | | | | | | | | | | | gk20a_pmu_disable_elpg can be called before the PMU driver has received and processed the INIT message from the PMU. If change ensures that the ELPG ref-count has been initialized to zero before that can happen. Bug 200016313 Change-Id: Ic80ec1ee69b1eb0499effb1abf556f78cb041f5e Signed-off-by: Neil Gabriel <ngabriel@nvidia.com> Reviewed-on: http://git-master/r/429161 Reviewed-on: http://git-master/r/433299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Robert Shih <rshih@nvidia.com> Tested-by: Robert Shih <rshih@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use pgsz_idx instead of page_sizeTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Alloc space writes the page size to a field that requires pgsz_idx. That can cause corruption in internal kernel structures. Clear_sparse treated a parameter as page size instead of index. Bug 1549451 Change-Id: I73ce17b99aae6865056facce72d2ab9ca8b3f81d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/495692
* gpu: nvgpu: Bypass for GM20B post-divider changeAlex Frid2015-03-18
| | | | | | | | | | | Switch GM20b GPCPLL under bypass when changing post-divider setting (for now, don't assume that post-divider is glitch-less). Change-Id: I62b1285c035de0913207a86c41f37b7765da3893 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495300 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: get VM reference for TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | We store a reference to common address space of channels in struct tsg_gk20a without increasing the refcount This could result in freeing the address space even when some channel in TSG needs it or when we need to free common gr_ctx Fix this by getting ref using gk20a_vm_get() when we store the VM reference. We drop this reference with gk20a_vm_put() when closing the TSG Bug 1470692 Change-Id: Ifc1f29d32cd721810bfbb5a4db96095770318c17 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/495668 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add refcounting for TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | Add refcounting for TSGs and manage the refcounts as below : - initialize ref when TSG is opened - get ref when channel is bound to TSG - drop the ref when channel is unbound (i.e. during channel close) - drop the ref when TSG is closed - when refcount drops to zero, we free the TSG This refcounting makes it possible to close channels or TSG in any order Bug 1470692 Change-Id: Ia4b39164a4582c8169da62a91b9131094c67f5f8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/495667 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fixes in dupe freeSupriya2015-03-18
| | | | | | | | | | | | | gr_gk20a.c : railgating path the crash was seen with multiple frees happening acr_gm20b.c : failure path, kernel panic was seen, with multiple frees Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494161 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Support for falctraceSupriya2015-03-18
| | | | | | | | | | | | Adding support for falc_trace for ACR Change-Id: Iad638b0de72ff122f43f2250dce6a37adab4cecb Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494162 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpu: nvgpu: remove config GK20A_PHYS_PAGE_TABLESDeepak Nibade2015-03-18
| | | | | | | | | | | | | | remove config GK20A_PHYS_PAGE_TABLES since all code dependent on this config is now moved to runtime selection Change-Id: I27d2722a9ad91cf4e0537a30943675c9132d6924 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/494499 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Increase GM20b debug monitor cyclesAlex Frid2015-03-18
| | | | | | | | Change-Id: I913b6879e0d1ac89b740c1d088d639cc9b13b9b4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494200 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
* gpu: nvgpu: Add GM20b pll registers error dumpAlex Frid2015-03-18
| | | | | | | | Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Clear PTE ref after freeingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | When clearing sparse buffers, pte->ref must be cleared once the PTE is freed. Bug 1549451 Change-Id: Ie7d3e438ef2c43cbcf893709ae50a67823bf0c9c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494670 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Fix max comptag calculationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix order of calculation for max comptag line calculation. Bug 1549451 Change-Id: I13bf657f0f0b8aafa4d64dacacb74d7224fed379 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494657 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Fix and enable L2 error processingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix L2 error processing to look into interrupts in each L2 and slice. Enable L2 error interrupts. Bug 1549451 Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gm20b: Enable rail-gating with max delaySeshendra Gadagottu2015-03-18
| | | | | | | | | | | Enable gpu rail gating with INT_MAX delay. This will allow teams to experiment with different rail-gate entry delay. Change-Id: I8c696140aba2374c797365282999b6589432047c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/491615 GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpmu:nvgpu: Falcon debug prints.Vaikundanathan S2015-03-18
| | | | | | | | | | | | | | | Display the Falcon Trace prints in the right format. Embedd the parameters in the string instead of printing it separately. Bug NA Change-Id: Ia61fc43384cf6e44a867c7aa9cbb828127146099 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: http://git-master/r/488757 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: update regops whitelistKevin Huang2015-03-18
| | | | | | | | | | | Bug 1500195 Change-Id: Ie2253f2650844cbc707a3083cc2f6b5150c4a17b Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488508 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add HAL for regopsKevin Huang2015-03-18
| | | | | | | | | | | Bug 1500195 Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488507 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | Moved detection of idempotent GPCPLL operations from set_pll_freq() function to its callers, e.g., explicitly check when enable operation is called on already enabled PLL, instead of passing same frequency to set_pll_freq() in such case. Similarly explicitly check when disable operation is called on already disabled PLL. Also moved check for GPU powered on from set_pll_freq() to callers, and skip call to set interface if not. Added last GPCPLL configuration structure updated after successful completion of set_pll_freq() function. Bug 1450787 Change-Id: I8c14b8cab2a8548e98c9b2d223c465c68fb87b61 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Enable gm20b fecs/gpccs bootloaderTerje Bergstrom2015-03-18
| | | | | | | | | | Change-Id: Ia9ab5ef8fbe3244b44c911d8808123e0aaf860cf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/488611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: cde: Map backing store as read-onlyLauri Peltonen2015-03-18
| | | | | | | | | The cde shader will only read data from the global compbit backing store. Map it as read-only to enforce this. Change-Id: If5be44b8daedd5e7fdee650a6e76befa7bdecfd6 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/486679
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 20:06:29 -0500