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* gpu: nvgpu: Return correct GPC base addressesTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Due to missing break statements, GPC base and GPC shared base were overwritten by values in following select cases. Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249970 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: gp10b: define fuse macro depend on kernel versionShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | | | - Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4 Bug 200243956 Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245825 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add PMU thermal RPC for WARN_TEMPLakshmanan M2016-12-27
| | | | | | | | | | | | | | | Added PMU thermal slct RPC handling for WARN_TEMP threshold configuration. JIRA DNVGPU-130 Change-Id: Iac96557080907bd091217fe983d6a951d0be1da4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1242133 (cherry picked from commit 8bca85490e716b974315093c47d0d54ec5fb7e0f) Reviewed-on: http://git-master/r/1246213 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add thermal module supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | The following CL contains the following VBIOS thermal table parsing and PMU interface support. 1) Thermal device table 2) Thermal channel table JIRA DNVGPU-130 Change-Id: Ie3abab4bf099a022b1b59db96811c2ed44079519 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1240630 (cherry picked from commit 814962a4be0a8cd0cddc7bc5211c62308ab1fea2) Reviewed-on: http://git-master/r/1246210 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Add PMU HAL is_pmu_supportedTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Add implementation for PMU HAL is_pmu_supported to gp106. JIRA GV11B-21 Change-Id: If4268465ffade7c3c8e7bb853a1d2070c0e2ae4f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1246026 Tested-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: pmu HAL updateseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Update pmu HAL to have function for is_pmu_supported. JIRA GV11B-21 Change-Id: Id08efa82aa04a6f92c7fea0eb5d4735db2699b5a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243918 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sram rail volt calculationVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-120 SRAM rail voltage needs to be picked up from SRAM index of VF entries in CLK prog table. Change-Id: Iabfff62edeec5aa9c2ead62d6b943fb2ebb952ed Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1227665 (cherry picked from commit 8053260438bc94397b20e74cf18453624ebeb325) Reviewed-on: http://git-master/r/1244664 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update volt pwm source & raw periodMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - calculate raw period as per pwm source - update pwm source for logic & sram rails. JIRA DNVGPU-123 Change-Id: I50b41d51b6aba760710700522dced7859f815463 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227626 (cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4) Reviewed-on: http://git-master/r/1244663 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: construct/load tabels & set voltageMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | - Read voltage tables from VBIOS & construct then send to PMU. - compare & set voltage based on mclk/gpc2clk clk, take higher voltage between two & set. JIRA DNVGPU-122 Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1224365 (cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c) Reviewed-on: http://git-master/r/1244657 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add support for voltage configMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - changes to read voltage tables from VBIOS & create boardobj then send to pmu - Rail, Device & Policy objects are read from VBIOS & created boardobjs - RPC support to load, Set & get voltage. JIRA DNVGPU-122 Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1222774 (cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac) Reviewed-on: http://git-master/r/1244656 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: parse performance tableThomas Fleury2016-12-27
| | | | | | | | | | | | | | | Parse VBIOS performance table to retrieve clock ranges. Jira DNVGPU-125 Change-Id: Ia8e4ede158de5c5374205a510099d00b497fe1a6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1218935 (cherry picked from commit b5b7c789e98a20eb4cc5c30f0e2eb45d4a882cc4) Reviewed-on: http://git-master/r/1232593 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add SW_THRESHOLD policy supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | Added SW_THRESHOLD policy support for over power protection. JIRA DNVGPU-70 Change-Id: I7a9d202619c997d6cab6fb750db7f3018229b2fd Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1233055 (cherry picked from commit b233c74b9ba4a3802f111757aecf24a27c830fc1) Reviewed-on: http://git-master/r/1241960 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add pmgr supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | | This CL covers the following implementation, 1) Power Sensor Table parsing. 2) Power Topology Table parsing. 3) Add debugfs interface to get the current power(mW), current(mA) and voltage(uV) information from PMU. 4) Power Policy Table Parsing 5) Implement PMU boardobj interface for pmgr module. 6) Over current protection. JIRA DNVGPU-47 Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1217189 (cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6) Reviewed-on: http://git-master/r/1241953 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: add set_preemption_modeRichard Zhao2016-12-27
| | | | | | | | | | | | | Implement HAL callback set_preemption_mode Bug 200238497 JIRA VFND-2683 Change-Id: I8fca8e1ba112d8782ce18f0899eca38a1d12b512 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1236976 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Don't call already called functionSeema Khowala2016-12-27
| | | | | | | | | | | | | | gm20b_init_fb already calls gm20b_init_uncompressed_kind_map() and gm20b_init_kind_attr(). JIRA GV11B-8 Change-Id: Id72ee1ae04d3a47ae7a6a972f6d8bd7e7bda7389 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1234570 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create function to program coreclkVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-123 now a function can be called with GPC2CLK value It will take care calculating slave clock values and calling VF inject to program clock Made programming of boot clock code to use this newly created function. Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1221976 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235056
* gpu: nvgpu: add function to retrieve clk pointsVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 Function will copy possible clock points for a given master clock domain to pointer passed. pointer with NULL value and count of zero can be passed to query number of clock points for a given domain so that memory can be allocated and function called again to fill clock points Change-Id: Iec6206f23789980036be99793599e934bd221035 Reviewed-on: http://git-master/r/1218912 (cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9) Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1235055 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support to parse VF tableVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 function was added to retrieve V for F or F for V for a given clock domain. Clock domain can be master or slave. F or V can be intermediate point between two successive V or F values in VF table. VF table should be cached before calling this function. A F value below Fmin will return Vmin. F > Fmax will return error A V value above Vmax wil return F max. A V value below Vmin will return error. Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1211234 (cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa) Reviewed-on: http://git-master/r/1235054 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add support to cache VF table from PMUVijayakumar2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-118 Change-Id: I5c6a919d18e6de077e03180ba70441cfc9791350 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1209849 (cherry picked from commit 469f35e3f65964a3402f7e0c49862bd44b68936a) Reviewed-on: http://git-master/r/1233040 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: make commit_userd globalseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Make channel_gp10b_commit_userd global, so other gpus can re-use that function. JIRA GV11B-11 Change-Id: Ibe03063befc2da6c67822121f880a141cad46e84 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237738 GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: At FB reset wait for scrubberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | We need to wait for scrubber to have finished before we can allow any accesses to memory. Do the wait in place where on iGPU we would do FB reset. Bug 1799537 Bug 1815139 Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235541 (cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc) Reviewed-on: http://git-master/r/1239955 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix sparse warning in LTC codeDavid Nieto2016-12-27
| | | | | | | | | | | | bug 200088648 sparse warning reported that the function was not defined. This was due to a missing include Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1237845 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: parse and execute mclk shadow scriptDavid Nieto2016-12-27
| | | | | | | | | | | | | * Parsing of shadow registers from VBIOS * Partial devinit engine interpreter implementation JIRA DNVGPU-117 Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1214956 Reviewed-on: http://git-master/r/1237293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move ELCG programming to thermTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement gp10b and gp106 ELCG programming. JIRA DNVGPU-74 Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1220431 (cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f) Reviewed-on: http://git-master/r/1239422 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add accessors for invalid ctx_statusDeepak Nibade2016-12-27
| | | | | | | | | | | Bug 1826768 Change-Id: I8be2b9c074868206cb95b3bc84d66ea84683b19a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1237522 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Cory Perry <cperry@nvidia.com>
* gpu: nvgpu: implement PCIe Gen2 frequency swapAlex Waterman2016-12-27
| | | | | | | | | | | | | | | | | | | | Implement the basic code to swap between PCIe bus speeds for the GPU. Other GPUs are not supported yet. Currently the following speeds can be used: Gen1 (2.5 MTPS) Gen2 (5.0 MTPS) gp106 on DPX2 does not support Gen3. JIRA DNVGPU-89 Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499 Reviewed-on: http://git-master/r/1218177 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1227925 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: compact pte buffersKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | | The lowest page table level may hold very few entries for mappings of large pages, but a new page is allocated for each list of entries at the lowest level, wasting memory and performance. Compact these so that the new "allocation" of ptes is appended at the end of the previous allocation, if there is space. Bug 1736604 Change-Id: I4c7c4cad9019de202325750aee6034076e7e61c2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1222810 (cherry picked from commit 97303ecc946c17150496486a2f52bd481311dbf7) Reviewed-on: http://git-master/r/1234995 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: Add debugfs entry for temperature readingLakshmanan M2016-12-27
| | | | | | | | | | | | | | | Added current temperature reading support for gp10x. JIRA DNVGPU-48 Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1213717 (cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b) Reviewed-on: http://git-master/r/1234092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Suppress error msg from VBIOS overlayTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Suppress error message when nvgpu tries to load VBIOS overlay, but one is not found. This situation is normal. This is done by moving gk20a_request_firmware() to be nvgpu generic function nvgpu_request_firmware(), and adding a NO_WARN flag to it. Introduce also a NO_SOC flag to suppress attempt to load firmware from SoC specific directory in addition to the chip specific directory. Use it for dGPU firmware files. Bug 200236777 Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1223839 (cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d) Reviewed-on: http://git-master/r/1233412 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: MCLK P8/P5 sequences and APIDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | Adds P5/P8 sequences and simple debugfs API to change from P0->P5 JIRA DNVGPU-117 Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1208655 (cherry picked from commit dd410a86263e2407e043743945cf09a77910d745) Reviewed-on: http://git-master/r/1231035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update PMU bootloader paramsMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Bootloader of PMU is changed & bootloader takes params using flcn_bl_dmem_desc_v1 descriptor to boot PMU JIRA DNVGPU-116 Change-Id: I005b615b2323678fa605d190c6b9b629976f0b74 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212818 (cherry picked from commit 89976a03c13cce6bbba25c99270b0da4ca0f2441) Reviewed-on: http://git-master/r/1223842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Clocks params updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | - Clocks params update as per r370 JIRA DNVGPU-116 Change-Id: I0aaa1e275aaa2027f2839f3fe24c9aee3e14fd8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212827 (cherry picked from commit 54df6ad9668d46dffb5b9d03265948a47611ff13) Reviewed-on: http://git-master/r/1227288 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: sequencer-script updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | Update to sequencer script to support SKU without display. Bug 200231242 Change-Id: Ibd983166be823370fc687eb2fe9bae3aa8c0dab7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1207096 (cherry picked from commit b573a627b3fe7697c90def46eaf83d755c5d2dee) Reviewed-on: http://git-master/r/1227247 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add gp106 clock gating tablesTerje Bergstrom2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-72 JIRA DNVGPU-73 Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1215915 (cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390) Reviewed-on: http://git-master/r/1227267 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: Prune non-existing registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Prune non-existing registers from mclk shadow register list. Bug 1799537 Change-Id: I8034a1820ef21e550616a5135856b05c2f375d6f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208018 (cherry picked from commit cb988bb28dd914ea291cedec799d055f3d71d877) Reviewed-on: http://git-master/r/1227266 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: Skip resetting FBTerje Bergstrom2016-12-27
| | | | | | | | | | | | | FB is enabled in devinit. Skip resetting it in GPU boot. Bug 1799537 Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208715 (cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698) Reviewed-on: http://git-master/r/1227265 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add debugfs to dump clocksDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | * Removed unused registers from headers * Added counter based MCLK * Removed hardcoding JIRA DNVGPU-98 Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1204019 (cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c) Reviewed-on: http://git-master/r/1227264 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add dGPU clocks supportVijayakumar Subbu2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Adding support for mclk moduleMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | JIRA DNVGPU-88 Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1202551 (cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108) Reviewed-on: http://git-master/r/1223854 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Add NVC097_SET_GO_IDLE_TIMEOUT SW methodSami Kiminki2016-12-27
| | | | | | | | | | | | | | | Add the NVC097_SET_GO_IDLE_TIMEOUT SW method for GP106. This enables booting the X server. Bug 1732372 Bug 1792002 Change-Id: I73abaaea240039dc91c66e3862ec01a342db2fa9 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1200637 (cherry picked from commit 0d24a6f3d8e421ea5205279166c6dc2d0f15c6a0) Reviewed-on: http://git-master/r/1223101 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pde0 target bit programmingKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | | | Use entry->mem for determining the target aperture bits of the memory block represented by entry->mem in update_gmmu_pde0_locked(), instead of pte->mem that holds the parent memory where this bit is written to. Previously this has worked because all page tables have been in the same aperture, but really large userspace allocations may push a part of them suddendly to sysmem. Bug 1809939 Change-Id: I3372487c6ae9793018ce44552ded3fb1ba4d145a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1218636 (cherry picked from commit a92596f6e8e621e51b6afae9ab7e62044d6311eb) Reviewed-on: http://git-master/r/1220525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: select target based on apertureDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | For bar2 and pmu instance blocks, use gk20a_aperture_mask() to select target address (i.e. if address is in sysmem or vidmem) based on aperture Also add target accessors for gr_fecs_new_ctx and gr_fecs_arb_ctx_ptr Jira DNVGPU-22 Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1216138 (cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b) Reviewed-on: http://git-master/r/1219712 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Skip LTCA initializationTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Skip LTCA initialization on dGPU. Bug 1799537 Change-Id: Ieb4c72e2169dc6bee73306c9b1e6c80866167a1a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208714 (cherry picked from commit 9a8dc5fe96b29b8a67f8203f17126b0093721312) Reviewed-on: http://git-master/r/1219164 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: change the usage of tegra_fuse_readlShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: update prod setting for slcgseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Update prod settings for slcg fifo. Bug 1785549 Change-Id: I0371ef7aeacce5933e06dd36d1368ddc06154ff9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1218109 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not initialize CBC on Pascal dGPUTerje Bergstrom2016-12-27
| | | | | | | | | | | | | CBC_BASE register is protected on Pascal dGPUs. Skip initializing it. Bug 1799537 Change-Id: Ie4b0ac5a37c3c586d1b631ce38823d156b554e1e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208016 (cherry picked from commit 5f9dbca140573798bd05b5b27a7b6abe1871e90f) Reviewed-on: http://git-master/r/1210289 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: fix cbc base calculation for dGPUDavid Nieto2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-9 Change-Id: I22667acfadfcabf79af841ca5389e41d2ac34860 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1206478 (cherry picked from commit 098b932f7633a903c915b1257beb9304735b4113) Reviewed-on: http://git-master/r/1210288 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Remove clock gating prod valsTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | We are using gp10b prod values for gp106, and they are incompatible. Because of this we are accessing invalid registers. Delete all prod vals for gp106 until we have generated new ones. Bug 1799537 Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208716 (cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804) Reviewed-on: http://git-master/r/1217287 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: cyclestat snapshot supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | Add support for cyclestats snapshots in the virtual case Bug 1700143 JIRA EVLR-278 Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1216644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use get_base_addr() for pdb and mm_entryDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Since page tables could either reside either in sysmem or vidmem, use gk20a_mem_get_base_addr() to get the base address for buffer This API will take care of returning proper base address Jira DNVGPU-20 Change-Id: I3422b51c3ffb8fb86f1dc5095263fc8f19dae44d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1206407 (cherry picked from commit 3c4b22c35b2c4eec33234c2f8dccd9de9422d093) Reviewed-on: http://git-master/r/1210962 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 21:31:46 -0500