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* gpu: nvgpu: clean-up the codeSumit Singh2015-07-21
| | | | | | | | | | As CONFIG_PM_GENERIC_DOMAINS_OF is enabled, so cleaning-up the code which remains unused when this config is enabled. Bug 200070810 Change-Id: I884ca3d6fb8fa6acdff8c1b2fbe66a672758274a Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
* gpu: nvgpu: Add DT support for gpu power-domainSumit Singh2015-07-21
| | | | | | | | | | Make modification to add DT support for gpu power-domain for T186 chip. Bug 200105664 Change-Id: Ief8d0a6c84918578c52d153db7eac02587b67ee7 Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
* gpu: nvgpu: Increase VA space to 40 bitsAlex Waterman2015-07-20
| | | | | | | | | | | | | | | Now that the buddy allocator is merged we can increase the VA space without dramatically increasing memory usage by the allocator. 40 bits is the max VA space available on gk20a and gm20b. Change-Id: I7bc8d86e35b28f041e9a435f2571c8288970c8ee Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/745076 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/771152 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Fix address space limit computationAlex Waterman2015-07-20
| | | | | | | | | | | | | | | | | | | | | | The address space limit was being computed with the assumption that the va_limit field is inclusive. The va_limit field is actually not inclusive. It points to the first invalid byte. Thus when generating the adr_limit register the code incorrectly calculated that the address limit should be 0. To fix this the computation now just uses va_limit - 1. Also, the bitwise OR of 0xfff into the lower limit word was incorrect. The bottom 12 bits of the lower 32 bit word are ignored by the GPU and as such should not be populated. Change-Id: Ifcc13343aaf50776f3cf1a1e3726e73ffde5003f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/756690 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/771151 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Fix overflow of alloc lengthAlex Waterman2015-07-20
| | | | | | | | | | | | | | | Fix an issue where large ( > 4GB) allocations were not being computed correctly. The two fields, pages and page_size, were both 32 bits so when multiplied they easily overflowed. Simple fix is to cast them to 64 bits before multiplying them. Change-Id: I63fa54679e485de5c3a99684cbeb72c6cdc65504 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/747429 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/771148 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Use correct tpc_per_gpc for GM20bSandarbh Jain2015-07-17
| | | | | | | | | | | | | | While evaluating the broadcast register, use the correct max_tpc_per_gpc for gm20b. Bug 200118793 Change-Id: Icdc506c05895e5ecdd424dfa2729d0d53460ff15 Reviewed-on: http://git-master/r/765147 (cherry picked from commit be5add9a2f13f787ea408d2a28b0b82c776227d4) Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/771254 Reviewed-by: Ken Adams <kadams@nvidia.com> Tested-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: improve sched err handlingVijayakumar2015-07-17
| | | | | | | | | | | | | | | | | bug 200114561 1) when handling sched error, if CTXSW status reads switch check FECS mailbox register to know whether next or current channel caused error 2) Update recovery function to use ch id passed to it 3) Recovery function now passes mmu_engine_id to mmu fault handler instead of fifo_engine_id Change-Id: I3576cc4a90408b2f76b2c42cce19c27344531b1c Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/763538 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: check that GPU is powered before flushSam Payne2015-07-16
| | | | | | | | | | | | | | | | | | if GPU is not powered before L2 is flushed, then L2 cache flush is a noop. Same behavior as gk20a_mm_L2_Invalidate() bug 1661228 Change-Id: I0f590628928a73b7277d1b16a5a79a86e0213648 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/768068 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> (cherry picked from commit cb4d29d34d0736aa753afa323bfb216481cc8640) Reviewed-on: http://git-master/r/771113 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix channel close sequenceDeepak Nibade2015-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_cde_remove_ctx(), current sequence is as below - gk20a_channel_close() - gk20a_deinit_cde_img() - gk20a_free_obj_ctx() But gk20a_free_obj_ctx() needs reference to channel and hence below crash is seen : [ 3901.466223] Unable to handle kernel paging request at virtual address 00001624 ... [ 3901.535218] PC is at gk20a_free_obj_ctx+0x14/0xb0 [ 3901.539910] LR is at gk20a_deinit_cde_img+0xd8/0x12c Fix this by closing the channel after gk20a_deinit_cde_img() Bug 1625901 Change-Id: Ic2dc5af933b6d6ef8982c2b9f0caa28df204051f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/770322 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* nvgpu: gk20a: include proper header fileAmit Sharma (SW-TEGRA)2015-07-16
| | | | | | | | | | | | | | | Fixed the following sparse warning by including the "fb_gk20a.h" header file: - fb_gk20a.c: warning: symbol 'fb_gk20a_reset' was not declared. Should it be static? Bug 200088648 Change-Id: I1ba6051455a22e81da6598eebdccfa8b45b78c3e Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/768203 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/770654
* gpu: nvgpu: cyclestats snapshots are only for t210Leonid Moiseichuk2015-07-10
| | | | | | | | | | | | | | | | | | | | The cyclestats mode-e feature supported by userspace only for t210 devices, so kernel should advertize it only for t210. Also small check added to prevent BUG in dma-buf.c:826 if device has lack of memory. Bug 1662506 Change-Id: I8417a8cdd9092e64126382f379d171932e4592a1 Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com> Reviewed-on: http://git-master/r/767073 (cherry picked from commit 06f86b6e78bae5e26e32466716c18e7918efb1b1) Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/767148 Reviewed-by: Automatic_Commit_Validation_User
* nvgpu: gm20b: make local function 'static'Amit Sharma (SW-TEGRA)2015-07-10
| | | | | | | | | | | | | | | Fixed the following sparse warning by making the local function 'static': - warning: symbol 'gm20b_load_falcon_ucode' was not declared. Should it be static? Bug 200067946 Change-Id: I11beaa301dc45dfec6f2295a6a96c1571e0264c9 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/766361 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/767991 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Implement own rail gating codeTerje Bergstrom2015-07-07
| | | | | | | | | | | Move rail gating sequence to happen in nvgpu driver instead of piggybacking on Tegra power gating APIs. Bug 200115454 Change-Id: I8514686c7b137f200021b05ead7157d0883bddc5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/761991
* gpu: nvgpu: Update eng_buf_load message for T18xTerje Bergstrom2015-07-06
| | | | | | | | | | | | | | eng_buf_load message structure for T18x is updated. Update kernel code to follow. Bug 200119744 Change-Id: Ib86c3e54ed60704470b29d9f7de612697cfd54a3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/764458 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
* gpu: nvgpu: Reset FB also in gm20bTerje Bergstrom2015-07-03
| | | | | | | | FB reset was added for gk20a. It should be invoked also on gm20b. Change-Id: I0b074bc50a889108edae93d62b3194e54bfda881 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/765366
* gpu: nvgpu: Implement priv pagesTerje Bergstrom2015-07-03
| | | | | | | | Implement support for privileged pages. Use them for kernel allocated buffers. Change-Id: I720fc441008077b8e2ed218a7a685b8aab2258f0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/761919
* gpu: nvgpu: Move clk bypass div code to clk initTerje Bergstrom2015-07-03
| | | | | | | | | | | | | Clock bypass divider was changed just before resetting priv ring. Move the code to a new clk op instead so that it is executed only on gk20a. Change-Id: Ic8084a4a5fac23770f50b50f910ced2543ba0f28 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/764970 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Initial MAP_BUFFER_BATCH implementationSami Kiminki2015-06-30
| | | | | | | | | | | | | | | | | | | Add batch support for mapping and unmapping. Batching essentially helps transform some per-map/unmap overhead to per-batch overhead, namely gk20a_busy()/gk20a_idle() calls, GPU L2 flushes, and GPU TLB invalidates. Batching with size 64 has been measured to yield >20x speed-up in low-level fixed-address mapping microbenchmarks. Bug 1614735 Bug 1623949 Change-Id: Ie22b9caea5a7c3fc68a968d1b7f8488dfce72085 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/733231 (cherry picked from commit de4a7cfb93e8228a4a0c6a2815755a8df4531c91) Reviewed-on: http://git-master/r/763812 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Delete T132 specific configurationTerje Bergstrom2015-06-29
| | | | | | Change-Id: I1cd97a8ea0911a657fc4d5b7a3aee534474aea47 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/762558
* Merge PM domain changes from k3.10 into 'kernel-3.18'Sumit Singh2015-06-29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change brings in all changes that were done for: 1. device-tree support for power domains 2. device-tree support for power-gating driver 3. Reverts of 3 changes from k3.18 power-domain Bug 200070810 Bug 200105664 Bug 200100078 Change-Id: Iba93713180d66caa46f1f55c30e9bbde2be9dcc0 Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
| * gpu: nvgpu: Uncomment suspend/resume opsSumit Singh2015-06-29
| | | | | | | | | | | | | | | | | | | | As upstream has removed them, but we are still using these. So uncommenting these callback assignment. Bug 200070810 Change-Id: I26a221f9d76f6acef70095eb8afcf440057f464c Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
| * gpu: nvgpu: Add DT support for gpu power-domain for T132Sumit Singh2015-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | Make modification to add DT support for gpu power-domain for T132 chip. Bug 200070810 Change-Id: Iac63c8fb5fc5280e9a9f5758e63c9da009f3813d Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/739698 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
| * Revert "HACK: Disable genpd_pm_subdomain_attach"Sumit Singh2015-06-29
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 83699a4ec9ebf55f6cc12c76e57dad1d4ec2fbfa. This hack was put in place as upstream has removed of_node field from generic_pm_domain structure. But as we are still using it, so removing this hack. Bug 200100078 Change-Id: I14e533786fb814e361c580e2883ceff1f63d251f
* | gpu: nvgpu: load secure gpccs using dmaVijayakumar2015-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bug 200080684 use new cmd defined in ucode for loading GR falcons. flip PRIV load flag in lsb header to indicate using dma. use pmu msg as cmd completion for new cmd instead of polling fecs mailbox. also move check for using dma in non secure boot path to hal. Change-Id: I22582a705bd1ae0603f858e1fe200d72e6794a81 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/761625 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* | gpu: nvgpu: More verbose BAR1 failure messageRich Wiley2015-06-26
| | | | | | | | | | | | | | | | Change-Id: Ie575aa3eeea8ebddf5778be0d03cf9744ec35540 Signed-off-by: Rich Wiley <rwiley@nvidia.com> Reviewed-on: http://git-master/r/760860 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* | gpu: nvgpu: While flushing, check only enabled L2sTerje Bergstrom2015-06-26
|/ | | | | | | | | | When flushing L2 do not check status of L2s not present in system. Change-Id: I95703689314c146f591fea0d85b1a484fdf82cf7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/759267 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: update flush L2 ioctl definitionSam Payne2015-06-23
| | | | | | | | | | | | | | | | | | this ioctl can be called only by a ctrlfd created from the /dev/nvhost-ctrl-gpu node therefore NVGPU_GPU_IOCTL_MAGIC, not NVGPU_DBG_GPU_IOCTL_MAGIC should be used for this bug 200111987 Change-Id: I9fce7eae9f8203a15270ac1d25b575aebd9ccf88 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/755164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit 609d45ddd98c31ecd089d2e213ee1b6c560fc21e) Reviewed-on: http://git-master/r/760830
* gpu: nvgpu: make functions as staticAlankrita G2015-06-23
| | | | | | | | | | | | | | | | - Fixed the following sparse warnings by making the local function as static: warning: symbol 'balloc_alloc_buddy' was not declared. Should it be static? Bug 200067946 Change-Id: I6eeb71f6c0d5fbfb99f6c43bbc4504fea1bc8d46 Signed-off-by: Alankrita G <alankritag@nvidia.com> Reviewed-on: http://git-master/r/746583 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/760446 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Tested-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: vgpu: support additional notificationsAingara Paramakuru2015-06-22
| | | | | | | | | | | | | | | | | Client notification support is now added for the following: - stalling and non-stalling GR sema release - non-stalling FIFO channel intr - non-stalling CE2 nonblockpipe intr Bug 200097077 Change-Id: Icd3c076d7880e1c9ef1fcc0fc58eed9f23f39277 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/736064 (cherry picked from commit 0585d1f14d5a5ae1ccde8ccb7b7daa5593b3d1bc) Reviewed-on: http://git-master/r/759824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Use NULL instead of integer '0'Amit Sharma (SW-TEGRA)2015-06-19
| | | | | | | | | | | | | | | | Fixed the following sparse warning by using the proper 'NULL' instead of '0': - fifo_gk20a.c: warning: Using plain integer as NULL pointer Bug 200067946 Bug 200088648 Change-Id: I316b119e87b7203450ce85232398b43384ee16cc Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/755348 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/757050
* gpu: nvgpu: Export gm20b floorsweepingTerje Bergstrom2015-06-12
| | | | | | | Change-Id: Ied5b1d2e3761a2f82d6b9e3cb9a7b04ea746f1da Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755208 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: remove excessive allow_all checksLeonid Moiseichuk2015-06-12
| | | | | | | | | | | | | | | | The allow_all checks are not required for mode-E snapshot buffers operations. Bug 1573150 Change-Id: I570e70d7ae94b8c9bf2d3e55996442bfe5f71410 Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com> Reviewed-on: http://git-master/r/754413 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755494
* gpu: nvgpu: Check for split_order > max_orderAlex Waterman2015-06-11
| | | | | | | | | | | | | | When choosing an order of buddy to start splitting from (happens when no buddies of the requested alloc order exist) don't sit in the while loop past max_order. This makes no sense and hangs the system. Bug 1647902 Change-Id: I6900597d24944d3170bc76cd75f33794b07707d1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/756591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Swap order of free/rb_eraseAlex Waterman2015-06-11
| | | | | | | | | | | | | | | | If rb_erase() is called after __balloc_do_free_fixed() then the rb_tree code crashes when trying to dereference the possibly changed (or poisoned in the case of debugging) data in the rb_node. Change-Id: I4a4456a5ec453fd9ab117c804dc19b2c048a61d4 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/755646 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Ian Stewart <istewart@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755816 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove simulation WARAlex Waterman2015-06-11
| | | | | | | | | | | | | | | | | | The WAR put into simulation to avoid a simulator crash can now be removed (c85be1a0968de813fe9b99ebd5c261dcb0ca8875). The first issue with the failing test was found to be GPFIFO entries that were not invalid. Other issues are still present with the test and are fixed in a later commit. Change-Id: I7d3def2e384eede82cfc82b961f09ca23b239d30 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/753378 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755815 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: WAR for bad GPFIFO entries from userspaceAlex Waterman2015-06-11
| | | | | | | | | | | | | | | | | | Userspace sometimes sends GPFIFO entries with a zero length. This is a problem when the address of the pushbuffer of zero length is larger than 32 bits. The high bits are interpreted as an opcode and either triggers an operation that should not happen or is trated as invalid. Oddly, this WAR is only necessary on simulation. Change-Id: I8be007c50f46d3e35c6a0e8512be88a8e68ee739 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/753379 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755814 Reviewed-by: Automatic_Commit_Validation_User
* gpu:nvgpu: correct name for unmapped ptes flagsSeshendra Gadagottu2015-06-10
| | | | | | | | | | Bug 1587825 Change-Id: I66f2988b7f1884b53bb8f3cd09ad1ead1652ffda Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/751484 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix prefix and export commit attrib cbTerje Bergstrom2015-06-10
| | | | | | | Change-Id: I8309837978b069fa5d416b7713654d6b71543c77 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/755212 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Do not pre-allocate cmdbuf entriesTerje Bergstrom2015-06-09
| | | | | | | | | | | | | | | Do not preallocate cmdbuf tracking entries. Allocate them only when needed. Bug 200104160 Change-Id: I12f8392723c301a368af1e280893ff993480477f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/743953 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/755148
* gpu: nvgpu: add per-channel refcountingKonsta Holtta2015-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add reference counting for channels, and wait for reference count to get to 0 in gk20a_channel_free() before actually freeing the channel. Also, change free channel tracking a bit by employing a list of free channels, which simplifies the procedure of finding available channels with reference counting. Each use of a channel must have a reference taken before use or held by the caller. Taking a reference of a wild channel pointer may fail, if the channel is either not opened or in a process of being closed. Also, add safeguards for protecting accidental use of closed channels, specifically, by setting ch->g = NULL in channel free. This will make it obvious if freed channel is attempted to be used. The last user of a channel might be the deferred interrupt handler, so wait for deferred interrupts to be processed twice in the channel free procedure: once for providing last notifications to the channel and once to make sure there are no stale pointers left after referencing to the channel has been denied. Finally, fix some races in channel and TSG force reset IOCTL path, by pausing the channel scheduler in gk20a_fifo_recover_ch() and gk20a_fifo_recover_tsg(), while the affected engines have been identified, the appropriate MMU faults triggered, and the MMU faults handled. In this case, make sure that the MMU fault does not attempt to query the hardware about the failing channel or TSG ids. This should make channel recovery more safe also in the regular (i.e., not in the interrupt handler) context. Bug 1530226 Bug 1597493 Bug 1625901 Bug 200076344 Bug 200071810 Change-Id: Ib274876908e18219c64ea41e50ca443df81d957b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/448463 (cherry picked from commit 3f03aeae64ef2af4829e06f5f63062e8ebd21353) Reviewed-on: http://git-master/r/755147 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: use 64K hole for PMU VMVijayakumar2015-06-06
| | | | | | | | | | | | | | | | | | | With 4K hole T186 PMU does not boot in NS T186 has 64 bit DMA Base. We subtract IMEM offset from GPUVA for PMU boot DMABASE setup It becomes above 4GB because of that So we will use a hole which is bigger than IMEM size. Change-Id: Ib87c39881299a4f5b14e28415195e00800250c46 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/740656 (cherry picked from commit 6504934d5f90719a5d564174aeb92da90aafbd5b) Reviewed-on: http://git-master/r/747742 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix build problem by including slab.hTerje Bergstrom2015-06-06
| | | | | | | | | Change-Id: I2346ed48bf82c032194264bab999097bf86404e2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/745885 (cherry picked from commit aba5f1ce08c2813c8bd570f36a5d15aa2a1aeaf8) Reviewed-on: http://git-master/r/753286 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: restore 50ms unmap wait for fixed bufsKonsta Holtta2015-06-06
| | | | | | | | | | | | | | | | | | Increase sync-unmap wait time from 5 ms to 50 ms. 6ccac11b4dd1a4eaf9c914fd567cdf7922184e28 decreased the wait tenfold, so this puts it back. Bug 1650025 Bug 200078514 Change-Id: I53a4ea115536ca2ff5d6aa701547c7477ac6e4ea Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/748224 (cherry picked from commit 7c22a24817f0880941e6f4343059fa303ec9eff5) Reviewed-on: http://git-master/r/753285 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Infinite wait for fixed alloc unmapTerje Bergstrom2015-06-06
| | | | | | | | | | | | | | In non-silicon wait infinitely for all jobs to complete before unmapping a fixed allocation. Bug 200078514 Change-Id: I9196afb1d3c5f0c999113a4a17ada2989ac55707 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/744067 (cherry picked from commit 6ccac11b4dd1a4eaf9c914fd567cdf7922184e28) Reviewed-on: http://git-master/r/753284 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Disable channel when updating SMPC WARTerje Bergstrom2015-06-06
| | | | | | | | | | | | | | | When updating SMPC WAR for channel, it needs to be kicked out. This ensures that the updated information is re-read from context header. Bug 1579548 Change-Id: Ia65bdb638cec7125021a8e60c365b83085efe0d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/741322 Reviewed-on: http://git-master/r/743859 (cherry picked from commit dd6cd54b41d63ae94d066b8d98a40c6f6a2196e5) Reviewed-on: http://git-master/r/753283 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Correction in allow_all flag usagesujeet baranwal2015-06-06
| | | | | | | | | | | | | | | | | The allow_all flag is used to avoid any kind of register's offset being validate when called through regops. but the current implementation was flawed. It printed error messages and set the status of each operation invalid, even when allow_all was set. Change-Id: Ie5a70a3cdc2368715731cf1c9cd771fdcf6b0d57 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/723830 (cherry picked from commit 4483ef020ff5f0fabc83b1226376b02d42bd1d75) Reviewed-on: http://git-master/r/753282 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix compbits mappingSami Kiminki2015-06-06
| | | | | | | | | | | | | | | | Commit e99aa2485f8992eabe3556f3ebcb57bdc8ad91ff broke compbits mapping. So, let's fix it. Bug 200077571 Change-Id: I02dc150fbcb4cd59660f510adde9f029290efdfb Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/745001 (cherry picked from commit 86fc7ec9a05999bea8de320840b962db3ee11410) Reviewed-on: http://git-master/r/753281 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix OOM case for buddy allocatorAlex Waterman2015-06-06
| | | | | | | | | | | | | | | | | | | | | The allocator could attempt to use a buddy list for an order larger than the max order when all the valid buddy lists were empty. This patch ensures that when looking for a particular order buddy that the passed order is valid. Also handle the prints in the no-mem case a litle differently. Only print and update alloc info when there was a successful allocation. Lastly print hex numbers for the allocator stats printing function. Change-Id: If289f3e8925e236e3b7d84206a75bd45a14082a1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/745071 (cherry picked from commit f3548e67f435975238b55ac152871dcd60a1a907) Reviewed-on: http://git-master/r/753280 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: sysfs queriesAnders Kugler2015-06-06
| | | | | | | | | | | | | | | | Export the gpu's safe fmax_at_vmin frequency so it can be queried from userspace (e.g. PHS). Bug 1566108 Change-Id: I47326588ebd443f189a6051edbf95b35b35636d1 Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/743501 (cherry picked from commit a977495878a486ca45c7de969582fd9ea949b0f0) Reviewed-on: http://git-master/r/753279 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add zbc support to vgpuRichard Zhao2015-06-06
| | | | | | | | | | | | | | | | | | | For both adding and querying zbc entry, added callbacks in gr ops. Native gpu driver (gk20a) and vgpu will both hook there. For vgpu, it will add or query zbc entry from RM server. Bug 1558561 Change-Id: If8a4850ecfbff41d8592664f5f93ad8c25f6fbce Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/732775 (cherry picked from commit a3787cf971128904c2712338087685b02673065d) Reviewed-on: http://git-master/r/737880 (cherry picked from commit fca2a0457c968656dc29455608f35acab094d816) Reviewed-on: http://git-master/r/753278 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 02:54:54 -0500