| Commit message (Collapse) | Author | Age |
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Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.
JIRA NVGPU-957
Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795845
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change-Id: I106a4e7de010d169c890e6b8dd28b3e0841b83a2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801498
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has
a broken implementation.
Bug 200439908
Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800797
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
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Since the posix code is supporting a particular OS this code
should belong under os/ not common/.
Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800658
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We do not use the stored hshub_config* register values.
Remove these redundant fields from nvlink data structure too.
This also allows us to not #include a FB hardware header in
nvlink.
JIRA NVGPU-966
Change-Id: I3be169a958ec17370b55889d1e1fbabb887a79fd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794955
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: Ieeecf719dca9acc1a116d2893637bf770caf4f5b
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794241
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I129cc170d27c7f1f2e193b326b95ebbe3c75ebab
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795600
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move implementation of ltc HAL to common/ltc.
JIRA NVGPU-956
Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The perf inst block was being treated as vidmem (LFB - local
framebuffer) always, regardless of the type of nvgpu_mem used
for the instance block. On dGPUs this was fine becasue we
always allocate instance blocks from vidmem. Inst blocks are
allocated with nvgpu_dma_alloc() which chooses vidmem if
vidmem is present, otherwise falls back to sysmem.
When the above fall back logic was deleted this caused inst
blocks to always be allocated in sysmem, even for dGPUs. This
isn't a problem in an of itself but the logic for the perf
instance block bind operation assumed a VIDMEM inst_block.
Thus this patch uses the nvgpu_aperture_mask() function to
correctly program the required aperture target for the perf's
inst block bind operation.
JIRA NVGPU-990
Change-Id: If6f09a743ee2ad47a6dbfa28cb7c61f1461fd8a7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This flag - has_physical_mode - doesn't seem to do much other than
force the PTE/PDE and inst block addresses to be physical instead
of potentially IOMMUed.
There is a reason to do this on volta (nvlink not being IOMMU'able
being the primary reason) but this flag is too general it seems.
The flag was being enabled on all native platforms. The problem is
that some page tables (the maxwell small page directories) could
be larger than 4KB which meant that the allocation used for them
could be potentially discontiguous. Discontiguous page directories
obviously is incorrect.
This patch deletes the has_physical_mode flag and instead replaces
the places where it's checked with a check for nvlink being
enabled. Since we _do_ want to program phyiscal PDEs and PTEs for
NVLINK devices (regardless of IOMMU status they always access
memory by physical address) we need a check for NVLINK state.
Bug 200414723
Change-Id: I09ad86b12d8aabcf9648a22503f4747fd63514dd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- fetch ecc info from RM server and create sysfs nodes
- new file ecc_vgpu.c for platform-independent code
- add 2 new commands: GET_ECC_INFO and GET_ECC_COUNTER_VALUE
JIRA EVLR-2590
Change-Id: I040a9fcd23326e432ca93e9a028319f9c1c570f0
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777428
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Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.
Bump gk20a code to gm20b.
JIRA NVGPU-955
Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
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Added targets in corresponding makefiles/sources to enable building
nvgpu-next from userspace.
JIRA NVGPU-1015
Change-Id: Ia358162e14205035e4552bfb7f32825c7de48fc2
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792003
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The nvgpu_ioctl_tsg_open() does not make sure that GPU is
unpowergated. Due to this it leads to kernel
panic when GPU registers are accessed when powergated.
__gk20a_warn_on_no_regs+0x38/0x58 [nvgpu]
__nvgpu_readl+0x74/0xc8 [nvgpu]
nvgpu_readl+0x28/0x60 [nvgpu]
xxxxx_ce_get_num_pce+0x28/0x70 [nvgpu]
xxxxx_fifo_init_eng_method_buffers+0x64/0x1c0 [nvgpu]
gk20a_tsg_open+0x110/0x1e0 [nvgpu]
nvgpu_ioctl_tsg_open+0x88/0x100 [nvgpu]
gk20a_ctrl_dev_ioctl+0x734/0x2388 [nvgpu]
do_vfs_ioctl+0xc4/0x918
SyS_ioctl+0x94/0xa8
This change fixes this issue by calling gk20a_busy()/gk20a_idle()
in nvgpu_ioctl_tsg_open()
Bug 2268533
JIRA NVGPU-1016
Change-Id: I578289e7eb60295d6b6169b754a5cc60f7546fd5
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794324
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA rule-10.4 only allows arithmetic conversions on operands of the
same essential type category.
Fix violations where an arithmetic conversion is performed on enum and
non-enum types.
JIRA NVGPU-993
Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792852
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Move implementation of priv_ring HAL to common/priv_ring. Implement
two new HAL APIs to remove illegal dependencies: enable_priv_ring and
enum_ltc.
As enum_ltc can be implemented only gm20b onwards, bump gk20a
implementation to base on gm20b.
JIRA NVGPU-964
Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797025
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Export below APIs in gv11b/gr_gv11b.h header so that they can be called from
other files too
gr_gv11b_set_shader_cut_collector()
gr_gv11b_set_go_idle_timeout()
gr_gv11b_set_coalesce_buffer_size()
gr_gv11b_set_tex_in_dbg()
gr_gv11b_set_skedcheck()
gv11b_gr_set_shader_exceptions()
Bug 2260560
Change-Id: Ic85e35bc223c88c2a54fab09851b8a957b4d1153
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1793525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit b79c350d68bac79ec9ed80ef5f19f15a0d0eedf4.
Underlying PRAMIN infrastructure enforces 4 byte aligned size only,
so the API should enforce that too
Bug 2285052
Change-Id: I2b4a209edd479d72992708b35e1d52940ff20637
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a bunch of build warning flags to make userspace builds mimic
the strictness of standard tmake builds.
Change-Id: If6f1f716f2bb2d64d240a66be2cb3aae814f24d0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796239
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Long <scottl@nvidia.com>
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userspace/src/module.c should #include its own <unit/module.h> to get
declarations for the functions defined.
Change-Id: Icff647f19468607ebfb757360b83ce9f133bd5ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797034
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
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When built with -Wmissing-braces, compiler complains about the missing
braces in nvgpu_mem_rd_n, nvgpu_mem_wr_n and nvgpu_memset. Add the
braces to satisfy compiler and to fix related MISRA C violations.
Change-Id: Ibe3606dc59317f8230cea57cfea8d0fe5af641d6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796238
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
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These macros exist to make integer literals used in certain arithmetic
operations explicitly large enough to hold the results of that operation.
The following is an example of this.
In MISRA the destination for a bitwise shift must be able to hold the number
of bits shifted. Otherwise the results are undefined. For example:
256U << 20U
This is valid C code but the results of this _may_ be undefined if the size
of an unsigned by default is less than 24 bits (i.e 16 bits). The MISRA misra
checker sees the 256U and determines that the 256U fits in a 16 bit data type
(i.e a u16). Since a u16 has 16 bits, which is less than 20, this is an
issue.
Of course most compilers these days use 32 bits for the default unsigned type
this is not a requirement. Moreover this name problem could exist like so:
0xfffffU << 40U
The 0xfffffU is a 32 bit unsigned type; but we are shifting 40 bits which
overflows the 32 bit data type. So in this case we need an explicit cast to
64 bits in order to prevent undefined behavior.
Change-Id: If2433fb8c44df0c714487fa3b6b056fc84570df7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795391
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Removed the utils.h include from gk20a.h
utils.h is included in those files which
make use of the macros in utils.h
JIRA NVGPU-1005
Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations
But we have separate gops.regops operations for all the regops and this would
be logically correct place for exec_reg_ops()
Move exec_reg_ops() from gops.dbg_session_ops to gops.regops
Also rename it to exec_regops()
Jira NVGPU-620
Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794999
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Add a unit test to test the nvgpu-posix bitmap implementation. This
unit test aims to both verify the functionality of this low level
set of APIs and provide a reference for how to use the basic unit
test functionality.
JIRA NVGPU-525
Change-Id: Ide5263e5ce49f18f5f2a3d4a6f9e494395299386
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1695007
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a super simple tiny test unit module to test the unit test
framework.
This unit test has a test that deliberately fails so it obviously
cannot be part of a real unit test run. Eventually this will have
to be removed or otherwise skipped.
JIRA NVGPU-525
Change-Id: I41532a85156445a778897bbc84bb5919deab56ae
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1687095
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Sort unit tests by their priority before running said unit tests.
There are three available priorities:
UNIT_PRIO_SELF_TEST
UNIT_PRIO_POSIX_TEST
UNIT_PRIO_NVGPU_TEST
Which correspond to the types of testing expected to be run. In
general unit tests should always just use UNIT_PRIO_NVGPU_TEST but
in the case of tests for the POSIX API layer or the unit test
framework the other two priorities are provided.
The reason for this is that it doesn't make much sense to run a
bunch of unit tests if the environment itself or the POSIX API
layer is broken. By placing these tests at the front of the list
of tests to run an engineer will easily be able to see if there
are core problems versus nvgpu problems.
This also lets users fine grain control of test order by adding
or subtracting to UNIT_PRIO_NVGPU_TEST but one must be very
careful about how they do this.
JIRA NVGPU-525
Change-Id: I12a5b798e998f34e4d1168bb3696c579460f20b1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741953
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Full documentation for this is in the unit testing
confluence page.
JIRA NVGPU-525
Bug 2261555
Change-Id: I463e6267eb0eb12b7313f8b275266e8faabe5ccf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683915
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move implementation of xve HAL to common/xve.
JIRA NVGPU-959
Change-Id: I27dba43253e3aa8fd11229a9c4fad97aa5cf0b59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.
JIRA NVGPU-989
Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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CBC base needs to be aligned to 64KB. On Linux this is
achieved making compbit backing size multiple of 64KB.
However QNX nvmap alloc function does not allocate
memory aligned to requested size and needs to overallocate
to satisfy alignment requirement. Make cbc alloc function OS
specific to be able to modify QNX code.
Also align cbc base address to 64KB before writing to CBC BASE
register.
Bug 200426427
Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36)
Reviewed-on: https://git-master.nvidia.com/r/1786046
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add reply messages for Therm, clock and Perf.
Bug 200428344
Change-Id: Ifb325d546a81f6810ac88b87cc10b718d279ac82
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792825
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The error returned from the execution of exec_reg_ops was ignored
leading to not propagating the error values to the caller methods.
This patch handles the error occurence in the exec_reg_ops call.
Bug 2245743
Change-Id: I0d696c116fc1b2fce0e14ac7a05e1d85b5d18129
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775818
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clk_arb.h and gk20a.h has circular dependencies to each other. This is
removed by forward declaring struct gk20a in clk_arb.h and removing the
header gk20a.h from clk_arb.h and similarly forward declaring struct
nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h
alongwith putting headers in every execution unit which calls clk_arb.h
related methods.
JIRA NVGPU-597
Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790915
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is
added to dbg session.
Currently support SM_EXCEPTION_TYPE_MASK_FATAL type
If this type is set then the code will skip RC recovery,
instead trigger CILP preemption.
bug 200412641
JIRA NVGPU-702
Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729792
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ce2.c is free of all Linux'isms and can be moved to
the common code, so that it can be used by other
OS'es.
VQRM-3705
Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792100
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix MISRA rule 10.1 violations involving need_reset var
in gk20a_gr_isr().
Changed type to bool and set it to true any time one of
the pending condition checks returns non-zero.
JIRA NVGPU-650
Change-Id: I2f87b68d455345080f7b4c68cacf515e074c671a
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1793633
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The sysfs_attr_init accepts pointer of struct attribute instead of
struct device_attribute. This patch fixes build error when
CONFIG_DEBUG_LOCK_ALLOC is enabled.
Bug 200432223
Change-Id: Id655ca18102c5252485db378ba2499a66d758882
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786590
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Moved the gk20a_from_as and gk20a_from_pmu
definitions from gk20a.h to as.h and pmu.h
Correction for MISRA rule 21.1 error
in as.h and pmu.h headers
JIRA NVGPU-624
Change-Id: I57de604b47afc589a9778fe69e4856ffcabd9dfc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785951
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Once tpc_pg_mask is programmed successfully, TPC PG mask and status
will be the same value afterwards and won't change. So we don't have
to inform user whenever gr_gv11b_powergate_tpc() is invoked.
Bug 200406784
Bug 200436857
Change-Id: I52f7bdbbbc0851b59366b1cd7d25ae7b8b9fa14e
Signed-off-by: Leon Yu <leoyu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791008
(cherry picked from commit c8872d61a2bc40e09e137a4bb81923c4747a2dcc)
Reviewed-on: https://git-master.nvidia.com/r/1791656
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/gk20a/
JIRA NVGPU-989
Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791019
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gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to
use max_gpc_count for any possible cases rather not gpc_count.
Bug 2302005
Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790464
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This fixes errors due to single statement loop bodies without braces,
which is part of Rule 15.6 of MISRA. This patch covers gpu/nvgpu/gm20b/
JIRA NVGPU-989
Change-Id: Ia177bd990409500fc8e8a2a54ba013df84cb9822
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1788050
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This reverts commit 96d4842c0dbae051258408480b981ed034163c13.
Change-Id: Ibcdf78b242c7bb9f17651b2bb9e23777c97cd436
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790634
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Fix MISRA rule 10.1 violations in gr_gk20a_init_ctx_vars_sim().
Instead of logically ORing alloc_xxx_list_yyy() results into
the signed err variable just bail immediately if an allocation
request fails.
Also made changes to sync gr_gk20a_init_ctx_vars_sim() behavior
with gr_gk20a_init_ctx_vars_fw() behavior:
* return a valid errno on failure
* free any previously allocated resources on failure
JIRA NVGPU-650
Change-Id: Ie5ea78438da59896da2a9f562d01e46ffaf56dec
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787042
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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In nvgpu_ioctl_channel_reg_ops(), we right now first check if context is
allocated or not and if context is not allocated we fail the regops operation
But it is possible that the regops operation only includes global regops which
does not need global context allocated
So move this global context check from nvgpu_ioctl_channel_reg_ops() to
exec_regops_gk20a() and only if we have context ops included in the regops
Bug 200431958
Change-Id: Iaa4953235d95b2106d5f81a456141d3a57603fb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1789262
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This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/common/
JIRA NVGPU-989
Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add support for PCI device id 0x1efa which has same driver data as of 0x1eba
device
Change-Id: If3d53fe116c711bf63a10eae0e731537b3705bc1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1788694
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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once gpu is powered off i.e. power_on set to false, nvgpu isr
does not handle stall/nonstall irq. Depending upon state
of gpu, this can result in either of following errors:
1) irq 458: nobody cared (try booting with the "irqpoll" option)
2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is
not in time.
Fix these by masking all interrupts just before gpu power off
as nvgpu won't be handling any irq anymore.
While masking interrupts, if there are any pending interrupts,
then report those with a log message.
Bug 1987855
Bug 200424832
Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770802
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