| Commit message (Collapse) | Author | Age |
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The NEXT bit can remain set for the channel if timeslice expires before
scheduler clears it. Due to this nvgpu fails TSG unbind and in turn
nvrm_gpu fails channel close. In this case, checking the channel hw
state after some time can help see NEXT bit cleared by scheduler.
Reenable the tsg and return -EAGAIN to nvrm_gpu for it to retry again.
Bug 3144960
Bug 200520811
Change-Id: I35f417f02270e371a4e632986b73a00f8a4f921a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468391
(cherry picked from commit cf287a4ef592e7329f813c076ec8bdad18dc5933)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2479106
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GVS: Gerrit_Virtual_Submit
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- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
for GP10B
- Updated the GP10B PMU app version for the ucode:
https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260
P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520
Bug 3233071
Bug 200696431
Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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As sprintf() is used to populate pool_name[20], it can overflow
for larger u32 values (u32 max decimal number chars are 10) i.e.
20 < strlen("semaphore_pool-") i.e. 15 + 10.
Fix this overflow by removing pool_name as it's not used.
Bug 2626446
Bug 3273414
Change-Id: I4e0a222a2cd34dcd09e69294bc46e2242abb04bb
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205356
(cherry picked from commit baa86cf134ee6753beabfa974a10faffc5775ee8)
Signed-off-by: ByungKuk Seo <bseo@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2496976
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This fix add NULL-ptr checks for some of the user-accessible
ioctl.
Bug 3240771
Bug 200696704
Change-Id: Ibe7f75b31b2521a530883253a93ba832f010dc80
Signed-off-by: Thomas Steinle <tsteinle@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483635
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Reviewed-by: Phoenix Jung <pjung@nvidia.com>
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Wrong acquire/release sequence.
DEBUG_LOCKS_WARN_ON(rt_mutex_owner(lock) != current)
....
CPU: 4 PID: 5404 Comm: cyclictest.sh Not tainted 4.9.201-rt134-tegra #1
Hardware name: Jetson-AGX (DT)
....
Call trace:
[<ffffff800810e4f8>] debug_rt_mutex_unlock+0x58/0x68
[<ffffff8008f34d0c>] rt_mutex_unlock+0x4c/0xb0
[<ffffff8008f36ea8>] _mutex_unlock+0x20/0x2c
[<ffffff8000f69d80>] nvgpu_cg_elcg_set_elcg_enabled+0x78/0xf0 [nvgpu]
[<ffffff8000f7bd44>] nvgpu_intr_nonstall_cb+0x21bc/0x22f0 [nvgpu]
[<ffffff800875b304>] dev_attr_store+0x44/0x60
[<ffffff80082dca44>] sysfs_kf_write+0x5c/0x78
[<ffffff80082dbd28>] kernfs_fop_write+0xc0/0x1d8
[<ffffff8008245b60>] __vfs_write+0x48/0x128
[<ffffff8008246b3c>] vfs_write+0xac/0x1b8
[<ffffff800824808c>] SyS_write+0x5c/0xc8
Bug 3227296
Suggested-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Change-Id: I932a23700539422c07de045dde516c52dd8348cf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2472903
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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When try to read '/sys/kernel/debug/gpu.0/railgate_residency'
debug fs node, NULL pointer access error can be happened if
is_railgated function is not assinged.
Add check for is_railgated before calling the function pointer.
Bug 200682233
Change-Id: I4a03d4e19b04d02815b792d7d967d4a1d5f42c35
Signed-off-by: Alvin Park <apark@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2459751
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Hardik T Shah <hardikts@nvidia.com>
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Reviewed-by: Jay Kumar Bajaj <jbajaj@nvidia.com>
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Host scheduler might be confused if more than one channels are present
in TSG and one of the unbound channel has NEXT set.
This is not so much of an issue if there is single channel in the TSG.
So don't fail unbind in that case. ctx_reload and engine_faulted check
can also be skipped for single channel TSG.
Bug 3144960
Change-Id: I85eb9025ea53706ce8fda6d9b4bcf6a15a300d17
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2442970
(cherry picked from commit ad4624aae3f109fc3c8c03653cb691e09f086930)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445445
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Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Register list for ACB SLCG is auto generated with scripts.
Add HAL operations to enable/disable ACB clock gating.
Cherry-pick/manually port from dev-main
Bug 200647909
Change-Id: I4be4c14cc072fcccd91031a5a40321f5ff11f549
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420355
(cherry picked from commit c7c04d3a28c2eb0edc8e015dd0130fa50d3496c7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434464
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
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For Linux, limit the use of the cache to entries less than the page size, to
avoid potential problems with running out of CMA memory when allocating large,
contiguous slabs, as would be required for non-iommmuable chips.
Also, in nvgpu_pd_cache_do_free(), zero out entries only if iommu is in use
and PTE entries use the cache (since it's the prefetch of invalid PTEs by
iommu that needs to be avoided).
Bug 3093183
Bug 3100907
Change-Id: I363031db32e11bc705810a7e87fc9e9ac1dc00bd
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422039
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
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Running out of priv cmd buffer allocation capacity is typically a
recoverable "error" caused by extra pressure wrt. allocation sizes based
on number of inflight jobs chosen by userspace. These conditions return
-EAGAIN and further retries will succeed as long as the channel advances
with submitted jobs. Remove the unnecessary debug spew.
Bug 200641803
Bug 200651329
Change-Id: I4dfc38cfc3eb10d57ac11c1b7164c3d84f9034d3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2388799
(cherry picked from commit 29ad324f8226ed3326f5de9117b9115a15cdd032)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410069
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In gk20a_free_channel, destroy notifier_wq and
semaphore_wq
In __nvgpu_vm_remove, destroy the update_gmmu_lock mutex
Bug 200647668
Change-Id: Icbb4e626c0fa9fa2dcf1430b3112b51829b00e4f
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2414820
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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Reviewed-by: Satish Arora <satisha@nvidia.com>
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Large buffers being mapped to GMMU end up needing many
pages for the PTE tables. Allocating these pages one
by one can end up being a performance bottleneck, particularly
in the virtualized case.
Add support for page-sized PTEs to the existing PD cache:
- define NVGPU_PD_CACHE_SIZE, the allocation size for a new slab
for the PD cache, effectively set to 64K bytes
- Use the PD cache for any allocation < NVGPU_PD_CACHE_SIZE
- When freeing up cached entries, avoid prefetch errors by
invalidating the entry (memset to 0)
Bug 3093183
Bug 3100907
Change-Id: I2302a1dfeb056b9461159121bbae1be70524a357
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2401783
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
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The device node permission for the ctxsw should be set to "root:debug"
instead.
Bug 2823941
Change-Id: I523fdd298b70cac82c0a8d853f3e241a80a2ebf5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2372943
(cherry picked from commit 692eafdd03af2f7ab4164732f878d2699867ac63)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2392715
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Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Below change added capability check in the ioctl. nvgpu is advertising
the support for RESCHEDULE_RUNLIST for all processes even though it
fails the ioctl for non-realtime processes.
Clear the ioctl flag for RESCHEDULE_RUNLIST for non-realtime processes.
commit 838ba0a14d61f ("gpu: nvgpu: check capability for reschedule runlist submit flag")
Author: David Li <davli@nvidia.com>
Date: Tue Sep 12 18:37:00 2017 -0700
NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is only used by realtime
priority EGL context, which checks for CAP_SYS_NICE during context
creation in userspace, so it wasn't secure against unprivileged program
spoofing submit ioctl with this flag to stall GPU progress of others.
This flag does increase duration of submit by approx 16us,
mostly due to register accesses and PMU FIFO mutex.
Bug 2823941
Change-Id: Iecee3989e5af035264b1ed5c1aa9a8576dd90883
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2372957
(cherry picked from commit 864213ae55b009b0a026ac380b26276332f79177)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2392714
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Debugfs can be mounted with root-only permissions hence remove the extra
cap checks in the debugfs open calls for fifo_sched & ctxsw_ring.
Bug 2823941
Change-Id: I41668a887635f34897886b872ad435b183b85959
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2372982
(cherry picked from commit f34037a09f5996762c69bb4ce86751ed7df24ee7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2392713
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With MSS Nvlink set for force snoop, check for the coherency flag in
gmmu attribute and setting pte aperture to coherent type based on that
checking is not relevant.
coherent variable removed from nvgpu_gmmu_attrs struct.
Bug 200473147
Bug 3057980
Change-Id: Idf76cac901ef7c70faa2c4f7f11a046d94b9466a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013212
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry-picked from 4e1769097526e5203f7c18a663ab3c29f5568ae5
in rel-32)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2387272
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Tested-by: Aayush Rajoria <arajoria@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove the code that set default aperture mask as coherent.
MSS nvlink is set for force snoop, so default aperture mask is set as
non-coherent.
Bug 200473147
Bug 3057980
Change-Id: Ia8f826b8414826d2642f9c35c14ffba1cd0b9353
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011966
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry-picked from aec64d8f8bcda4a5270a16032005c7b5d1742656
in dev-main)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2387271
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Tested-by: Aayush Rajoria <arajoria@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Cycle stats and cycle stats snapshot ioctls have been moved to
debug node. Removing channel ioctls.
Bug 2660206
Bug 220464613
Change-Id: I3aecdf4a8310eeb38de2de5ac076048891afe436
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030992
(cherry picked from commit f20424ea6a7c6fcf977630e3e95d9e78418f13b8)
Signed-off-by: Gagan Grover <ggrover@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2092020
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
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Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS to debugger node, to
install/uninstall a buffer for cycle stats.
Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT to debugger
node, to attach/flush/detach a buffer for Mode-E streamout.
Those ioctls will apply to the first channel in the debug session.
Bug 2660206
Bug 200464613
Change-Id: I0b96d9a07c016690140292fa5886fda545697ee6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2002060
(cherry picked from commit 90b0bf98ac01d7fa24c40f6a1f20bfe5fa481d36)
Signed-off-by: Gagan Grover <ggrover@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2092008
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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On Volta, nvgpu needs to wait for explicit ACK from CTXSW while
setting FECS watchdog timeoout
This is manual port of the fixes 4d7e5026e38528b88a4a168eca9a8b180475b368
and ad89436b03428a42e43042b6a849c15843fdebc4 on dev-main since clean
cherry-pick is not possible due to huge file and structure differences.
Bug 200603566
Change-Id: Icba69998ab45eee5fdf2a29e1ac1067589301be6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2371708
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The timeout message of nvgpu_timeout_expired_msg() leaks
a stack value (%llx) in error log on timeout. As the format
expects 1 argument and none is given, fix this by specifying
the required argument.
Manual port of https://git-master.nvidia.com/r/c/linux-nvgpu/+/2205423
Bug 2780861
Bug 3051385
Change-Id: Ic223e4b79bde718108826f095740b10b54a5e84d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366452
(cherry picked from commit 372837506af77e2c5b8489ee2123292778abe75d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2370285
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sungwook Kim <sungwookk@nvidia.com>
Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
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File tu104/gr_tu104.c was added with commit f56874aec2 owing to
incorrect conflict resolution. Delete it.
Bug 200447167
Change-Id: I24648a3130bc76731c888328d5742229f6f6c928
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2371610
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Data can be speculativerly stored and
code flow can be hijacked.
To mitigate this problem insert a
speculation barrier.
Bug 200447167
Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08
Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972221
(cherry picked from commit f0762ed4831b3fe6cc953a4a4ec26c2537dcb69f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/1996052
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.
Bug 2833620
Change-Id: I3a424345aec6176a97dd20fb2c68a6e2faf955ad
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add pmu_idle_mask_1, pmu_idle_mask_2 and pmu_idle_mask_2_supp
Bug 2833620
Change-Id: Icceb99b48a227d32653fd9fbc3da9e27065e9fe2
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2334219
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Regenerating header from register generator
Bug 2833620
Change-Id: Idc8e922bb611ed5acae66b6ca38db4bb9c8a1904
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335263
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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There is no point to depend on strlen of second argument,
otherwise it could be a simple strcpy. Instead, let's make
it depending on sizeof(destination)
...and make sure that result is NUL-terminated, too
Bug 2973859
Change-Id: Ifc941fab07e503b7b980696950d65b8bb10bf4ff
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342281
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Currently, for platforms with canRailgate device characteristics disabled,
suspend can block as deterministic channels hold busy references. This
patch makes the change to first hold off any new jobs for deterministic
channels and then reverts back the busy references taken by those
channels. Following this, suspend also waits for the device to get idle
by waiting (with timeout) for the nvgpu's internal usage counter to be
come zero. This ensures there are no further jobs in progress and
allows the system to go into a suspend state.
Bug 200598228
Bug 2930266
Change-Id: Id02b4d41a9c2dd64303b2e2449dbed48c12aea4c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328489
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Background: There is a race that occurs when l2_fb_ops ioctl is
invoked. The race occurs as part of the flush() call while a
gk20_idle() is in progress.
This patch handles the race by making changes in the l2_fb_ops
ioctl itself. For cases where pm_runtime is disabled or railgate is
disabled, we allow this ioctl call to always go ahead as power is
assumed to be always on.
For the other case, we first check the status of g->power_on. In the
driver, g->power_on is set to true, once unrailgate is completed and is
set to false just before calling railgate.
For linux, the driver invokes gk20a_idle() but there is a delay after
which the call to the rpm_suspend()'s callback gets triggered. This
leads to a scenario where we cannot efficiently rely on the
runtime_pm's APIs to allow us to block an imminent suspend or exit if
the suspend is currently in progress. Previous attempts at solving this
has lead to ineffective solutions and make it much complicated to
maintain the code.
With regards to the above, this patch attempts to simplify the way this
can be solved. The patch calls gk20a_busy() when g->power_on = true.
This prevents the race with gk20a_idle(). Based on the rpm_resume and
rpm_suspend's upstream code, resume is prioritized over a suspend
unless a suspend is already in progress i.e. the delay period has been
served and the suspend invokes the callback. There is a very small
window for this to happen and the ioctl can then power_up the device as
evident from the gk20a_busy's calls.
A new function gk20a_check_poweron() is added. This function protects
the access to g->power_on via a mutex. By preventing a read from
happening simulatenously as a write on g->power_on, the likelihood of
an runtime_suspend triggering before a runtime_resume is further
reduced.
Bug 200507468
Change-Id: I5c02dfa8ea855732e59b759d167152cf45a1131f
Signed-off-by:Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299545
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Some of the APIs that access debugger register are not protected
from ELPG. This might trigger PRI access timeouts for corresponding
registers if GR engine is power gated.
Add gr_gk20a_elpg_protected_call() to protect against ELPG.
Bug 2820066
Change-Id: I467ea28aaea1c0e36c2d6aabce6a2daea6ee9911
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306383
(cherry picked from commit 0c0eb25ee798db3a8dcd8cab7db06312a220240e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313210
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When nvgpu_vm_unmap_sync fails, nvgpu_unmap_sync currently bails
out without decreasing the buffer refcount. This prevents from
releasing the buffer, in case a deferred job completes after the
timeout (which was observed 2 times during overnight
stress tests). This also means that the fixed address is not
re-useable.
Throw out a warning when nvgpu_vm_unmap_sync fails, but proceed
with decreasing refcount.
Bug 200578193
Change-Id: Ie0cc7caa7d12ca0a3b42123a5f7a28bda72dabbc
Signed-off-by: ddutta <ddutta@nvidia.com>
(cherry picked from commit a433f26d5bb1ec3253fc2655998b1ef7fb2847cb
in dev-main)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291352
Tested-by: Naveen Kumar S <nkumars@nvidia.com>
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blcg is always enabled by default and there is no need for disabling
this during gr init or gr reset.
Bug 2866010
Change-Id: Iaf17b7fdf05ad04fe435e1a1fda758deedc6484c
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303114
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Check kzalloc() allocations for failures and return
an error if an allocation fails.
Bug 2279948
Change-Id: I8a2c3b84904da897ad6118900c11489c8656c20f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020123
(cherry picked from commit fadd0014da39cb9498472494e52590db4b0bd7b9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298066
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When unbinding a channel from a tsg when virtual, vgpu_tsg_unbind_channel
would return an error if unbinding the channel on the guest side failed,
and did so before notifying the RM server of the unbind.
Later on in the recovery process, the guest OS would remove the channel from the
TSG's list, but this would leave the RM server with an out-of-date channel list.
Fix this by making the tsg_unbind_channel HAL optional and implemented only for vgpu:
the vgpu version now just notifies the RM server so that it can clean up its version
of the TSG; if vgpu, always call the tsg_unbind_channel HAL whether or not
the local unbind succeeded.
Minimal port from dev-main of https://git-master.nvidia.com/r/c/linux-nvgpu/+/2084029
Bug 2766920
Bug 200587845
Change-Id: I75bddf3a28ac20bf4fb7510ff64097a32c7eec3f
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287774
(cherry picked from commit 471c72c1efcc4fe6d547f556edf7773827fd2674)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289928
Reviewed-by: Thomas Steinle <tsteinle@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
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tsg_release hal_fn was missing in vgpu_gp10b causing
proper cleanup not to happen at the rm-server.
Bug 2766920
Bug 200587845
Change-Id: Ic0e57d1d37e0f92eea23087299c8c22c094199b0
Signed-off-by: aalex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1830192
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287773
(cherry picked from commit db765a8b898e1fd74a447081ea5e7de195ad3ce7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289927
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This patch help resolve the boot time failures happening with
pmu_exterr for porg. cg_enable can race with pmu_init thread,
cg_enable is moved post pmu init thread to avoid the above race.
Bug 200565050
Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959
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IOCTL definition specifies _IOR whereas _IOWR is required
Bug 200412642
Change-Id: I1093362ea621ee507d19236b859b7defb6dfa090
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1920071
(cherry picked from commit 79af49f86b90a80e20509a3b008440e9b9680cf9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287838
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Added two new IVC commands that set gr and fb mmu debug mode.
Bug 2586624
Change-Id: I358fb04713a9754fb209c0a90d02130dd4a1caf6
Reviewed-on: https://git-master.nvidia.com/r/2204980
(cherry picked from commit db4e5b09891aff075dfffb7cc2fe0630a71ab9a6)
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288347
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt.
If channel is enabled multiple times by userspace, then ref count is
updated accordingly. There is an expectation that enable/disable
calls are balanced for setting channel's mmu debug mode.
When unbinding the channel, decrease refcnt for the channel until it
reaches 0.
Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it
can be retrieved from ch.
Bug 2515097
Bug 2713590
Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184702
(cherry picked from commit f422aee39387a5aa337de69cc21a67f16697ae0e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208772
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
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Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL
in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in
NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
Bug 2515097
Bug 2713590
Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115785
(cherry picked from commit 8057514a9f7fc5f175e2e0571dfa91d78ebb6410)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208771
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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Add accessors for NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and
NV_PFB_PRI_MMU_DEBUG_CTRL
Bug 2515097
Bug 2713590
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Change-Id: Ieadee041854bc9a17721b5b17938a106e205517f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208770
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.
Bug 2515097
Bug 2713590
Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
(cherry picked from commit a1248d87fe6e20aab3e5f2e0764f9fe8d80d0552)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208769
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
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NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b
FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that
userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
ioctl for gv11b.
Bug 2515097
Bug 2713590
Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115019
(cherry picked from commit 3f9ea7dfd854d748c3d0fae52e2981bae1c8e650)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208768
Reviewed-by: Automatic_Commit_Validation_User
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
But 2713590
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When the TSG is initialized, the timeslice is initially set to 0,
which is a flag for using the default timeslice.
The sched get_params ioctl was returning 0 in this case; instead,
call gk20a_tsg_get_timeslice() to get the correct value.
Bug 2818547
Change-Id: I29fde48240098074de12e9a9a3e347e4042a64e8
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283962
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gk20a_pm_runtime_suspend can fail and invoke gk20a_pm_finalize_poweron
that can cause double mapping of the usermode mmap region via
io_remap_pfn_range(). Avoid this by using a boolean variable to track
whether the region is already mapped.
Bug 2707416
Bug 200582208
Change-Id: I4d8cbe427400a5b986348a19af145367cc08ffc6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2229312
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283801
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Add struct nvgpu_sched_ctrl to struct gk20a
Delete struct gk20a_sched_ctrl from struct nvgpu_os_linux
Update sched_ctrl functions to use the nvgpu_sched_ctrl struct
Bug 200576520
Change-Id: I35b13219e5ef0a8a03333dfd7d46e1d308aec541
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279152
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
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Nvgpu flags will miss fecs when nvgpu poweron. We have to add this
fecs in flag when we are seeing trace was initialized before.
Bug 2629615
Change-Id: I7815af7bf66a7a103a14cd375a3fd394243035b1
Signed-off-by: Jeremy Ho <jeremyh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279244
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Set platform atomic attribute flag.
bug 200580236
Change-Id: I06fd0cf363886922ad5145837004d04e35383470
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016078
(cherry picked from commit ef5aac37d9a4531fecd1f1dae0581a2bd28f164d)
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274970
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Support following changes related to platform atomic feature
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ
In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege,
so atomic mode register bits cannot be updated from kernel code.
atomic capability and atomic_sys_ncoh_mode bits are copied from
fb mmu_ctrl to gpcs_mmu_ctrl register.
new tu104 hal for fb_enable_nvlink function.
bug 200580236
Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013481
(cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1)
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274932
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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