summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAge
* gpu: nvgpu: Do not reset FBTerje Bergstrom2018-08-24
| | | | | | | | | | | | | | | | | The fields for resetting FB have been defunct since Maxwell, and FB and related units are powered up by default. Remove accessing the resets. JIRA NVGPU-1063 Change-Id: I3de23134e56408cc32321717d55d23a4d7af3140 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801414 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Fix MISRA 15.6 violationsSrirangan2018-08-23
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Iba8bf3a69ebba04e30ad3d0d7d1db3e183ecbb3d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803559 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: Fix MISRA 15.6 violationsSrirangan2018-08-23
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I4d9933c51a297a725f48cbb15520a70494d74aeb Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800833 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reduce structure padding wasteNicolin Chen2018-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gk20a_init_fifo_setup_sw_common() function allocates memory of schannel_gk20a and tsg_gk20a tructures for all 512 channels: Size Caller Module Pages Type 749568 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=182 vmalloc 602112 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=146 vmalloc This change just simply reorgnizes the member defines in those two structures to reduce padding waste. After this change: Size Caller Module Pages Type 733184 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=178 vmalloc 585728 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=142 vmalloc In summary, it saves 8 pages in 32KB memory. Bug 2327574 Bug 2284925 Change-Id: I06693e0fef516a145b48dd3a05d756c0feaf3ba5 Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803358 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations [3/3]Alex Waterman2018-08-22
| | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This change removes the usage of the '__a' argument scattered throughout the nvgpu allocator code. JIRA NVGPU-1029 Change-Id: I553a66a3d7d2c6bb21ba0a45e29a1d01f7b89f49 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803353 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations [2/3]Alex Waterman2018-08-22
| | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This change removes the usage of the '__a' argument scattered throughout the nvgpu allocator code. JIRA NVGPU-1029 Change-Id: Ic39213ab800e92c6815ce5b9deb22520aa6d0630 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803352 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations [1/3]Alex Waterman2018-08-22
| | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This change removes the usage of the '__a' argument scattered throughout the nvgpu allocator code. JIRA NVGPU-1029 Change-Id: I5a9b8a3e0602ba4d519ca19080951402b6f3287d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803351 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Scrub gv11b vgpu HALsTerje Bergstrom2018-08-22
| | | | | | | | | | | | | | | | vgpu does not have access to registers. Go through vgpu gv11b HAL and find all functions that would access a register. Replace each of them with a NULL. Change-Id: I26e47c49b61dd002f5f5906aa2fdda7aa248d1c3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803276 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Scrub gp10b vgpu HALsTerje Bergstrom2018-08-22
| | | | | | | | | | | | | | | | vgpu does not have access to registers. Go through vgpu gp10b HAL and find all functions that would access a register. Replace each of them with a NULL. Change-Id: I32e91c85f128958ba03d2b8303fa9ff11615498f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1798507 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: switch gk20a nonstall ops to #definesScott Long2018-08-22
| | | | | | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops enums by replacing them with with corresponding #defines. Because these values can be used in expressions that require unsigned values (e.g. bitwise OR) we cannot use enums. The g->ce2.isr_nonstall() function was previously returning an int that was a combination of gk20a_nonstall_ops enum bits which led to the violations. JIRA NVGPU-650 Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796242 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Changed enum gmmu_pgsz_gk20a into macrosAmulya2018-08-22
| | | | | | | | | | | | | | | | | | Changed the enum gmmu_pgsz_gk20a into macros and changed all the instances of it. The enum gmmu_pgsz_gk20a was being used in for loops, where it was compared with an integer. This violates MISRA rule 10.4, which only allows arithmetic operations on operands of the same essential type category. Changing this enum into macro will fix this violation. JIRA NVGPU-993 Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Depend on PM_DEVFREQ if GK20A_DEVFREQ is selectedMikko Perttunen2018-08-22
| | | | | | | | | | | | | | | | | | | | The GK20A_DEVFREQ requires the kernel devfreq framework (PM_DEVFREQ) to be enabled. Specify this in the Kconfig file. bug 200434446 Change-Id: I9abff330a064ec2835a8a013ea6b9e4ebc6534f1 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790315 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: fix MISRA 10.4 violationsSai Nikhil2018-08-22
| | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fix violations where an arithmetic operation is performed on signed and unsigned int types. Jira NVGPU-992 Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1789425 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: Fix nonpes aware tpc mappingPhilemon Gardet2018-08-22
| | | | | | | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG are indexed on nonpes aware tpc. Bug 2096878 Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea Signed-off-by: Philemon Gardet <pgardet@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1783046 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* scripts: rfr: Add file supportAlex Waterman2018-08-22
| | | | | | | | | | | | | | | | Add support for reading a file full of commit IDs/URLs. This makes generating an RFR from a long list of commits easier in some cases. Change-Id: Id71173853e29d951048e8c3394ffce5d8b1eeb52 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1576523 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove falcon header usage in nvlinkTejal Kudav2018-08-22
| | | | | | | | | | | | | | | | | For nvlink, we need to use minion registers instead of generic falcon registers. JIRA NVGPU-966 Change-Id: I850d2e2a4475394c37d2253c5034713c78439bd0 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795086 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: pmu: Fix MISRA 15.6 violationsSrirangan2018-08-21
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I497fbdb07bb2ec5a404046f06db3c713b3859e8e Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Force the PMU VM to use 128K large pages (gm20b)Alex Waterman2018-08-21
| | | | | | | | | | | | | | | Add a WAR for gm20b that allows us to force the PMU VM to use 128K large pages. For some reason setting the small page size to 64K breaks the PMU boot. Unclear why. Bug needs to be filed and fixed. Once fixed this patch can and should be reverted. Bug 200105199 Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1782769 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Set default large page size to 64K for gm20bAlex Waterman2018-08-21
| | | | | | | | | | | | | | | | | | | | | | | | Since all userspace apps are using 64K pages these days it makes sense to set the default large page size to 64K. This in turn causes the PDE coverage field to be set to 64M in the GPU characteristics field. While it would therefor be possible to create a VM with a PDE coverage that's larger than 64M (128M if you set the large page size to 128K) this will make the defaults work properly. This in turn fixes a CUDA issue where CUDA tries to determine the PDE coverage (and correspondingly a minimum alignemnt) from the characteristics IOCTL. Bug 200105199 Change-Id: Iee3c213f1b81d8628571f46c7ad5e16fbfe07499 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781088 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: MISRA 10.3-Conversions to/from an enumAmulya2018-08-21
| | | | | | | | | | | | | | | | | Fix violations where the conversion is from a non-enum type to enum type or vice-versa. JIRA NVGPU-659 Change-Id: I45f43c907b810cc86b2a4480809d0c6757ed3486 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1802322 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: MISRA 10.3 Conversions to/from charSai Nikhil2018-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.3 states that the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. We have cases where we are converting to/from char and non char types and this fix 10.3 violations resulting from these conversions. This also fix violations in conversions between s8 and non-s8 types as s8 can be typedefed as char. Jira NVGPU-1010 Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801613 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use BIT64() for NVGPU_L3_ALLOC_BITAlex Waterman2018-08-21
| | | | | | | | | | | | | This bit is in the upper half a 64bit field (bit 36). As such the BIT64() macro must now be used. Change-Id: Id91ee982ca91be4b6a4f61ded2cf1bc98b3519d1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797198 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add BIT32() and BIT64() macrosAlex Waterman2018-08-21
| | | | | | | | | | | | | | | | | Provide both a BIT32() and BIT64() macro so that bit fields can be sized appropriately. The existing BIT() macro is now deprecated and should not be used. Instead use the explicitly sized macros. JIRA NVGPU-781 Change-Id: I9309bd0cda8f811934b7388990e12d0e02436eb0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797197 Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* scripts: rfr: support multiple recipientsKonsta Holtta2018-08-21
| | | | | | | | | | | | | | | | | | Add an argument (-t, --to) to specify additional recipients for the review email. Sometimes it's useful to highlight some people explicitly or in addition to the usual nvgpu core list. In the future, we might consider adding some heuristics for less typing (such as adding @nvidia.com automatically). For now the addresses have to be complete. Change-Id: I0e4ce5974a7a2f3db6eacc7128b825d20d6fd57c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768066 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix memory leak in failure conditionPreetha Chandru R2018-08-21
| | | | | | | | | | | | | | | | | | This change frees tsg_private structure in nvgpu_ioctl_tsg_open() when gk20a_busy() fails and avoids a memory leak. Bug 2268533 JIRA NVGPU-1016 Change-Id: I0428cc40e042b881537f7cb597e5ebeaad815b32 Signed-off-by: Preetha Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800955 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove switching alt_clk to slowclkTejal Kudav2018-08-21
| | | | | | | | | | | | | | | | | | | | | nvlink alt_clk switch defaults to slowclk; the init value of register field is slowclk. So we need not program the register field 'clk_alt_switchfinalsel'. Also the code lines were not taking effect as the value is not written back to the register. JIRA NVGPU-966 Change-Id: I75904e94a8e113c17fb3bf8c414174c549ad893e Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795050 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: t19x: Update pmu ucode version.Deepak Goyal2018-08-20
| | | | | | | | | | | | | | | | | | | | | This fixes PMU halt caused due to IMEM miss exception when calling apCtrlEnable/apCtrlDisable. IMEM miss exception occurs as overlay containing these functions is not loaded in the PMU's IMEM. This version loads the overlays before calling these functions. Bug 2167968. Change-Id: I37c75c59b1b545571d2bf94f07a7ecb3a814af54 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801250 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse HAL to commonTerje Bergstrom2018-08-20
| | | | | | | | | | | | Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
* gpu: nvgpu: common: Fix MISRA 15.6 violationsSrirangan2018-08-20
| | | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795845 Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Populate GM20b clock debugfsAlex Frid2018-08-17
| | | | | | | | Change-Id: I106a4e7de010d169c890e6b8dd28b3e0841b83a2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHEAnup Mahindre2018-08-17
| | | | | | | | | | | | | | | | | Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has a broken implementation. Bug 200439908 Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800797 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: move the posix dir to osAlex Waterman2018-08-17
| | | | | | | | | | | Since the posix code is supporting a particular OS this code should belong under os/ not common/. Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800658 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove code to save hshub config regsTejal Kudav2018-08-17
| | | | | | | | | | | | | | | | | We do not use the stored hshub_config* register values. Remove these redundant fields from nvlink data structure too. This also allows us to not #include a FB hardware header in nvlink. JIRA NVGPU-966 Change-Id: I3be169a958ec17370b55889d1e1fbabb887a79fd Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794955 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: mm: Fix MISRA 15.6 violationsSrirangan2018-08-17
| | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Ieeecf719dca9acc1a116d2893637bf770caf4f5b Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794241 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: mm: Fix MISRA 15.6 violationsSrirangan2018-08-16
| | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I129cc170d27c7f1f2e193b326b95ebbe3c75ebab Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795600 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ltc HAL to commonTerje Bergstrom2018-08-16
| | | | | | | | | | | | Move implementation of ltc HAL to common/ltc. JIRA NVGPU-956 Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1798461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use correct aperture for perf inst_blockAlex Waterman2018-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | The perf inst block was being treated as vidmem (LFB - local framebuffer) always, regardless of the type of nvgpu_mem used for the instance block. On dGPUs this was fine becasue we always allocate instance blocks from vidmem. Inst blocks are allocated with nvgpu_dma_alloc() which chooses vidmem if vidmem is present, otherwise falls back to sysmem. When the above fall back logic was deleted this caused inst blocks to always be allocated in sysmem, even for dGPUs. This isn't a problem in an of itself but the logic for the perf instance block bind operation assumed a VIDMEM inst_block. Thus this patch uses the nvgpu_aperture_mask() function to correctly program the required aperture target for the perf's inst block bind operation. JIRA NVGPU-990 Change-Id: If6f09a743ee2ad47a6dbfa28cb7c61f1461fd8a7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796388 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use NVLINK config instead of has_physical_modeAlex Waterman2018-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag - has_physical_mode - doesn't seem to do much other than force the PTE/PDE and inst block addresses to be physical instead of potentially IOMMUed. There is a reason to do this on volta (nvlink not being IOMMU'able being the primary reason) but this flag is too general it seems. The flag was being enabled on all native platforms. The problem is that some page tables (the maxwell small page directories) could be larger than 4KB which meant that the allocation used for them could be potentially discontiguous. Discontiguous page directories obviously is incorrect. This patch deletes the has_physical_mode flag and instead replaces the places where it's checked with a check for nvlink being enabled. Since we _do_ want to program phyiscal PDEs and PTEs for NVLINK devices (regardless of IOMMU status they always access memory by physical address) we need a check for NVLINK state. Bug 200414723 Change-Id: I09ad86b12d8aabcf9648a22503f4747fd63514dd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792163 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: ecc sysfs support for vgpuKyle Guo2018-08-15
| | | | | | | | | | | | | | - fetch ecc info from RM server and create sysfs nodes - new file ecc_vgpu.c for platform-independent code - add 2 new commands: GET_ECC_INFO and GET_ECC_COUNTER_VALUE JIRA EVLR-2590 Change-Id: I040a9fcd23326e432ca93e9a028319f9c1c570f0 Signed-off-by: Kyle Guo <kyleg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777428 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move therm HAL to commonTerje Bergstrom2018-08-14
| | | | | | | | | | | | | | | Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* userspace: Enable nvgpu-next buildAnup Mahindre2018-08-14
| | | | | | | | | | | | | | | Added targets in corresponding makefiles/sources to enable building nvgpu-next from userspace. JIRA NVGPU-1015 Change-Id: Ia358162e14205035e4552bfb7f32825c7de48fc2 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792003 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: unpowergate GPU in ioctl_tsg_open()Preetham Chandru Ramchandra2018-08-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvgpu_ioctl_tsg_open() does not make sure that GPU is unpowergated. Due to this it leads to kernel panic when GPU registers are accessed when powergated. __gk20a_warn_on_no_regs+0x38/0x58 [nvgpu] __nvgpu_readl+0x74/0xc8 [nvgpu] nvgpu_readl+0x28/0x60 [nvgpu] xxxxx_ce_get_num_pce+0x28/0x70 [nvgpu] xxxxx_fifo_init_eng_method_buffers+0x64/0x1c0 [nvgpu] gk20a_tsg_open+0x110/0x1e0 [nvgpu] nvgpu_ioctl_tsg_open+0x88/0x100 [nvgpu] gk20a_ctrl_dev_ioctl+0x734/0x2388 [nvgpu] do_vfs_ioctl+0xc4/0x918 SyS_ioctl+0x94/0xa8 This change fixes this issue by calling gk20a_busy()/gk20a_idle() in nvgpu_ioctl_tsg_open() Bug 2268533 JIRA NVGPU-1016 Change-Id: I578289e7eb60295d6b6169b754a5cc60f7546fd5 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794324 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: MISRA 10.4 enum fixesAmulya2018-08-14
| | | | | | | | | | | | | | | | MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move priv_ring HAL to commonTerje Bergstrom2018-08-13
| | | | | | | | | | | | | | | | | Move implementation of priv_ring HAL to common/priv_ring. Implement two new HAL APIs to remove illegal dependencies: enable_priv_ring and enum_ltc. As enum_ltc can be implemented only gm20b onwards, bump gk20a implementation to base on gm20b. JIRA NVGPU-964 Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797025 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export APIs to handle sw methodsDeepak Nibade2018-08-13
| | | | | | | | | | | | | | | | | | | | Export below APIs in gv11b/gr_gv11b.h header so that they can be called from other files too gr_gv11b_set_shader_cut_collector() gr_gv11b_set_go_idle_timeout() gr_gv11b_set_coalesce_buffer_size() gr_gv11b_set_tex_in_dbg() gr_gv11b_set_skedcheck() gv11b_gr_set_shader_exceptions() Bug 2260560 Change-Id: Ic85e35bc223c88c2a54fab09851b8a957b4d1153 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: allow all sizes in access fb API"Deepak Nibade2018-08-13
| | | | | | | | | | | | | | | | | This reverts commit b79c350d68bac79ec9ed80ef5f19f15a0d0eedf4. Underlying PRAMIN infrastructure enforces 4 byte aligned size only, so the API should enforce that too Bug 2285052 Change-Id: I2b4a209edd479d72992708b35e1d52940ff20637 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795653 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make userspace build stricterTerje Bergstrom2018-08-11
| | | | | | | | | | | | | | | Add a bunch of build warning flags to make userspace builds mimic the strictness of standard tmake builds. Change-Id: If6f1f716f2bb2d64d240a66be2cb3aae814f24d0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796239 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: module.c should #include its own hdrTerje Bergstrom2018-08-11
| | | | | | | | | | | | | | | userspace/src/module.c should #include its own <unit/module.h> to get declarations for the functions defined. Change-Id: Icff647f19468607ebfb757360b83ce9f133bd5ec Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797034 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add missing braces in nvgpu_mem.cTerje Bergstrom2018-08-11
| | | | | | | | | | | | | | | | When built with -Wmissing-braces, compiler complains about the missing braces in nvgpu_mem_rd_n, nvgpu_mem_wr_n and nvgpu_memset. Add the braces to satisfy compiler and to fix related MISRA C violations. Change-Id: Ibe3606dc59317f8230cea57cfea8d0fe5af641d6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796238 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add U64() and U32() macrosAlex Waterman2018-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These macros exist to make integer literals used in certain arithmetic operations explicitly large enough to hold the results of that operation. The following is an example of this. In MISRA the destination for a bitwise shift must be able to hold the number of bits shifted. Otherwise the results are undefined. For example: 256U << 20U This is valid C code but the results of this _may_ be undefined if the size of an unsigned by default is less than 24 bits (i.e 16 bits). The MISRA misra checker sees the 256U and determines that the 256U fits in a 16 bit data type (i.e a u16). Since a u16 has 16 bits, which is less than 20, this is an issue. Of course most compilers these days use 32 bits for the default unsigned type this is not a requirement. Moreover this name problem could exist like so: 0xfffffU << 40U The 0xfffffU is a 32 bit unsigned type; but we are shifting 40 bits which overflows the 32 bit data type. So in this case we need an explicit cast to 64 bits in order to prevent undefined behavior. Change-Id: If2433fb8c44df0c714487fa3b6b056fc84570df7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795391 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-28 19:44:48 -0400