diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index c4dd81dd..979d454e 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -76,7 +76,14 @@ enum { | |||
76 | TEGRA_VGPU_CMD_REG_OPS, | 76 | TEGRA_VGPU_CMD_REG_OPS, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, | 78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, |
79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE | 79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE, |
80 | RESVD1, | ||
81 | RESVD2, | ||
82 | RESVD3, | ||
83 | RESVD4, | ||
84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, | ||
85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, | ||
86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, | ||
80 | }; | 87 | }; |
81 | 88 | ||
82 | struct tegra_vgpu_connect_params { | 89 | struct tegra_vgpu_connect_params { |
@@ -312,6 +319,20 @@ struct tegra_vgpu_channel_timeslice_params { | |||
312 | u32 timeslice_us; | 319 | u32 timeslice_us; |
313 | }; | 320 | }; |
314 | 321 | ||
322 | enum { | ||
323 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, | ||
324 | TEGRA_VGPU_CTXSW_MODE_CTXSW, | ||
325 | }; | ||
326 | |||
327 | struct tegra_vgpu_channel_set_ctxsw_mode { | ||
328 | u64 handle; | ||
329 | u32 mode; | ||
330 | }; | ||
331 | |||
332 | struct tegra_vgpu_channel_free_hwpm_ctx { | ||
333 | u64 handle; | ||
334 | }; | ||
335 | |||
315 | struct tegra_vgpu_cmd_msg { | 336 | struct tegra_vgpu_cmd_msg { |
316 | u32 cmd; | 337 | u32 cmd; |
317 | int ret; | 338 | int ret; |
@@ -342,6 +363,8 @@ struct tegra_vgpu_cmd_msg { | |||
342 | struct tegra_vgpu_channel_priority_params channel_priority; | 363 | struct tegra_vgpu_channel_priority_params channel_priority; |
343 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | 364 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; |
344 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | 365 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; |
366 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | ||
367 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | ||
345 | char padding[192]; | 368 | char padding[192]; |
346 | } params; | 369 | } params; |
347 | }; | 370 | }; |