3 files changed, 171 insertions, 9 deletions

diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 280ca9c0..c4dd81dd 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -1,7 +1,7 @@
 /*
  * Tegra GPU Virtualization Interfaces to Server
  *
- * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -74,7 +74,9 @@ enum {
         TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
         TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
         TEGRA_VGPU_CMD_REG_OPS,
-        TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY
+        TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
+        TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE,
+        TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE
 };
 
 struct tegra_vgpu_connect_params {
@@ -84,6 +86,7 @@ struct tegra_vgpu_connect_params {
 
 struct tegra_vgpu_channel_hwctx_params {
         u32 id;
+        u64 pid;
         u64 handle;
 };
 
@@ -298,6 +301,17 @@ struct tegra_vgpu_channel_priority_params {
         u32 priority;
 };
 
+/* level follows nvgpu.h definitions */
+struct tegra_vgpu_channel_runlist_interleave_params {
+        u64 handle;
+        u32 level;
+};
+
+struct tegra_vgpu_channel_timeslice_params {
+        u64 handle;
+        u32 timeslice_us;
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -326,6 +340,8 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_sm_debug_mode sm_debug_mode;
                 struct tegra_vgpu_reg_ops_params reg_ops;
                 struct tegra_vgpu_channel_priority_params channel_priority;
+                struct tegra_vgpu_channel_runlist_interleave_params channel_interleave;
+                struct tegra_vgpu_channel_timeslice_params channel_timeslice;
                 char padding[192];
         } params;
 };
diff --git a/include/trace/events/gk20a.h b/include/trace/events/gk20a.h
index 461ff6e8..23b5b642 100644
--- a/include/trace/events/gk20a.h
+++ b/include/trace/events/gk20a.h
@@ -387,7 +387,7 @@ TRACE_EVENT(gk20a_as_ioctl_get_va_regions,
 TRACE_EVENT(gk20a_mmu_fault,
             TP_PROTO(u32 fault_hi, u32 fault_lo,
                      u32 fault_info,
-                     u32 instance,
+                     u64 instance,
                      u32 engine_id,
                      const char *engine,
                      const char *client,
@@ -398,7 +398,7 @@ TRACE_EVENT(gk20a_mmu_fault,
                          __field(u32, fault_hi)
                          __field(u32, fault_lo)
                          __field(u32, fault_info)
-                         __field(u32, instance)
+                         __field(u64, instance)
                          __field(u32, engine_id)
                          __field(const char *, engine)
                          __field(const char *, client)
@@ -414,7 +414,7 @@ TRACE_EVENT(gk20a_mmu_fault,
                        __entry->client = client;
                        __entry->fault_type = fault_type;
                        ),
-            TP_printk("fault=0x%x,%08x info=0x%x instance=0x%x engine_id=%d engine=%s client=%s type=%s",
+            TP_printk("fault=0x%x,%08x info=0x%x instance=0x%llx engine_id=%d engine=%s client=%s type=%s",
                       __entry->fault_hi, __entry->fault_lo,
                       __entry->fault_info, __entry->instance, __entry->engine_id,
                       __entry->engine, __entry->client, __entry->fault_type)
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 442a84ac..64ac45b5 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -351,6 +351,28 @@ struct nvgpu_gpu_get_buffer_info_args {
         };
 };
 
+#define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT               16
+#define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TSC              1
+#define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_JIFFIES          2
+#define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TIMEOFDAY        3
+
+struct nvgpu_gpu_get_cpu_time_correlation_sample {
+        /* gpu timestamp value */
+        __u64 cpu_timestamp;
+        /* raw GPU counter (PTIMER) value */
+        __u64 gpu_timestamp;
+};
+
+struct nvgpu_gpu_get_cpu_time_correlation_info_args {
+        /* timestamp pairs */
+        struct nvgpu_gpu_get_cpu_time_correlation_sample samples[
+                NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT];
+        /* number of pairs to read */
+        __u32 count;
+        /* cpu clock source id */
+        __u32 source_id;
+};
+
 #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \
         _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args)
 #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \
@@ -397,11 +419,13 @@ struct nvgpu_gpu_get_buffer_info_args {
         _IO(NVGPU_GPU_IOCTL_MAGIC, 22)
 #define NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS \
         _IO(NVGPU_GPU_IOCTL_MAGIC, 23)
-
+#define NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO \
+        _IOWR(NVGPU_GPU_IOCTL_MAGIC, 24, \
+                        struct nvgpu_gpu_get_cpu_time_correlation_info_args)
 #define NVGPU_GPU_IOCTL_LAST            \
-        _IOC_NR(NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS)
+        _IOC_NR(NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO)
 #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE    \
-        sizeof(struct nvgpu_gpu_prepare_compressible_read_args)
+        sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args)
 
 /*
  * /dev/nvhost-tsg-gpu device
@@ -834,6 +858,34 @@ struct nvgpu_channel_wdt_args {
 #define NVGPU_IOCTL_CHANNEL_DISABLE_WDT         1
 #define NVGPU_IOCTL_CHANNEL_ENABLE_WDT          2
 
+/*
+ * Interleaving channels in a runlist is an approach to improve
+ * GPU scheduling by allowing certain channels to appear multiple
+ * times on the runlist. The number of times a channel appears is
+ * governed by the following levels:
+ *
+ * low (L)   : appears once
+ * medium (M): if L, appears L times
+ *             else, appears once
+ * high (H)  : if L, appears (M + 1) x L times
+ *             else if M, appears M times
+ *             else, appears once
+ */
+struct nvgpu_runlist_interleave_args {
+        __u32 level;
+        __u32 reserved;
+};
+#define NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW      0
+#define NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM   1
+#define NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH     2
+#define NVGPU_RUNLIST_INTERLEAVE_NUM_LEVELS     3
+
+/* controls how long a channel occupies an engine uninterrupted */
+struct nvgpu_timeslice_args {
+        __u32 timeslice_us;
+        __u32 reserved;
+};
+
 #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD        \
         _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args)
 #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \
@@ -876,9 +928,13 @@ struct nvgpu_channel_wdt_args {
         _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args)
 #define NVGPU_IOCTL_CHANNEL_WDT \
         _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args)
+#define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \
+        _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args)
+#define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \
+        _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args)
 
 #define NVGPU_IOCTL_CHANNEL_LAST        \
-        _IOC_NR(NVGPU_IOCTL_CHANNEL_WDT)
+        _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_TIMESLICE)
 #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args)
 
 /*
@@ -1159,4 +1215,94 @@ struct nvgpu_as_map_buffer_batch_args {
 #define NVGPU_AS_IOCTL_MAX_ARG_SIZE     \
         sizeof(struct nvgpu_as_map_buffer_ex_args)
 
+
+/*
+ * /dev/nvhost-ctxsw-gpu device
+ *
+ * Opening a '/dev/nvhost-ctxsw-gpu' device node creates a way to trace
+ * context switches on GR engine
+ */
+
+#define NVGPU_CTXSW_IOCTL_MAGIC 'C'
+
+#define NVGPU_CTXSW_TAG_SOF                     0x00
+#define NVGPU_CTXSW_TAG_CTXSW_REQ_BY_HOST       0x01
+#define NVGPU_CTXSW_TAG_FE_ACK                  0x02
+#define NVGPU_CTXSW_TAG_FE_ACK_WFI              0x0a
+#define NVGPU_CTXSW_TAG_FE_ACK_GFXP             0x0b
+#define NVGPU_CTXSW_TAG_FE_ACK_CTAP             0x0c
+#define NVGPU_CTXSW_TAG_FE_ACK_CILP             0x0d
+#define NVGPU_CTXSW_TAG_SAVE_END                0x03
+#define NVGPU_CTXSW_TAG_RESTORE_START           0x04
+#define NVGPU_CTXSW_TAG_CONTEXT_START           0x05
+#define NVGPU_CTXSW_TAG_INVALID_TIMESTAMP       0xff
+#define NVGPU_CTXSW_TAG_LAST                    \
+        NVGPU_CTXSW_TAG_INVALID_TIMESTAMP
+
+struct nvgpu_ctxsw_trace_entry {
+        __u8 tag;
+        __u8 vmid;
+        __u16 seqno;            /* sequence number to detect drops */
+        __u32 context_id;       /* context_id as allocated by FECS */
+        __u64 pid;              /* 64-bit is max bits of different OS pid */
+        __u64 timestamp;        /* 64-bit time */
+};
+
+#define NVGPU_CTXSW_RING_HEADER_MAGIC 0x7000fade
+#define NVGPU_CTXSW_RING_HEADER_VERSION 0
+
+struct nvgpu_ctxsw_ring_header {
+        __u32 magic;
+        __u32 version;
+        __u32 num_ents;
+        __u32 ent_size;
+        volatile __u32 drop_count;      /* excluding filtered out events */
+        volatile __u32 write_seqno;
+        volatile __u32 write_idx;
+        volatile __u32 read_idx;
+};
+
+struct nvgpu_ctxsw_ring_setup_args {
+        __u32 size;     /* [in/out] size of ring buffer in bytes (including
+                           header). will be rounded page size. this parameter
+                           is updated with actual allocated size. */
+};
+
+#define NVGPU_CTXSW_FILTER_SIZE (NVGPU_CTXSW_TAG_LAST + 1)
+#define NVGPU_CTXSW_FILTER_SET(n, p) \
+        ((p)->tag_bits[(n) / 64] |=  (1 << ((n) & 63)))
+#define NVGPU_CTXSW_FILTER_CLR(n, p) \
+        ((p)->tag_bits[(n) / 64] &= ~(1 << ((n) & 63)))
+#define NVGPU_CTXSW_FILTER_ISSET(n, p) \
+        ((p)->tag_bits[(n) / 64] &   (1 << ((n) & 63)))
+#define NVGPU_CTXSW_FILTER_CLR_ALL(p)    memset((void *)(p), 0, sizeof(*(p)))
+#define NVGPU_CTXSW_FILTER_SET_ALL(p)    memset((void *)(p), ~0, sizeof(*(p)))
+
+struct nvgpu_ctxsw_trace_filter {
+        __u64 tag_bits[(NVGPU_CTXSW_FILTER_SIZE + 63) / 64];
+};
+
+struct nvgpu_ctxsw_trace_filter_args {
+        struct nvgpu_ctxsw_trace_filter filter;
+};
+
+#define NVGPU_CTXSW_IOCTL_TRACE_ENABLE \
+        _IO(NVGPU_CTXSW_IOCTL_MAGIC, 1)
+#define NVGPU_CTXSW_IOCTL_TRACE_DISABLE \
+        _IO(NVGPU_CTXSW_IOCTL_MAGIC, 2)
+#define NVGPU_CTXSW_IOCTL_RING_SETUP \
+        _IOWR(NVGPU_CTXSW_IOCTL_MAGIC, 3, struct nvgpu_ctxsw_ring_setup_args)
+#define NVGPU_CTXSW_IOCTL_SET_FILTER \
+        _IOW(NVGPU_CTXSW_IOCTL_MAGIC, 4, struct nvgpu_ctxsw_trace_filter_args)
+#define NVGPU_CTXSW_IOCTL_GET_FILTER \
+        _IOR(NVGPU_CTXSW_IOCTL_MAGIC, 5, struct nvgpu_ctxsw_trace_filter_args)
+#define NVGPU_CTXSW_IOCTL_POLL \
+        _IO(NVGPU_CTXSW_IOCTL_MAGIC, 6)
+
+#define NVGPU_CTXSW_IOCTL_LAST            \
+        _IOC_NR(NVGPU_CTXSW_IOCTL_POLL)
+
+#define NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE  \
+        sizeof(struct nvgpu_ctxsw_trace_filter_args)
+
 #endif