diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 504a31ad..ef4c36d9 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -114,22 +114,22 @@ enum { | |||
114 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */ | 114 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */ |
115 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */ | 115 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */ |
116 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */ | 116 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */ |
117 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, | 117 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */ |
118 | TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, | 118 | TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, |
119 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, | 119 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, |
120 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, | 120 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, |
121 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ | 121 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ |
122 | TEGRA_VGPU_ATTRIB_L2_SIZE = 8, | 122 | TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */ |
123 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, | 123 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, |
124 | TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, | 124 | TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, |
125 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, | 125 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, |
126 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, | 126 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, |
127 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, | 127 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, |
128 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, | 128 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, |
129 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, | 129 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */ |
130 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, | 130 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */ |
131 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, | 131 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */ |
132 | TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, | 132 | TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */ |
133 | TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, | 133 | TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, |
134 | TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, | 134 | TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, |
135 | TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ | 135 | TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ |
@@ -411,6 +411,12 @@ struct tegra_vgpu_constants_params { | |||
411 | u32 num_channels; | 411 | u32 num_channels; |
412 | u32 golden_ctx_size; | 412 | u32 golden_ctx_size; |
413 | u32 zcull_ctx_size; | 413 | u32 zcull_ctx_size; |
414 | u32 l2_size; | ||
415 | u32 ltc_count; | ||
416 | u32 cacheline_size; | ||
417 | u32 slices_per_ltc; | ||
418 | u32 comptags_per_cacheline; | ||
419 | u32 comptag_lines; | ||
414 | }; | 420 | }; |
415 | 421 | ||
416 | struct tegra_vgpu_cmd_msg { | 422 | struct tegra_vgpu_cmd_msg { |