diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index b4c7e829..d4582036 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -510,6 +510,171 @@ struct nvgpu_gpu_alloc_vidmem_args { | |||
510 | }; | 510 | }; |
511 | }; | 511 | }; |
512 | 512 | ||
513 | #define NVGPU_GPU_CLK_DOMAIN_MCLK (0x00000010) | ||
514 | #define NVGPU_GPU_CLK_DOMAIN_GPC2CLK (0x00010000) | ||
515 | |||
516 | struct nvgpu_gpu_clk_range { | ||
517 | |||
518 | /* Flags (not currently used) */ | ||
519 | __u32 flags; | ||
520 | |||
521 | /* NVGPU_GPU_CLK_DOMAIN_* */ | ||
522 | __u32 clk_domain; | ||
523 | __u32 min_mhz; | ||
524 | __u32 max_mhz; | ||
525 | }; | ||
526 | |||
527 | struct nvgpu_gpu_clk_range_args { | ||
528 | |||
529 | /* Flags (not currently used) */ | ||
530 | __u32 flags; | ||
531 | |||
532 | /* in/out: max number of entries in clk_range_entries buffer. If zero, | ||
533 | NVGPU_GPU_IOCTL_CLK_GET_RANGE will return 0 and max_entries will be | ||
534 | set to the max number of clock domains. If there are more entries | ||
535 | than max_entries, then ioctl will return -EINVAL. | ||
536 | */ | ||
537 | __u16 max_entries; | ||
538 | |||
539 | /* out: number of nvgpu_gpu_clk_range entries contained in | ||
540 | clk_range_entries */ | ||
541 | __u16 num_entries; | ||
542 | |||
543 | /* in: Pointer to clock range entries in the caller's address space. | ||
544 | size must be >= max_entries * sizeof(struct nvgpu_gpu_clk_range) | ||
545 | */ | ||
546 | __u64 clk_range_entries; | ||
547 | }; | ||
548 | |||
549 | struct nvgpu_gpu_clk_vf_point { | ||
550 | |||
551 | /* Flags (not currently used) */ | ||
552 | __u32 flags; | ||
553 | __u32 freq_mhz; | ||
554 | }; | ||
555 | |||
556 | struct nvgpu_gpu_clk_vf_points_args { | ||
557 | |||
558 | /* in: Flags (not currently used) */ | ||
559 | __u32 flags; | ||
560 | |||
561 | /* in: NVGPU_GPU_CLK_DOMAIN_* */ | ||
562 | __u32 clk_domain; | ||
563 | |||
564 | /* in/out: max number of nvgpu_gpu_clk_vf_point entries in | ||
565 | clk_vf_point_entries. If max_entries is zero, | ||
566 | NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS will return 0 and max_entries will | ||
567 | be set to the max number of VF entries for this clock domain. If | ||
568 | there are more entries than max_entires, then ioctl will return | ||
569 | -EINVAL. | ||
570 | */ | ||
571 | __u16 max_entries; | ||
572 | |||
573 | /* out: Number of nvgpu_gpu_clk_vf_point entries returned in | ||
574 | clk_vf_point_entries. Number of entries might vary depending on | ||
575 | thermal conditions. | ||
576 | */ | ||
577 | __u16 num_entries; | ||
578 | |||
579 | __u32 reserved; | ||
580 | |||
581 | /* in: Pointer to clock VF point entries in the caller's address space. | ||
582 | size must be >= max_entries * sizeof(struct nvgpu_gpu_clk_vf_point). | ||
583 | */ | ||
584 | __u64 clk_vf_point_entries; | ||
585 | }; | ||
586 | |||
587 | struct nvgpu_gpu_clk_info { | ||
588 | |||
589 | /* Flags (not currently used) */ | ||
590 | __u32 flags; | ||
591 | |||
592 | /* NVGPU_GPU_CLK_DOMAIN_* */ | ||
593 | __u32 clk_domain; | ||
594 | |||
595 | /* target clock frequency for the domain in MHz. Should be | ||
596 | specified with a non-zero value in NVGPU_GPU_IOCTL_CLK_SET_INFO. | ||
597 | */ | ||
598 | __u32 target_mhz; | ||
599 | |||
600 | /* actual clock frequency for the domain in MHz. This value | ||
601 | may deviate from the desired target frequency due to PLL constraints. | ||
602 | Not used in NVGPU_GPU_IOCTL_CLK_SET_INFO. | ||
603 | */ | ||
604 | __u32 actual_mhz; | ||
605 | }; | ||
606 | |||
607 | struct nvgpu_gpu_clk_get_info_args { | ||
608 | |||
609 | /* in: Flags (not currently used). */ | ||
610 | __u32 flags; | ||
611 | |||
612 | __u16 pad0; | ||
613 | |||
614 | /* in/out: Number of clock info entries contained in clk_info_entries. | ||
615 | If zero, NVGPU_GPU_IOCTL_CLK_GET_INFO will return 0 and | ||
616 | max_entries will be set to number of clock domains. Also, | ||
617 | last_req_nr will be updated, which allows checking if a given | ||
618 | request has completed. If there are more entries than max_entries, | ||
619 | then ioctl will return -EINVAL. | ||
620 | */ | ||
621 | __u16 num_entries; | ||
622 | |||
623 | /* in: Pointer to nvgpu_gpu_clk_info entries in the caller's address | ||
624 | space. Buffer size must be at least: | ||
625 | num_entries * sizeof(struct nvgpu_gpu_clk_info) | ||
626 | For each entry, the clk_domain to be queried should be set. Note | ||
627 | that clk_info_entries passed to an NVGPU_GPU_IOCTL_CLK_SET_INFO, | ||
628 | can be re-used on completion for a NVGPU_GPU_IOCTL_CLK_GET_INFO. | ||
629 | This allows checking actual_mhz. | ||
630 | */ | ||
631 | __u64 clk_info_entries; | ||
632 | |||
633 | __u32 pad1; | ||
634 | |||
635 | /* out: sequence number of last processed request. sequence numbers | ||
636 | are per-user. | ||
637 | */ | ||
638 | __u32 last_req_nr; | ||
639 | }; | ||
640 | |||
641 | struct nvgpu_gpu_clk_set_info_args { | ||
642 | |||
643 | /* in: Flags (not currently used). */ | ||
644 | __u32 flags; | ||
645 | |||
646 | __u16 pad0; | ||
647 | |||
648 | /* Number of clock info entries contained in clk_info_entries. | ||
649 | Must be > 0. | ||
650 | */ | ||
651 | __u16 num_entries; | ||
652 | |||
653 | /* Pointer to clock info entries in the caller's address space. Buffer | ||
654 | size must be at least | ||
655 | num_entries * sizeof(struct nvgpu_gpu_clk_info) | ||
656 | */ | ||
657 | __u64 clk_info_entries; | ||
658 | |||
659 | /* out: File descriptor for completions and event notifications. | ||
660 | If application does not close this fd after completion, then the | ||
661 | same fd will be returned for subsequent request (recommended). | ||
662 | */ | ||
663 | int fd; | ||
664 | |||
665 | /* out: sequence number for this request. In order to determine that | ||
666 | a request has completed, an application should check this sequence | ||
667 | number against last_req_nr from NVGPU_GPU_IOCTL_CLK_GET_INFO, using | ||
668 | nvgpu_clk_req_complete(req_nr, last_req_nr); | ||
669 | */ | ||
670 | __u32 req_nr; | ||
671 | }; | ||
672 | |||
673 | static inline int nvgpu_clk_req_complete(__u32 req_nr, __u32 last_req_nr) | ||
674 | { | ||
675 | return ((long)(last_req_nr - req_nr) >= 0); | ||
676 | } | ||
677 | |||
513 | struct nvgpu_gpu_get_memory_state_args { | 678 | struct nvgpu_gpu_get_memory_state_args { |
514 | /* | 679 | /* |
515 | * Current free space for this device; may change even when any | 680 | * Current free space for this device; may change even when any |
@@ -596,6 +761,14 @@ struct nvgpu_gpu_get_fbp_l2_masks_args { | |||
596 | #define NVGPU_GPU_IOCTL_ALLOC_VIDMEM \ | 761 | #define NVGPU_GPU_IOCTL_ALLOC_VIDMEM \ |
597 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 27, \ | 762 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 27, \ |
598 | struct nvgpu_gpu_alloc_vidmem_args) | 763 | struct nvgpu_gpu_alloc_vidmem_args) |
764 | #define NVGPU_GPU_IOCTL_CLK_GET_RANGE \ | ||
765 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 28, struct nvgpu_gpu_clk_range_args) | ||
766 | #define NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS \ | ||
767 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 29, struct nvgpu_gpu_clk_vf_points_args) | ||
768 | #define NVGPU_GPU_IOCTL_CLK_GET_INFO \ | ||
769 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 30, struct nvgpu_gpu_clk_get_info_args) | ||
770 | #define NVGPU_GPU_IOCTL_CLK_SET_INFO \ | ||
771 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 31, struct nvgpu_gpu_clk_set_info_args) | ||
599 | #define NVGPU_GPU_IOCTL_GET_MEMORY_STATE \ | 772 | #define NVGPU_GPU_IOCTL_GET_MEMORY_STATE \ |
600 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 33, \ | 773 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 33, \ |
601 | struct nvgpu_gpu_get_memory_state_args) | 774 | struct nvgpu_gpu_get_memory_state_args) |