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-rw-r--r--include/uapi/linux/nvgpu-t19x.h53
-rw-r--r--include/uapi/linux/nvgpu.h32
2 files changed, 21 insertions, 64 deletions
diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h
deleted file mode 100644
index 7fb7fc48..00000000
--- a/include/uapi/linux/nvgpu-t19x.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * NVGPU Public Interface Header
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16/* This file is meant to extend nvgpu.h, not replace it
17 * as such, be sure that nvgpu.h is actually the file performing the
18 * inclusion, to the extent that's possible.
19 */
20#ifndef _UAPI__LINUX_NVGPU_IOCTL_H
21# error "This file is to be included within nvgpu.h only."
22#endif
23
24#ifndef _UAPI__LINUX_NVGPU_T19X_IOCTL_H_
25#define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_
26
27#define NVGPU_GPU_ARCH_GV110 0x00000150
28#define NVGPU_GPU_ARCH_GV100 0x00000140
29#define NVGPU_GPU_IMPL_GV11B 0x0000000B
30#define NVGPU_GPU_IMPL_GV100 0x00000000
31
32/* subcontexts are available */
33#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22)
34
35struct nvgpu_tsg_bind_channel_ex_args {
36 /* in: channel fd */
37 __s32 channel_fd;
38
39 /* in: VEID in Volta */
40 __u32 subcontext_id;
41 __u32 num_active_tpcs;
42 __u8 tpc_pg_enabled;
43 __u8 reserved[11];
44};
45
46#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \
47 _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args)
48
49#define NVGPU_TSG_IOCTL_MAX NVGPU_TSG_IOCTL_BIND_CHANNEL_EX
50
51#define NVGPU_TSG_IOCTL_MAX_ARG sizeof(struct nvgpu_tsg_bind_channel_ex_args)
52
53#endif /* _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ */
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 95da072c..391d482d 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -84,6 +84,8 @@ struct nvgpu_gpu_zbc_query_table_args {
84#define NVGPU_GPU_ARCH_GK100 0x000000E0 84#define NVGPU_GPU_ARCH_GK100 0x000000E0
85#define NVGPU_GPU_ARCH_GM200 0x00000120 85#define NVGPU_GPU_ARCH_GM200 0x00000120
86#define NVGPU_GPU_ARCH_GP100 0x00000130 86#define NVGPU_GPU_ARCH_GP100 0x00000130
87#define NVGPU_GPU_ARCH_GV110 0x00000150
88#define NVGPU_GPU_ARCH_GV100 0x00000140
87 89
88#define NVGPU_GPU_IMPL_GK20A 0x0000000A 90#define NVGPU_GPU_IMPL_GK20A 0x0000000A
89#define NVGPU_GPU_IMPL_GM204 0x00000004 91#define NVGPU_GPU_IMPL_GM204 0x00000004
@@ -93,6 +95,8 @@ struct nvgpu_gpu_zbc_query_table_args {
93#define NVGPU_GPU_IMPL_GP104 0x00000004 95#define NVGPU_GPU_IMPL_GP104 0x00000004
94#define NVGPU_GPU_IMPL_GP106 0x00000006 96#define NVGPU_GPU_IMPL_GP106 0x00000006
95#define NVGPU_GPU_IMPL_GP10B 0x0000000B 97#define NVGPU_GPU_IMPL_GP10B 0x0000000B
98#define NVGPU_GPU_IMPL_GV11B 0x0000000B
99#define NVGPU_GPU_IMPL_GV100 0x00000000
96 100
97#ifdef CONFIG_TEGRA_19x_GPU 101#ifdef CONFIG_TEGRA_19x_GPU
98#include <linux/nvgpu-t19x.h> 102#include <linux/nvgpu-t19x.h>
@@ -142,6 +146,8 @@ struct nvgpu_gpu_zbc_query_table_args {
142#define NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE (1ULL << 20) 146#define NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE (1ULL << 20)
143/* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */ 147/* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */
144#define NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST (1ULL << 21) 148#define NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST (1ULL << 21)
149/* subcontexts are available */
150#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22)
145/* Direct PTE kind control is supported (map_buffer_ex) */ 151/* Direct PTE kind control is supported (map_buffer_ex) */
146#define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23) 152#define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23)
147/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ 153/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
@@ -1008,6 +1014,17 @@ struct nvgpu_gpu_set_event_filter_args {
1008 1014
1009#define NVGPU_TSG_IOCTL_MAGIC 'T' 1015#define NVGPU_TSG_IOCTL_MAGIC 'T'
1010 1016
1017struct nvgpu_tsg_bind_channel_ex_args {
1018 /* in: channel fd */
1019 __s32 channel_fd;
1020
1021 /* in: VEID in Volta */
1022 __u32 subcontext_id;
1023 __u32 num_active_tpcs;
1024 __u8 tpc_pg_enabled;
1025 __u8 reserved[11];
1026};
1027
1011#define NVGPU_TSG_IOCTL_BIND_CHANNEL \ 1028#define NVGPU_TSG_IOCTL_BIND_CHANNEL \
1012 _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int) 1029 _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int)
1013#define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \ 1030#define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \
@@ -1026,19 +1043,12 @@ struct nvgpu_gpu_set_event_filter_args {
1026 _IOW(NVGPU_TSG_IOCTL_MAGIC, 9, struct nvgpu_timeslice_args) 1043 _IOW(NVGPU_TSG_IOCTL_MAGIC, 9, struct nvgpu_timeslice_args)
1027#define NVGPU_IOCTL_TSG_GET_TIMESLICE \ 1044#define NVGPU_IOCTL_TSG_GET_TIMESLICE \
1028 _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) 1045 _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args)
1029 1046#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \
1030 1047 _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args)
1031#ifdef CONFIG_TEGRA_19x_GPU
1032#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
1033 NVGPU_TSG_IOCTL_MAX_ARG
1034#define NVGPU_TSG_IOCTL_LAST \
1035 _IOC_NR(NVGPU_TSG_IOCTL_MAX)
1036#else
1037#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ 1048#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
1038 sizeof(struct nvgpu_event_id_ctrl_args) 1049 sizeof(struct nvgpu_tsg_bind_channel_ex_args)
1039#define NVGPU_TSG_IOCTL_LAST \ 1050#define NVGPU_TSG_IOCTL_LAST \
1040 _IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE) 1051 _IOC_NR(NVGPU_TSG_IOCTL_BIND_CHANNEL_EX)
1041#endif
1042 1052
1043/* 1053/*
1044 * /dev/nvhost-dbg-gpu device 1054 * /dev/nvhost-dbg-gpu device