diff options
Diffstat (limited to 'include/uapi')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 51 |
1 files changed, 47 insertions, 4 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 6bde9d41..42673820 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -100,6 +100,10 @@ struct nvgpu_gpu_zbc_query_table_args { | |||
100 | #define NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS (1 << 1) | 100 | #define NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS (1 << 1) |
101 | /* MAP_BUFFER_EX with sparse allocations */ | 101 | /* MAP_BUFFER_EX with sparse allocations */ |
102 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1 << 2) | 102 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1 << 2) |
103 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
104 | #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1 << 3) | ||
105 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | ||
106 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1 << 4) | ||
103 | 107 | ||
104 | struct nvgpu_gpu_characteristics { | 108 | struct nvgpu_gpu_characteristics { |
105 | __u32 arch; | 109 | __u32 arch; |
@@ -111,14 +115,18 @@ struct nvgpu_gpu_characteristics { | |||
111 | __u64 L2_cache_size; /* bytes */ | 115 | __u64 L2_cache_size; /* bytes */ |
112 | __u64 on_board_video_memory_size; /* bytes */ | 116 | __u64 on_board_video_memory_size; /* bytes */ |
113 | 117 | ||
114 | __u32 num_tpc_per_gpc; | 118 | __u32 num_tpc_per_gpc; /* the architectural maximum */ |
115 | __u32 bus_type; | 119 | __u32 bus_type; |
116 | 120 | ||
117 | __u32 big_page_size; | 121 | __u32 big_page_size; /* the default big page size */ |
118 | __u32 compression_page_size; | 122 | __u32 compression_page_size; |
119 | 123 | ||
120 | __u32 pde_coverage_bit_count; | 124 | __u32 pde_coverage_bit_count; |
121 | __u32 reserved; | 125 | |
126 | /* bit N set ==> big page size 2^N is available in | ||
127 | NVGPU_GPU_IOCTL_ALLOC_AS. The default big page size is | ||
128 | always available regardless of this field. */ | ||
129 | __u32 available_big_page_sizes; | ||
122 | 130 | ||
123 | __u64 flags; | 131 | __u64 flags; |
124 | 132 | ||
@@ -129,6 +137,23 @@ struct nvgpu_gpu_characteristics { | |||
129 | __u32 inline_to_memory_class; | 137 | __u32 inline_to_memory_class; |
130 | __u32 dma_copy_class; | 138 | __u32 dma_copy_class; |
131 | 139 | ||
140 | __u32 gpc_mask; /* enabled GPCs */ | ||
141 | |||
142 | __u32 sm_arch_sm_version; /* sm version */ | ||
143 | __u32 sm_arch_spa_version; /* sm instruction set */ | ||
144 | __u32 sm_arch_warp_count; | ||
145 | |||
146 | /* IOCTL interface levels by service. -1 if not supported */ | ||
147 | __s16 gpu_ioctl_nr_last; | ||
148 | __s16 tsg_ioctl_nr_last; | ||
149 | __s16 dbg_gpu_ioctl_nr_last; | ||
150 | __s16 ioctl_channel_nr_last; | ||
151 | __s16 as_ioctl_nr_last; | ||
152 | |||
153 | __u8 gpu_va_bit_count; | ||
154 | |||
155 | __u8 reserved; | ||
156 | |||
132 | /* Notes: | 157 | /* Notes: |
133 | - This struct can be safely appended with new fields. However, always | 158 | - This struct can be safely appended with new fields. However, always |
134 | keep the structure size multiple of 8 and make sure that the binary | 159 | keep the structure size multiple of 8 and make sure that the binary |
@@ -197,6 +222,22 @@ struct nvgpu_gpu_open_tsg_args { | |||
197 | __u32 reserved; /* must be zero */ | 222 | __u32 reserved; /* must be zero */ |
198 | }; | 223 | }; |
199 | 224 | ||
225 | struct nvgpu_gpu_get_tpc_masks_args { | ||
226 | /* [in] TPC mask buffer size reserved by userspace. Should be | ||
227 | at least sizeof(__u32) * fls(gpc_mask) to receive TPC | ||
228 | mask for each GPC. | ||
229 | [out] full kernel buffer size | ||
230 | */ | ||
231 | __u32 mask_buf_size; | ||
232 | __u32 reserved; | ||
233 | |||
234 | /* [in] pointer to TPC mask buffer. It will receive one | ||
235 | 32-bit TPC mask per GPC or 0 if GPC is not enabled or | ||
236 | not present. This parameter is ignored if | ||
237 | mask_buf_size is 0. */ | ||
238 | __u64 mask_buf_addr; | ||
239 | }; | ||
240 | |||
200 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 241 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
201 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 242 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
202 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 243 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -215,9 +256,11 @@ struct nvgpu_gpu_open_tsg_args { | |||
215 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 8, struct nvgpu_alloc_as_args) | 256 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 8, struct nvgpu_alloc_as_args) |
216 | #define NVGPU_GPU_IOCTL_OPEN_TSG \ | 257 | #define NVGPU_GPU_IOCTL_OPEN_TSG \ |
217 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) | 258 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) |
259 | #define NVGPU_GPU_IOCTL_GET_TPC_MASKS \ | ||
260 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) | ||
218 | 261 | ||
219 | #define NVGPU_GPU_IOCTL_LAST \ | 262 | #define NVGPU_GPU_IOCTL_LAST \ |
220 | _IOC_NR(NVGPU_GPU_IOCTL_OPEN_TSG) | 263 | _IOC_NR(NVGPU_GPU_IOCTL_GET_TPC_MASKS) |
221 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 264 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
222 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) | 265 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) |
223 | 266 | ||