diff options
Diffstat (limited to 'include/uapi')
-rw-r--r-- | include/uapi/linux/nvgpu-t18x.h | 61 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 31 |
2 files changed, 27 insertions, 65 deletions
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h deleted file mode 100644 index 59db77c7..00000000 --- a/include/uapi/linux/nvgpu-t18x.h +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | /* | ||
2 | * NVGPU Public Interface Header | ||
3 | * | ||
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | /* This file is meant to extend nvgpu.h, not replace it | ||
17 | * as such, be sure that nvgpu.h is actually the file performing the | ||
18 | * inclusion, to the extent that's possible. | ||
19 | */ | ||
20 | #ifndef _UAPI__LINUX_NVGPU_IOCTL_H | ||
21 | # error "This file is to be included within nvgpu.h only." | ||
22 | #endif | ||
23 | |||
24 | #ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ | ||
25 | #define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ | ||
26 | |||
27 | /* | ||
28 | * this flag is used in struct nvgpu_alloc_gpfifo_args | ||
29 | * to enable re-playable faults for that channel | ||
30 | */ | ||
31 | #define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) | ||
32 | |||
33 | /* Flags in nvgpu_alloc_obj_ctx_args.flags */ | ||
34 | #define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1) | ||
35 | #define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) | ||
36 | |||
37 | /* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */ | ||
38 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1) | ||
39 | /* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */ | ||
40 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2) | ||
41 | |||
42 | /* SM LRF ECC is enabled */ | ||
43 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) | ||
44 | /* SM SHM ECC is enabled */ | ||
45 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61) | ||
46 | /* TEX ECC is enabled */ | ||
47 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62) | ||
48 | /* L2 ECC is enabled */ | ||
49 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63) | ||
50 | /* All types of ECC are enabled */ | ||
51 | #define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \ | ||
52 | (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \ | ||
53 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \ | ||
54 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \ | ||
55 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC) | ||
56 | |||
57 | /* Channel event_id in nvgpu_channel_events_ctrl_ext_args */ | ||
58 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3 | ||
59 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4 | ||
60 | |||
61 | #endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */ | ||
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index bf711ef8..95da072c 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -94,10 +94,6 @@ struct nvgpu_gpu_zbc_query_table_args { | |||
94 | #define NVGPU_GPU_IMPL_GP106 0x00000006 | 94 | #define NVGPU_GPU_IMPL_GP106 0x00000006 |
95 | #define NVGPU_GPU_IMPL_GP10B 0x0000000B | 95 | #define NVGPU_GPU_IMPL_GP10B 0x0000000B |
96 | 96 | ||
97 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
98 | #include <linux/nvgpu-t18x.h> | ||
99 | #endif | ||
100 | |||
101 | #ifdef CONFIG_TEGRA_19x_GPU | 97 | #ifdef CONFIG_TEGRA_19x_GPU |
102 | #include <linux/nvgpu-t19x.h> | 98 | #include <linux/nvgpu-t19x.h> |
103 | #endif | 99 | #endif |
@@ -150,6 +146,20 @@ struct nvgpu_gpu_zbc_query_table_args { | |||
150 | #define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23) | 146 | #define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23) |
151 | /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ | 147 | /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ |
152 | #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24) | 148 | #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24) |
149 | /* SM LRF ECC is enabled */ | ||
150 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) | ||
151 | /* SM SHM ECC is enabled */ | ||
152 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61) | ||
153 | /* TEX ECC is enabled */ | ||
154 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62) | ||
155 | /* L2 ECC is enabled */ | ||
156 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63) | ||
157 | /* All types of ECC are enabled */ | ||
158 | #define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \ | ||
159 | (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \ | ||
160 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \ | ||
161 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \ | ||
162 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC) | ||
153 | 163 | ||
154 | struct nvgpu_gpu_characteristics { | 164 | struct nvgpu_gpu_characteristics { |
155 | __u32 arch; | 165 | __u32 arch; |
@@ -1388,6 +1398,9 @@ struct nvgpu_set_nvmap_fd_args { | |||
1388 | } __packed; | 1398 | } __packed; |
1389 | 1399 | ||
1390 | #define NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO (1 << 0) | 1400 | #define NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO (1 << 0) |
1401 | /* Flags in nvgpu_alloc_obj_ctx_args.flags */ | ||
1402 | #define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1) | ||
1403 | #define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) | ||
1391 | 1404 | ||
1392 | struct nvgpu_alloc_obj_ctx_args { | 1405 | struct nvgpu_alloc_obj_ctx_args { |
1393 | __u32 class_num; /* kepler3d, 2d, compute, etc */ | 1406 | __u32 class_num; /* kepler3d, 2d, compute, etc */ |
@@ -1398,6 +1411,11 @@ struct nvgpu_alloc_obj_ctx_args { | |||
1398 | struct nvgpu_alloc_gpfifo_args { | 1411 | struct nvgpu_alloc_gpfifo_args { |
1399 | __u32 num_entries; | 1412 | __u32 num_entries; |
1400 | #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ | 1413 | #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ |
1414 | /* | ||
1415 | * this flag is used in struct nvgpu_alloc_gpfifo_args | ||
1416 | * to enable re-playable faults for that channel | ||
1417 | */ | ||
1418 | #define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) | ||
1401 | __u32 flags; | 1419 | __u32 flags; |
1402 | }; | 1420 | }; |
1403 | 1421 | ||
@@ -1592,6 +1610,8 @@ struct nvgpu_event_id_ctrl_args { | |||
1592 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 | 1610 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 |
1593 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 | 1611 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 |
1594 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 | 1612 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 |
1613 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3 | ||
1614 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4 | ||
1595 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN 5 | 1615 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN 5 |
1596 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 6 | 1616 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 6 |
1597 | 1617 | ||
@@ -1600,11 +1620,14 @@ struct nvgpu_event_id_ctrl_args { | |||
1600 | struct nvgpu_preemption_mode_args { | 1620 | struct nvgpu_preemption_mode_args { |
1601 | /* only one should be enabled at a time */ | 1621 | /* only one should be enabled at a time */ |
1602 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI (1 << 0) | 1622 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI (1 << 0) |
1623 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1) | ||
1603 | __u32 graphics_preempt_mode; /* in */ | 1624 | __u32 graphics_preempt_mode; /* in */ |
1604 | 1625 | ||
1605 | /* only one should be enabled at a time */ | 1626 | /* only one should be enabled at a time */ |
1606 | #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI (1 << 0) | 1627 | #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI (1 << 0) |
1607 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA (1 << 1) | 1628 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA (1 << 1) |
1629 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2) | ||
1630 | |||
1608 | __u32 compute_preempt_mode; /* in */ | 1631 | __u32 compute_preempt_mode; /* in */ |
1609 | }; | 1632 | }; |
1610 | 1633 | ||