diff options
Diffstat (limited to 'include/uapi/linux')
-rw-r--r-- | include/uapi/linux/nvgpu-t18x.h | 61 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 2195 |
2 files changed, 2256 insertions, 0 deletions
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h new file mode 100644 index 00000000..59db77c7 --- /dev/null +++ b/include/uapi/linux/nvgpu-t18x.h | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | * NVGPU Public Interface Header | ||
3 | * | ||
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | /* This file is meant to extend nvgpu.h, not replace it | ||
17 | * as such, be sure that nvgpu.h is actually the file performing the | ||
18 | * inclusion, to the extent that's possible. | ||
19 | */ | ||
20 | #ifndef _UAPI__LINUX_NVGPU_IOCTL_H | ||
21 | # error "This file is to be included within nvgpu.h only." | ||
22 | #endif | ||
23 | |||
24 | #ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ | ||
25 | #define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ | ||
26 | |||
27 | /* | ||
28 | * this flag is used in struct nvgpu_alloc_gpfifo_args | ||
29 | * to enable re-playable faults for that channel | ||
30 | */ | ||
31 | #define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) | ||
32 | |||
33 | /* Flags in nvgpu_alloc_obj_ctx_args.flags */ | ||
34 | #define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1) | ||
35 | #define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2) | ||
36 | |||
37 | /* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */ | ||
38 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1) | ||
39 | /* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */ | ||
40 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2) | ||
41 | |||
42 | /* SM LRF ECC is enabled */ | ||
43 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) | ||
44 | /* SM SHM ECC is enabled */ | ||
45 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61) | ||
46 | /* TEX ECC is enabled */ | ||
47 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62) | ||
48 | /* L2 ECC is enabled */ | ||
49 | #define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63) | ||
50 | /* All types of ECC are enabled */ | ||
51 | #define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \ | ||
52 | (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \ | ||
53 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \ | ||
54 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \ | ||
55 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC) | ||
56 | |||
57 | /* Channel event_id in nvgpu_channel_events_ctrl_ext_args */ | ||
58 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3 | ||
59 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4 | ||
60 | |||
61 | #endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */ | ||
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h new file mode 100644 index 00000000..20a6de29 --- /dev/null +++ b/include/uapi/linux/nvgpu.h | |||
@@ -0,0 +1,2195 @@ | |||
1 | /* | ||
2 | * NVGPU Public Interface Header | ||
3 | * | ||
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _UAPI__LINUX_NVGPU_IOCTL_H | ||
17 | #define _UAPI__LINUX_NVGPU_IOCTL_H | ||
18 | |||
19 | #include <linux/ioctl.h> | ||
20 | #include <linux/types.h> | ||
21 | |||
22 | #if !defined(__KERNEL__) | ||
23 | #define __user | ||
24 | #endif | ||
25 | |||
26 | /* | ||
27 | * /dev/nvhost-ctrl-gpu device | ||
28 | * | ||
29 | * Opening a '/dev/nvhost-ctrl-gpu' device node creates a way to send | ||
30 | * ctrl ioctl to gpu driver. | ||
31 | * | ||
32 | * /dev/nvhost-gpu is for channel (context specific) operations. We use | ||
33 | * /dev/nvhost-ctrl-gpu for global (context independent) operations on | ||
34 | * gpu device. | ||
35 | */ | ||
36 | |||
37 | #define NVGPU_GPU_IOCTL_MAGIC 'G' | ||
38 | |||
39 | /* return zcull ctx size */ | ||
40 | struct nvgpu_gpu_zcull_get_ctx_size_args { | ||
41 | __u32 size; | ||
42 | } __packed; | ||
43 | |||
44 | /* return zcull info */ | ||
45 | struct nvgpu_gpu_zcull_get_info_args { | ||
46 | __u32 width_align_pixels; | ||
47 | __u32 height_align_pixels; | ||
48 | __u32 pixel_squares_by_aliquots; | ||
49 | __u32 aliquot_total; | ||
50 | __u32 region_byte_multiplier; | ||
51 | __u32 region_header_size; | ||
52 | __u32 subregion_header_size; | ||
53 | __u32 subregion_width_align_pixels; | ||
54 | __u32 subregion_height_align_pixels; | ||
55 | __u32 subregion_count; | ||
56 | }; | ||
57 | |||
58 | #define NVGPU_ZBC_COLOR_VALUE_SIZE 4 | ||
59 | #define NVGPU_ZBC_TYPE_INVALID 0 | ||
60 | #define NVGPU_ZBC_TYPE_COLOR 1 | ||
61 | #define NVGPU_ZBC_TYPE_DEPTH 2 | ||
62 | |||
63 | struct nvgpu_gpu_zbc_set_table_args { | ||
64 | __u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE]; | ||
65 | __u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE]; | ||
66 | __u32 depth; | ||
67 | __u32 format; | ||
68 | __u32 type; /* color or depth */ | ||
69 | } __packed; | ||
70 | |||
71 | struct nvgpu_gpu_zbc_query_table_args { | ||
72 | __u32 color_ds[NVGPU_ZBC_COLOR_VALUE_SIZE]; | ||
73 | __u32 color_l2[NVGPU_ZBC_COLOR_VALUE_SIZE]; | ||
74 | __u32 depth; | ||
75 | __u32 ref_cnt; | ||
76 | __u32 format; | ||
77 | __u32 type; /* color or depth */ | ||
78 | __u32 index_size; /* [out] size, [in] index */ | ||
79 | } __packed; | ||
80 | |||
81 | |||
82 | /* This contains the minimal set by which the userspace can | ||
83 | determine all the properties of the GPU */ | ||
84 | #define NVGPU_GPU_ARCH_GK100 0x000000E0 | ||
85 | #define NVGPU_GPU_ARCH_GM200 0x00000120 | ||
86 | #define NVGPU_GPU_ARCH_GP100 0x00000130 | ||
87 | |||
88 | #define NVGPU_GPU_IMPL_GK20A 0x0000000A | ||
89 | #define NVGPU_GPU_IMPL_GM204 0x00000004 | ||
90 | #define NVGPU_GPU_IMPL_GM206 0x00000006 | ||
91 | #define NVGPU_GPU_IMPL_GM20B 0x0000000B | ||
92 | #define NVGPU_GPU_IMPL_GM20B_B 0x0000000E | ||
93 | #define NVGPU_GPU_IMPL_GP104 0x00000004 | ||
94 | #define NVGPU_GPU_IMPL_GP106 0x00000006 | ||
95 | #define NVGPU_GPU_IMPL_GP10B 0x0000000B | ||
96 | |||
97 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
98 | #include <linux/nvgpu-t18x.h> | ||
99 | #endif | ||
100 | |||
101 | #ifdef CONFIG_TEGRA_19x_GPU | ||
102 | #include <linux/nvgpu-t19x.h> | ||
103 | #endif | ||
104 | |||
105 | #define NVGPU_GPU_BUS_TYPE_NONE 0 | ||
106 | #define NVGPU_GPU_BUS_TYPE_AXI 32 | ||
107 | |||
108 | #define NVGPU_GPU_FLAGS_HAS_SYNCPOINTS (1ULL << 0) | ||
109 | /* MAP_BUFFER_EX with partial mappings */ | ||
110 | #define NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS (1ULL << 1) | ||
111 | /* MAP_BUFFER_EX with sparse allocations */ | ||
112 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2) | ||
113 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
114 | #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3) | ||
115 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | ||
116 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4) | ||
117 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ | ||
118 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6) | ||
119 | /* User-space managed address spaces support */ | ||
120 | #define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7) | ||
121 | /* Both gpu driver and device support TSG */ | ||
122 | #define NVGPU_GPU_FLAGS_SUPPORT_TSG (1ULL << 8) | ||
123 | /* Clock control support */ | ||
124 | #define NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS (1ULL << 9) | ||
125 | /* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ | ||
126 | #define NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE (1ULL << 10) | ||
127 | /* NVGPU_GPU_IOCTL_GET_CURRENT is available */ | ||
128 | #define NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT (1ULL << 11) | ||
129 | /* NVGPU_GPU_IOCTL_GET_POWER is available */ | ||
130 | #define NVGPU_GPU_FLAGS_SUPPORT_GET_POWER (1ULL << 12) | ||
131 | /* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */ | ||
132 | #define NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE (1ULL << 13) | ||
133 | /* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */ | ||
134 | #define NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT (1ULL << 14) | ||
135 | /* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */ | ||
136 | #define NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS (1ULL << 15) | ||
137 | /* FECS context switch tracing is available */ | ||
138 | #define NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE (1ULL << 16) | ||
139 | /* NVGPU_AS_IOCTL_MAP_BUFFER_COMPBITS is available */ | ||
140 | #define NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITS (1ULL << 17) | ||
141 | /* Fast deterministic submits with no job tracking are supported */ | ||
142 | #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING (1ULL << 18) | ||
143 | /* Deterministic submits are supported even with job tracking */ | ||
144 | #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL (1ULL << 19) | ||
145 | /* IO coherence support is available */ | ||
146 | #define NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE (1ULL << 20) | ||
147 | /* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */ | ||
148 | #define NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST (1ULL << 21) | ||
149 | /* Direct PTE kind control is supported (map_buffer_ex) */ | ||
150 | #define NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL (1ULL << 23) | ||
151 | /* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */ | ||
152 | #define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24) | ||
153 | |||
154 | struct nvgpu_gpu_characteristics { | ||
155 | __u32 arch; | ||
156 | __u32 impl; | ||
157 | __u32 rev; | ||
158 | __u32 num_gpc; | ||
159 | |||
160 | __u64 L2_cache_size; /* bytes */ | ||
161 | __u64 on_board_video_memory_size; /* bytes */ | ||
162 | |||
163 | __u32 num_tpc_per_gpc; /* the architectural maximum */ | ||
164 | __u32 bus_type; | ||
165 | |||
166 | __u32 big_page_size; /* the default big page size */ | ||
167 | __u32 compression_page_size; | ||
168 | |||
169 | __u32 pde_coverage_bit_count; | ||
170 | |||
171 | /* bit N set ==> big page size 2^N is available in | ||
172 | NVGPU_GPU_IOCTL_ALLOC_AS. The default big page size is | ||
173 | always available regardless of this field. */ | ||
174 | __u32 available_big_page_sizes; | ||
175 | |||
176 | __u64 flags; | ||
177 | |||
178 | __u32 twod_class; | ||
179 | __u32 threed_class; | ||
180 | __u32 compute_class; | ||
181 | __u32 gpfifo_class; | ||
182 | __u32 inline_to_memory_class; | ||
183 | __u32 dma_copy_class; | ||
184 | |||
185 | __u32 gpc_mask; /* enabled GPCs */ | ||
186 | |||
187 | __u32 sm_arch_sm_version; /* sm version */ | ||
188 | __u32 sm_arch_spa_version; /* sm instruction set */ | ||
189 | __u32 sm_arch_warp_count; | ||
190 | |||
191 | /* IOCTL interface levels by service. -1 if not supported */ | ||
192 | __s16 gpu_ioctl_nr_last; | ||
193 | __s16 tsg_ioctl_nr_last; | ||
194 | __s16 dbg_gpu_ioctl_nr_last; | ||
195 | __s16 ioctl_channel_nr_last; | ||
196 | __s16 as_ioctl_nr_last; | ||
197 | |||
198 | __u8 gpu_va_bit_count; | ||
199 | __u8 reserved; | ||
200 | |||
201 | __u32 max_fbps_count; | ||
202 | __u32 fbp_en_mask; | ||
203 | __u32 max_ltc_per_fbp; | ||
204 | __u32 max_lts_per_ltc; | ||
205 | __u32 max_tex_per_tpc; | ||
206 | __u32 max_gpc_count; | ||
207 | /* mask of Rop_L2 for each FBP */ | ||
208 | __u32 rop_l2_en_mask_DEPRECATED[2]; | ||
209 | |||
210 | |||
211 | __u8 chipname[8]; | ||
212 | |||
213 | __u64 gr_compbit_store_base_hw; | ||
214 | __u32 gr_gobs_per_comptagline_per_slice; | ||
215 | __u32 num_ltc; | ||
216 | __u32 lts_per_ltc; | ||
217 | __u32 cbc_cache_line_size; | ||
218 | __u32 cbc_comptags_per_line; | ||
219 | |||
220 | /* MAP_BUFFER_BATCH: the upper limit for num_unmaps and | ||
221 | * num_maps */ | ||
222 | __u32 map_buffer_batch_limit; | ||
223 | |||
224 | __u64 max_freq; | ||
225 | |||
226 | /* supported preemption modes */ | ||
227 | __u32 graphics_preemption_mode_flags; /* NVGPU_GRAPHICS_PREEMPTION_MODE_* */ | ||
228 | __u32 compute_preemption_mode_flags; /* NVGPU_COMPUTE_PREEMPTION_MODE_* */ | ||
229 | /* default preemption modes */ | ||
230 | __u32 default_graphics_preempt_mode; /* NVGPU_GRAPHICS_PREEMPTION_MODE_* */ | ||
231 | __u32 default_compute_preempt_mode; /* NVGPU_COMPUTE_PREEMPTION_MODE_* */ | ||
232 | |||
233 | __u64 local_video_memory_size; /* in bytes, non-zero only for dGPUs */ | ||
234 | |||
235 | /* These are meaningful only for PCI devices */ | ||
236 | __u16 pci_vendor_id, pci_device_id; | ||
237 | __u16 pci_subsystem_vendor_id, pci_subsystem_device_id; | ||
238 | __u16 pci_class; | ||
239 | __u8 pci_revision; | ||
240 | __u8 vbios_oem_version; | ||
241 | __u32 vbios_version; | ||
242 | |||
243 | /* NVGPU_DBG_GPU_IOCTL_REG_OPS: the upper limit for the number | ||
244 | * of regops */ | ||
245 | __u32 reg_ops_limit; | ||
246 | __u32 reserved1; | ||
247 | |||
248 | __s16 event_ioctl_nr_last; | ||
249 | __u16 pad; | ||
250 | |||
251 | __u32 max_css_buffer_size; | ||
252 | |||
253 | /* Notes: | ||
254 | - This struct can be safely appended with new fields. However, always | ||
255 | keep the structure size multiple of 8 and make sure that the binary | ||
256 | layout does not change between 32-bit and 64-bit architectures. | ||
257 | - If the last field is reserved/padding, it is not | ||
258 | generally safe to repurpose the field in future revisions. | ||
259 | */ | ||
260 | }; | ||
261 | |||
262 | struct nvgpu_gpu_get_characteristics { | ||
263 | /* [in] size reserved by the user space. Can be 0. | ||
264 | [out] full buffer size by kernel */ | ||
265 | __u64 gpu_characteristics_buf_size; | ||
266 | |||
267 | /* [in] address of nvgpu_gpu_characteristics buffer. Filled with field | ||
268 | values by exactly MIN(buf_size_in, buf_size_out) bytes. Ignored, if | ||
269 | buf_size_in is zero. */ | ||
270 | __u64 gpu_characteristics_buf_addr; | ||
271 | }; | ||
272 | |||
273 | #define NVGPU_GPU_COMPBITS_NONE 0 | ||
274 | #define NVGPU_GPU_COMPBITS_GPU (1 << 0) | ||
275 | #define NVGPU_GPU_COMPBITS_CDEH (1 << 1) | ||
276 | #define NVGPU_GPU_COMPBITS_CDEV (1 << 2) | ||
277 | |||
278 | struct nvgpu_gpu_prepare_compressible_read_args { | ||
279 | __u32 handle; /* in, dmabuf fd */ | ||
280 | union { | ||
281 | __u32 request_compbits; /* in */ | ||
282 | __u32 valid_compbits; /* out */ | ||
283 | }; | ||
284 | __u64 offset; /* in, within handle */ | ||
285 | __u64 compbits_hoffset; /* in, within handle */ | ||
286 | __u64 compbits_voffset; /* in, within handle */ | ||
287 | __u32 width; /* in, in pixels */ | ||
288 | __u32 height; /* in, in pixels */ | ||
289 | __u32 block_height_log2; /* in */ | ||
290 | __u32 submit_flags; /* in (NVGPU_SUBMIT_GPFIFO_FLAGS_) */ | ||
291 | union { | ||
292 | struct { | ||
293 | __u32 syncpt_id; | ||
294 | __u32 syncpt_value; | ||
295 | }; | ||
296 | __s32 fd; | ||
297 | } fence; /* in/out */ | ||
298 | __u32 zbc_color; /* out */ | ||
299 | __u32 reserved; /* must be zero */ | ||
300 | __u64 scatterbuffer_offset; /* in, within handle */ | ||
301 | __u32 reserved2[2]; /* must be zero */ | ||
302 | }; | ||
303 | |||
304 | struct nvgpu_gpu_mark_compressible_write_args { | ||
305 | __u32 handle; /* in, dmabuf fd */ | ||
306 | __u32 valid_compbits; /* in */ | ||
307 | __u64 offset; /* in, within handle */ | ||
308 | __u32 zbc_color; /* in */ | ||
309 | __u32 reserved[3]; /* must be zero */ | ||
310 | }; | ||
311 | |||
312 | struct nvgpu_alloc_as_args { | ||
313 | __u32 big_page_size; | ||
314 | __s32 as_fd; | ||
315 | |||
316 | /* | ||
317 | * The GPU address space will be managed by the userspace. This has | ||
318 | * the following changes in functionality: | ||
319 | * 1. All non-fixed-offset user mappings are rejected (i.e., | ||
320 | * fixed-offset only) | ||
321 | * 2. Address space does not need to be allocated for fixed-offset | ||
322 | * mappings, except to mark sparse address space areas. | ||
323 | * 3. Maps and unmaps are immediate. In particular, mapping ref | ||
324 | * increments at kickoffs and decrements at job completion are | ||
325 | * bypassed. | ||
326 | */ | ||
327 | #define NVGPU_GPU_IOCTL_ALLOC_AS_FLAGS_USERSPACE_MANAGED (1 << 0) | ||
328 | __u32 flags; | ||
329 | |||
330 | __u32 reserved; /* must be zero */ | ||
331 | }; | ||
332 | |||
333 | struct nvgpu_gpu_open_tsg_args { | ||
334 | __u32 tsg_fd; /* out, tsg fd */ | ||
335 | __u32 reserved; /* must be zero */ | ||
336 | }; | ||
337 | |||
338 | struct nvgpu_gpu_get_tpc_masks_args { | ||
339 | /* [in] TPC mask buffer size reserved by userspace. Should be | ||
340 | at least sizeof(__u32) * fls(gpc_mask) to receive TPC | ||
341 | mask for each GPC. | ||
342 | [out] full kernel buffer size | ||
343 | */ | ||
344 | __u32 mask_buf_size; | ||
345 | __u32 reserved; | ||
346 | |||
347 | /* [in] pointer to TPC mask buffer. It will receive one | ||
348 | 32-bit TPC mask per GPC or 0 if GPC is not enabled or | ||
349 | not present. This parameter is ignored if | ||
350 | mask_buf_size is 0. */ | ||
351 | __u64 mask_buf_addr; | ||
352 | }; | ||
353 | |||
354 | struct nvgpu_gpu_open_channel_args { | ||
355 | union { | ||
356 | __s32 channel_fd; /* deprecated: use out.channel_fd instead */ | ||
357 | struct { | ||
358 | /* runlist_id is the runlist for the | ||
359 | * channel. Basically, the runlist specifies the target | ||
360 | * engine(s) for which the channel is | ||
361 | * opened. Runlist_id -1 is synonym for the primary | ||
362 | * graphics runlist. */ | ||
363 | __s32 runlist_id; | ||
364 | } in; | ||
365 | struct { | ||
366 | __s32 channel_fd; | ||
367 | } out; | ||
368 | }; | ||
369 | }; | ||
370 | |||
371 | /* L2 cache writeback, optionally invalidate clean lines and flush fb */ | ||
372 | struct nvgpu_gpu_l2_fb_args { | ||
373 | __u32 l2_flush:1; | ||
374 | __u32 l2_invalidate:1; | ||
375 | __u32 fb_flush:1; | ||
376 | __u32 reserved; | ||
377 | } __packed; | ||
378 | |||
379 | struct nvgpu_gpu_inval_icache_args { | ||
380 | int channel_fd; | ||
381 | __u32 reserved; | ||
382 | } __packed; | ||
383 | |||
384 | struct nvgpu_gpu_mmu_debug_mode_args { | ||
385 | __u32 state; | ||
386 | __u32 reserved; | ||
387 | } __packed; | ||
388 | |||
389 | struct nvgpu_gpu_sm_debug_mode_args { | ||
390 | int channel_fd; | ||
391 | __u32 enable; | ||
392 | __u64 sms; | ||
393 | } __packed; | ||
394 | |||
395 | struct warpstate { | ||
396 | __u64 valid_warps[2]; | ||
397 | __u64 trapped_warps[2]; | ||
398 | __u64 paused_warps[2]; | ||
399 | }; | ||
400 | |||
401 | struct nvgpu_gpu_wait_pause_args { | ||
402 | __u64 pwarpstate; | ||
403 | }; | ||
404 | |||
405 | struct nvgpu_gpu_tpc_exception_en_status_args { | ||
406 | __u64 tpc_exception_en_sm_mask; | ||
407 | }; | ||
408 | |||
409 | struct nvgpu_gpu_num_vsms { | ||
410 | __u32 num_vsms; | ||
411 | __u32 reserved; | ||
412 | }; | ||
413 | |||
414 | struct nvgpu_gpu_vsms_mapping_entry { | ||
415 | __u8 gpc_index; | ||
416 | __u8 tpc_index; | ||
417 | }; | ||
418 | |||
419 | struct nvgpu_gpu_vsms_mapping { | ||
420 | __u64 vsms_map_buf_addr; | ||
421 | }; | ||
422 | |||
423 | struct nvgpu_gpu_get_buffer_info_args { | ||
424 | union { | ||
425 | struct { | ||
426 | __u32 dmabuf_fd; /* dma-buf fd */ | ||
427 | } in; | ||
428 | struct { | ||
429 | __u64 id; /* Unique within live | ||
430 | * buffers */ | ||
431 | __u64 length; /* Allocated length of the | ||
432 | * buffer */ | ||
433 | __u64 reserved0; | ||
434 | __u64 reserved1; | ||
435 | } out; | ||
436 | }; | ||
437 | }; | ||
438 | |||
439 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT 16 | ||
440 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TSC 1 | ||
441 | |||
442 | struct nvgpu_gpu_get_cpu_time_correlation_sample { | ||
443 | /* gpu timestamp value */ | ||
444 | __u64 cpu_timestamp; | ||
445 | /* raw GPU counter (PTIMER) value */ | ||
446 | __u64 gpu_timestamp; | ||
447 | }; | ||
448 | |||
449 | struct nvgpu_gpu_get_cpu_time_correlation_info_args { | ||
450 | /* timestamp pairs */ | ||
451 | struct nvgpu_gpu_get_cpu_time_correlation_sample samples[ | ||
452 | NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT]; | ||
453 | /* number of pairs to read */ | ||
454 | __u32 count; | ||
455 | /* cpu clock source id */ | ||
456 | __u32 source_id; | ||
457 | }; | ||
458 | |||
459 | struct nvgpu_gpu_get_gpu_time_args { | ||
460 | /* raw GPU counter (PTIMER) value */ | ||
461 | __u64 gpu_timestamp; | ||
462 | |||
463 | /* reserved for future extensions */ | ||
464 | __u64 reserved; | ||
465 | }; | ||
466 | |||
467 | struct nvgpu_gpu_get_engine_info_item { | ||
468 | |||
469 | #define NVGPU_GPU_ENGINE_ID_GR 0 | ||
470 | #define NVGPU_GPU_ENGINE_ID_GR_COPY 1 | ||
471 | #define NVGPU_GPU_ENGINE_ID_ASYNC_COPY 2 | ||
472 | __u32 engine_id; | ||
473 | |||
474 | __u32 engine_instance; | ||
475 | |||
476 | /* runlist id for opening channels to the engine, or -1 if | ||
477 | * channels are not supported */ | ||
478 | __s32 runlist_id; | ||
479 | |||
480 | __u32 reserved; | ||
481 | }; | ||
482 | |||
483 | struct nvgpu_gpu_get_engine_info_args { | ||
484 | /* [in] Buffer size reserved by userspace. | ||
485 | * | ||
486 | * [out] Full kernel buffer size. Multiple of sizeof(struct | ||
487 | * nvgpu_gpu_get_engine_info_item) | ||
488 | */ | ||
489 | __u32 engine_info_buf_size; | ||
490 | __u32 reserved; | ||
491 | __u64 engine_info_buf_addr; | ||
492 | }; | ||
493 | |||
494 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_CONTIGUOUS (1U << 0) | ||
495 | |||
496 | /* CPU access and coherency flags (3 bits). Use CPU access with care, | ||
497 | * BAR resources are scarce. */ | ||
498 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_CPU_NOT_MAPPABLE (0U << 1) | ||
499 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_CPU_WRITE_COMBINE (1U << 1) | ||
500 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_CPU_CACHED (2U << 1) | ||
501 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_CPU_MASK (7U << 1) | ||
502 | |||
503 | #define NVGPU_GPU_ALLOC_VIDMEM_FLAG_VPR (1U << 4) | ||
504 | |||
505 | /* Allocation of device-specific local video memory. Returns dmabuf fd | ||
506 | * on success. */ | ||
507 | struct nvgpu_gpu_alloc_vidmem_args { | ||
508 | union { | ||
509 | struct { | ||
510 | /* Size for allocation. Must be a multiple of | ||
511 | * small page size. */ | ||
512 | __u64 size; | ||
513 | |||
514 | /* NVGPU_GPU_ALLOC_VIDMEM_FLAG_* */ | ||
515 | __u32 flags; | ||
516 | |||
517 | /* Informational mem tag for resource usage | ||
518 | * tracking. */ | ||
519 | __u16 memtag; | ||
520 | |||
521 | __u16 reserved0; | ||
522 | |||
523 | /* GPU-visible physical memory alignment in | ||
524 | * bytes. | ||
525 | * | ||
526 | * Alignment must be a power of two. Minimum | ||
527 | * alignment is the small page size, which 0 | ||
528 | * also denotes. | ||
529 | * | ||
530 | * For contiguous and non-contiguous | ||
531 | * allocations, the start address of the | ||
532 | * physical memory allocation will be aligned | ||
533 | * by this value. | ||
534 | * | ||
535 | * For non-contiguous allocations, memory is | ||
536 | * internally allocated in round_up(size / | ||
537 | * alignment) contiguous blocks. The start | ||
538 | * address of each block is aligned by the | ||
539 | * alignment value. If the size is not a | ||
540 | * multiple of alignment (which is ok), the | ||
541 | * last allocation block size is (size % | ||
542 | * alignment). | ||
543 | * | ||
544 | * By specifying the big page size here and | ||
545 | * allocation size that is a multiple of big | ||
546 | * pages, it will be guaranteed that the | ||
547 | * allocated buffer is big page size mappable. | ||
548 | */ | ||
549 | __u32 alignment; | ||
550 | |||
551 | __u32 reserved1[3]; | ||
552 | } in; | ||
553 | |||
554 | struct { | ||
555 | __s32 dmabuf_fd; | ||
556 | } out; | ||
557 | }; | ||
558 | }; | ||
559 | |||
560 | /* Memory clock */ | ||
561 | #define NVGPU_GPU_CLK_DOMAIN_MCLK (0) | ||
562 | /* Main graphics core clock */ | ||
563 | #define NVGPU_GPU_CLK_DOMAIN_GPCCLK (1) | ||
564 | |||
565 | struct nvgpu_gpu_clk_range { | ||
566 | |||
567 | /* Flags (not currently used) */ | ||
568 | __u32 flags; | ||
569 | |||
570 | /* NVGPU_GPU_CLK_DOMAIN_* */ | ||
571 | __u32 clk_domain; | ||
572 | __u64 min_hz; | ||
573 | __u64 max_hz; | ||
574 | }; | ||
575 | |||
576 | /* Request on specific clock domains */ | ||
577 | #define NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS (1UL << 0) | ||
578 | |||
579 | struct nvgpu_gpu_clk_range_args { | ||
580 | |||
581 | /* Flags. If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS the request will | ||
582 | apply only to domains specified in clock entries. In this case | ||
583 | caller must set clock domain in each entry. Otherwise, the | ||
584 | ioctl will return all clock domains. | ||
585 | */ | ||
586 | __u32 flags; | ||
587 | |||
588 | __u16 pad0; | ||
589 | |||
590 | /* in/out: Number of entries in clk_range_entries buffer. If zero, | ||
591 | NVGPU_GPU_IOCTL_CLK_GET_RANGE will return 0 and | ||
592 | num_entries will be set to number of clock domains. | ||
593 | */ | ||
594 | __u16 num_entries; | ||
595 | |||
596 | /* in: Pointer to clock range entries in the caller's address space. | ||
597 | size must be >= max_entries * sizeof(struct nvgpu_gpu_clk_range) | ||
598 | */ | ||
599 | __u64 clk_range_entries; | ||
600 | }; | ||
601 | |||
602 | struct nvgpu_gpu_clk_vf_point { | ||
603 | __u64 freq_hz; | ||
604 | }; | ||
605 | |||
606 | struct nvgpu_gpu_clk_vf_points_args { | ||
607 | |||
608 | /* in: Flags (not currently used) */ | ||
609 | __u32 flags; | ||
610 | |||
611 | /* in: NVGPU_GPU_CLK_DOMAIN_* */ | ||
612 | __u32 clk_domain; | ||
613 | |||
614 | /* in/out: max number of nvgpu_gpu_clk_vf_point entries in | ||
615 | clk_vf_point_entries. If max_entries is zero, | ||
616 | NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS will return 0 and max_entries will | ||
617 | be set to the max number of VF entries for this clock domain. If | ||
618 | there are more entries than max_entries, then ioctl will return | ||
619 | -EINVAL. | ||
620 | */ | ||
621 | __u16 max_entries; | ||
622 | |||
623 | /* out: Number of nvgpu_gpu_clk_vf_point entries returned in | ||
624 | clk_vf_point_entries. Number of entries might vary depending on | ||
625 | thermal conditions. | ||
626 | */ | ||
627 | __u16 num_entries; | ||
628 | |||
629 | __u32 reserved; | ||
630 | |||
631 | /* in: Pointer to clock VF point entries in the caller's address space. | ||
632 | size must be >= max_entries * sizeof(struct nvgpu_gpu_clk_vf_point). | ||
633 | */ | ||
634 | __u64 clk_vf_point_entries; | ||
635 | }; | ||
636 | |||
637 | /* Target clock requested by application*/ | ||
638 | #define NVGPU_GPU_CLK_TYPE_TARGET 1 | ||
639 | /* Actual clock frequency for the domain. | ||
640 | May deviate from desired target frequency due to PLL constraints. */ | ||
641 | #define NVGPU_GPU_CLK_TYPE_ACTUAL 2 | ||
642 | /* Effective clock, measured from hardware */ | ||
643 | #define NVGPU_GPU_CLK_TYPE_EFFECTIVE 3 | ||
644 | |||
645 | struct nvgpu_gpu_clk_info { | ||
646 | |||
647 | /* Flags (not currently used) */ | ||
648 | __u16 flags; | ||
649 | |||
650 | /* in: When NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS set, indicates | ||
651 | the type of clock info to be returned for this entry. It is | ||
652 | allowed to have several entries with different clock types in | ||
653 | the same request (for instance query both target and actual | ||
654 | clocks for a given clock domain). This field is ignored for a | ||
655 | SET operation. */ | ||
656 | __u16 clk_type; | ||
657 | |||
658 | /* NVGPU_GPU_CLK_DOMAIN_xxx */ | ||
659 | __u32 clk_domain; | ||
660 | |||
661 | __u64 freq_hz; | ||
662 | }; | ||
663 | |||
664 | struct nvgpu_gpu_clk_get_info_args { | ||
665 | |||
666 | /* Flags. If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS the request will | ||
667 | apply only to domains specified in clock entries. In this case | ||
668 | caller must set clock domain in each entry. Otherwise, the | ||
669 | ioctl will return all clock domains. | ||
670 | */ | ||
671 | __u32 flags; | ||
672 | |||
673 | /* in: indicates which type of clock info to be returned (see | ||
674 | NVGPU_GPU_CLK_TYPE_xxx). If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS | ||
675 | is defined, clk_type is specified in each clock info entry instead. | ||
676 | */ | ||
677 | __u16 clk_type; | ||
678 | |||
679 | /* in/out: Number of clock info entries contained in clk_info_entries. | ||
680 | If zero, NVGPU_GPU_IOCTL_CLK_GET_INFO will return 0 and | ||
681 | num_entries will be set to number of clock domains. Also, | ||
682 | last_req_nr will be updated, which allows checking if a given | ||
683 | request has completed. If there are more entries than max_entries, | ||
684 | then ioctl will return -EINVAL. | ||
685 | */ | ||
686 | __u16 num_entries; | ||
687 | |||
688 | /* in: Pointer to nvgpu_gpu_clk_info entries in the caller's address | ||
689 | space. Buffer size must be at least: | ||
690 | num_entries * sizeof(struct nvgpu_gpu_clk_info) | ||
691 | If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS is set, caller should set | ||
692 | clk_domain to be queried in each entry. With this flag, | ||
693 | clk_info_entries passed to an NVGPU_GPU_IOCTL_CLK_SET_INFO, | ||
694 | can be re-used on completion for a NVGPU_GPU_IOCTL_CLK_GET_INFO. | ||
695 | This allows checking actual_mhz. | ||
696 | */ | ||
697 | __u64 clk_info_entries; | ||
698 | |||
699 | }; | ||
700 | |||
701 | struct nvgpu_gpu_clk_set_info_args { | ||
702 | |||
703 | /* in: Flags (not currently used). */ | ||
704 | __u32 flags; | ||
705 | |||
706 | __u16 pad0; | ||
707 | |||
708 | /* Number of clock info entries contained in clk_info_entries. | ||
709 | Must be > 0. | ||
710 | */ | ||
711 | __u16 num_entries; | ||
712 | |||
713 | /* Pointer to clock info entries in the caller's address space. Buffer | ||
714 | size must be at least | ||
715 | num_entries * sizeof(struct nvgpu_gpu_clk_info) | ||
716 | */ | ||
717 | __u64 clk_info_entries; | ||
718 | |||
719 | /* out: File descriptor for request completion. Application can poll | ||
720 | this file descriptor to determine when the request has completed. | ||
721 | The fd must be closed afterwards. | ||
722 | */ | ||
723 | __s32 completion_fd; | ||
724 | }; | ||
725 | |||
726 | struct nvgpu_gpu_get_event_fd_args { | ||
727 | |||
728 | /* in: Flags (not currently used). */ | ||
729 | __u32 flags; | ||
730 | |||
731 | /* out: File descriptor for events, e.g. clock update. | ||
732 | * On successful polling of this event_fd, application is | ||
733 | * expected to read status (nvgpu_gpu_event_info), | ||
734 | * which provides detailed event information | ||
735 | * For a poll operation, alarms will be reported with POLLPRI, | ||
736 | * and GPU shutdown will be reported with POLLHUP. | ||
737 | */ | ||
738 | __s32 event_fd; | ||
739 | }; | ||
740 | |||
741 | struct nvgpu_gpu_get_memory_state_args { | ||
742 | /* | ||
743 | * Current free space for this device; may change even when any | ||
744 | * kernel-managed metadata (e.g., page tables or channels) is allocated | ||
745 | * or freed. For an idle gpu, an allocation of this size would succeed. | ||
746 | */ | ||
747 | __u64 total_free_bytes; | ||
748 | |||
749 | /* For future use; must be set to 0. */ | ||
750 | __u64 reserved[4]; | ||
751 | }; | ||
752 | |||
753 | struct nvgpu_gpu_get_fbp_l2_masks_args { | ||
754 | /* [in] L2 mask buffer size reserved by userspace. Should be | ||
755 | at least sizeof(__u32) * fls(fbp_en_mask) to receive LTC | ||
756 | mask for each FBP. | ||
757 | [out] full kernel buffer size | ||
758 | */ | ||
759 | __u32 mask_buf_size; | ||
760 | __u32 reserved; | ||
761 | |||
762 | /* [in] pointer to L2 mask buffer. It will receive one | ||
763 | 32-bit L2 mask per FBP or 0 if FBP is not enabled or | ||
764 | not present. This parameter is ignored if | ||
765 | mask_buf_size is 0. */ | ||
766 | __u64 mask_buf_addr; | ||
767 | }; | ||
768 | |||
769 | #define NVGPU_GPU_VOLTAGE_CORE 1 | ||
770 | #define NVGPU_GPU_VOLTAGE_SRAM 2 | ||
771 | #define NVGPU_GPU_VOLTAGE_BUS 3 /* input to regulator */ | ||
772 | |||
773 | struct nvgpu_gpu_get_voltage_args { | ||
774 | __u64 reserved; | ||
775 | __u32 which; /* in: NVGPU_GPU_VOLTAGE_* */ | ||
776 | __u32 voltage; /* uV */ | ||
777 | }; | ||
778 | |||
779 | struct nvgpu_gpu_get_current_args { | ||
780 | __u32 reserved[3]; | ||
781 | __u32 currnt; /* mA */ | ||
782 | }; | ||
783 | |||
784 | struct nvgpu_gpu_get_power_args { | ||
785 | __u32 reserved[3]; | ||
786 | __u32 power; /* mW */ | ||
787 | }; | ||
788 | |||
789 | struct nvgpu_gpu_get_temperature_args { | ||
790 | __u32 reserved[3]; | ||
791 | /* Temperature in signed fixed point format SFXP24.8 | ||
792 | * Celsius = temp_f24_8 / 256. | ||
793 | */ | ||
794 | __s32 temp_f24_8; | ||
795 | }; | ||
796 | |||
797 | struct nvgpu_gpu_set_therm_alert_limit_args { | ||
798 | __u32 reserved[3]; | ||
799 | /* Temperature in signed fixed point format SFXP24.8 | ||
800 | * Celsius = temp_f24_8 / 256. | ||
801 | */ | ||
802 | __s32 temp_f24_8; | ||
803 | }; | ||
804 | |||
805 | /* | ||
806 | * Adjust options of deterministic channels in channel batches. | ||
807 | * | ||
808 | * This supports only one option currently: relax railgate blocking by | ||
809 | * "disabling" the channel. | ||
810 | * | ||
811 | * Open deterministic channels do not allow the GPU to railgate by default. It | ||
812 | * may be preferable to hold preopened channel contexts open and idle and still | ||
813 | * railgate the GPU, taking the channels back into use dynamically in userspace | ||
814 | * as an optimization. This ioctl allows to drop or reacquire the requirement | ||
815 | * to hold GPU power on for individual channels. If allow_railgate is set on a | ||
816 | * channel, no work can be submitted to it. | ||
817 | * | ||
818 | * num_channels is updated to signify how many channels were updated | ||
819 | * successfully. It can be used to test which was the first update to fail. | ||
820 | */ | ||
821 | struct nvgpu_gpu_set_deterministic_opts_args { | ||
822 | __u32 num_channels; /* in/out */ | ||
823 | /* | ||
824 | * Set or unset the railgating reference held by deterministic channels. If | ||
825 | * the channel status is already the same as the flag, this is a no-op. Both | ||
826 | * of these flags cannot be set at the same time. If none are set, the state | ||
827 | * is left as is. | ||
828 | */ | ||
829 | #define NVGPU_GPU_SET_DETERMINISTIC_OPTS_FLAGS_ALLOW_RAILGATING (1 << 0) | ||
830 | #define NVGPU_GPU_SET_DETERMINISTIC_OPTS_FLAGS_DISALLOW_RAILGATING (1 << 1) | ||
831 | __u32 flags; /* in */ | ||
832 | /* | ||
833 | * This is a pointer to an array of size num_channels. | ||
834 | * | ||
835 | * The channels have to be valid fds and be previously set as | ||
836 | * deterministic. | ||
837 | */ | ||
838 | __u64 channels; /* in */ | ||
839 | }; | ||
840 | |||
841 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | ||
842 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | ||
843 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | ||
844 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 2, struct nvgpu_gpu_zcull_get_info_args) | ||
845 | #define NVGPU_GPU_IOCTL_ZBC_SET_TABLE \ | ||
846 | _IOW(NVGPU_GPU_IOCTL_MAGIC, 3, struct nvgpu_gpu_zbc_set_table_args) | ||
847 | #define NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE \ | ||
848 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 4, struct nvgpu_gpu_zbc_query_table_args) | ||
849 | #define NVGPU_GPU_IOCTL_GET_CHARACTERISTICS \ | ||
850 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 5, struct nvgpu_gpu_get_characteristics) | ||
851 | #define NVGPU_GPU_IOCTL_PREPARE_COMPRESSIBLE_READ \ | ||
852 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 6, struct nvgpu_gpu_prepare_compressible_read_args) | ||
853 | #define NVGPU_GPU_IOCTL_MARK_COMPRESSIBLE_WRITE \ | ||
854 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 7, struct nvgpu_gpu_mark_compressible_write_args) | ||
855 | #define NVGPU_GPU_IOCTL_ALLOC_AS \ | ||
856 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 8, struct nvgpu_alloc_as_args) | ||
857 | #define NVGPU_GPU_IOCTL_OPEN_TSG \ | ||
858 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) | ||
859 | #define NVGPU_GPU_IOCTL_GET_TPC_MASKS \ | ||
860 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) | ||
861 | #define NVGPU_GPU_IOCTL_OPEN_CHANNEL \ | ||
862 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) | ||
863 | #define NVGPU_GPU_IOCTL_FLUSH_L2 \ | ||
864 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args) | ||
865 | #define NVGPU_GPU_IOCTL_INVAL_ICACHE \ | ||
866 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 13, struct nvgpu_gpu_inval_icache_args) | ||
867 | #define NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE \ | ||
868 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 14, struct nvgpu_gpu_mmu_debug_mode_args) | ||
869 | #define NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE \ | ||
870 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 15, struct nvgpu_gpu_sm_debug_mode_args) | ||
871 | #define NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE \ | ||
872 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 16, struct nvgpu_gpu_wait_pause_args) | ||
873 | #define NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS \ | ||
874 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 17, struct nvgpu_gpu_tpc_exception_en_status_args) | ||
875 | #define NVGPU_GPU_IOCTL_NUM_VSMS \ | ||
876 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 18, struct nvgpu_gpu_num_vsms) | ||
877 | #define NVGPU_GPU_IOCTL_VSMS_MAPPING \ | ||
878 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 19, struct nvgpu_gpu_vsms_mapping) | ||
879 | #define NVGPU_GPU_IOCTL_GET_BUFFER_INFO \ | ||
880 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 20, struct nvgpu_gpu_get_buffer_info_args) | ||
881 | #define NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE \ | ||
882 | _IO(NVGPU_GPU_IOCTL_MAGIC, 21) | ||
883 | #define NVGPU_GPU_IOCTL_TRIGGER_SUSPEND \ | ||
884 | _IO(NVGPU_GPU_IOCTL_MAGIC, 22) | ||
885 | #define NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS \ | ||
886 | _IO(NVGPU_GPU_IOCTL_MAGIC, 23) | ||
887 | #define NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO \ | ||
888 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 24, \ | ||
889 | struct nvgpu_gpu_get_cpu_time_correlation_info_args) | ||
890 | #define NVGPU_GPU_IOCTL_GET_GPU_TIME \ | ||
891 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 25, \ | ||
892 | struct nvgpu_gpu_get_gpu_time_args) | ||
893 | #define NVGPU_GPU_IOCTL_GET_ENGINE_INFO \ | ||
894 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 26, \ | ||
895 | struct nvgpu_gpu_get_engine_info_args) | ||
896 | #define NVGPU_GPU_IOCTL_ALLOC_VIDMEM \ | ||
897 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 27, \ | ||
898 | struct nvgpu_gpu_alloc_vidmem_args) | ||
899 | #define NVGPU_GPU_IOCTL_CLK_GET_RANGE \ | ||
900 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 28, struct nvgpu_gpu_clk_range_args) | ||
901 | #define NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS \ | ||
902 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 29, struct nvgpu_gpu_clk_vf_points_args) | ||
903 | #define NVGPU_GPU_IOCTL_CLK_GET_INFO \ | ||
904 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 30, struct nvgpu_gpu_clk_get_info_args) | ||
905 | #define NVGPU_GPU_IOCTL_CLK_SET_INFO \ | ||
906 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 31, struct nvgpu_gpu_clk_set_info_args) | ||
907 | #define NVGPU_GPU_IOCTL_GET_EVENT_FD \ | ||
908 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 32, struct nvgpu_gpu_get_event_fd_args) | ||
909 | #define NVGPU_GPU_IOCTL_GET_MEMORY_STATE \ | ||
910 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 33, \ | ||
911 | struct nvgpu_gpu_get_memory_state_args) | ||
912 | #define NVGPU_GPU_IOCTL_GET_VOLTAGE \ | ||
913 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 34, struct nvgpu_gpu_get_voltage_args) | ||
914 | #define NVGPU_GPU_IOCTL_GET_CURRENT \ | ||
915 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 35, struct nvgpu_gpu_get_current_args) | ||
916 | #define NVGPU_GPU_IOCTL_GET_POWER \ | ||
917 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 36, struct nvgpu_gpu_get_power_args) | ||
918 | #define NVGPU_GPU_IOCTL_GET_TEMPERATURE \ | ||
919 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 37, struct nvgpu_gpu_get_temperature_args) | ||
920 | #define NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS \ | ||
921 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 38, struct nvgpu_gpu_get_fbp_l2_masks_args) | ||
922 | #define NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT \ | ||
923 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 39, \ | ||
924 | struct nvgpu_gpu_set_therm_alert_limit_args) | ||
925 | #define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \ | ||
926 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \ | ||
927 | struct nvgpu_gpu_set_deterministic_opts_args) | ||
928 | #define NVGPU_GPU_IOCTL_LAST \ | ||
929 | _IOC_NR(NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS) | ||
930 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | ||
931 | sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args) | ||
932 | |||
933 | /* | ||
934 | * Event session | ||
935 | * | ||
936 | * NVGPU_GPU_IOCTL_GET_EVENT_FD opens an event session. | ||
937 | * Below ioctls can be used on these sessions fds. | ||
938 | */ | ||
939 | #define NVGPU_EVENT_IOCTL_MAGIC 'E' | ||
940 | |||
941 | /* Normal events (POLLIN) */ | ||
942 | /* Event associated to a VF update */ | ||
943 | #define NVGPU_GPU_EVENT_VF_UPDATE 0 | ||
944 | |||
945 | /* Recoverable alarms (POLLPRI) */ | ||
946 | /* Alarm when target frequency on any session is not possible */ | ||
947 | #define NVGPU_GPU_EVENT_ALARM_TARGET_VF_NOT_POSSIBLE 1 | ||
948 | /* Alarm when target frequency on current session is not possible */ | ||
949 | #define NVGPU_GPU_EVENT_ALARM_LOCAL_TARGET_VF_NOT_POSSIBLE 2 | ||
950 | /* Alarm when Clock Arbiter failed */ | ||
951 | #define NVGPU_GPU_EVENT_ALARM_CLOCK_ARBITER_FAILED 3 | ||
952 | /* Alarm when VF table update failed */ | ||
953 | #define NVGPU_GPU_EVENT_ALARM_VF_TABLE_UPDATE_FAILED 4 | ||
954 | /* Alarm on thermal condition */ | ||
955 | #define NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD 5 | ||
956 | /* Alarm on power condition */ | ||
957 | #define NVGPU_GPU_EVENT_ALARM_POWER_ABOVE_THRESHOLD 6 | ||
958 | |||
959 | /* Non recoverable alarm (POLLHUP) */ | ||
960 | /* Alarm on GPU shutdown/fall from bus */ | ||
961 | #define NVGPU_GPU_EVENT_ALARM_GPU_LOST 7 | ||
962 | |||
963 | #define NVGPU_GPU_EVENT_LAST NVGPU_GPU_EVENT_ALARM_GPU_LOST | ||
964 | |||
965 | struct nvgpu_gpu_event_info { | ||
966 | __u32 event_id; /* NVGPU_GPU_EVENT_* */ | ||
967 | __u32 reserved; | ||
968 | __u64 timestamp; /* CPU timestamp (in nanoseconds) */ | ||
969 | }; | ||
970 | |||
971 | struct nvgpu_gpu_set_event_filter_args { | ||
972 | |||
973 | /* in: Flags (not currently used). */ | ||
974 | __u32 flags; | ||
975 | |||
976 | /* in: Size of event filter in 32-bit words */ | ||
977 | __u32 size; | ||
978 | |||
979 | /* in: Address of buffer containing bit mask of events. | ||
980 | * Bit #n is set if event #n should be monitored. | ||
981 | */ | ||
982 | __u64 buffer; | ||
983 | }; | ||
984 | |||
985 | #define NVGPU_EVENT_IOCTL_SET_FILTER \ | ||
986 | _IOW(NVGPU_EVENT_IOCTL_MAGIC, 1, struct nvgpu_gpu_set_event_filter_args) | ||
987 | #define NVGPU_EVENT_IOCTL_LAST \ | ||
988 | _IOC_NR(NVGPU_EVENT_IOCTL_SET_FILTER) | ||
989 | #define NVGPU_EVENT_IOCTL_MAX_ARG_SIZE \ | ||
990 | sizeof(struct nvgpu_gpu_set_event_filter_args) | ||
991 | |||
992 | /* | ||
993 | * /dev/nvhost-tsg-gpu device | ||
994 | * | ||
995 | * Opening a '/dev/nvhost-tsg-gpu' device node creates a way to | ||
996 | * bind/unbind a channel to/from TSG group | ||
997 | */ | ||
998 | |||
999 | #define NVGPU_TSG_IOCTL_MAGIC 'T' | ||
1000 | |||
1001 | #define NVGPU_TSG_IOCTL_BIND_CHANNEL \ | ||
1002 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int) | ||
1003 | #define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \ | ||
1004 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 2, int) | ||
1005 | #define NVGPU_IOCTL_TSG_ENABLE \ | ||
1006 | _IO(NVGPU_TSG_IOCTL_MAGIC, 3) | ||
1007 | #define NVGPU_IOCTL_TSG_DISABLE \ | ||
1008 | _IO(NVGPU_TSG_IOCTL_MAGIC, 4) | ||
1009 | #define NVGPU_IOCTL_TSG_PREEMPT \ | ||
1010 | _IO(NVGPU_TSG_IOCTL_MAGIC, 5) | ||
1011 | #define NVGPU_IOCTL_TSG_EVENT_ID_CTRL \ | ||
1012 | _IOWR(NVGPU_TSG_IOCTL_MAGIC, 7, struct nvgpu_event_id_ctrl_args) | ||
1013 | #define NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \ | ||
1014 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 8, struct nvgpu_runlist_interleave_args) | ||
1015 | #define NVGPU_IOCTL_TSG_SET_TIMESLICE \ | ||
1016 | _IOW(NVGPU_TSG_IOCTL_MAGIC, 9, struct nvgpu_timeslice_args) | ||
1017 | #define NVGPU_IOCTL_TSG_GET_TIMESLICE \ | ||
1018 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) | ||
1019 | |||
1020 | |||
1021 | #ifdef CONFIG_TEGRA_19x_GPU | ||
1022 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ | ||
1023 | NVGPU_TSG_IOCTL_MAX_ARG | ||
1024 | #define NVGPU_TSG_IOCTL_LAST \ | ||
1025 | _IOC_NR(NVGPU_TSG_IOCTL_MAX) | ||
1026 | #else | ||
1027 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ | ||
1028 | sizeof(struct nvgpu_event_id_ctrl_args) | ||
1029 | #define NVGPU_TSG_IOCTL_LAST \ | ||
1030 | _IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE) | ||
1031 | #endif | ||
1032 | |||
1033 | /* | ||
1034 | * /dev/nvhost-dbg-gpu device | ||
1035 | * | ||
1036 | * Opening a '/dev/nvhost-dbg-gpu' device node creates a new debugger | ||
1037 | * session. nvgpu channels (for the same module) can then be bound to such a | ||
1038 | * session. | ||
1039 | * | ||
1040 | * One nvgpu channel can also be bound to multiple debug sessions | ||
1041 | * | ||
1042 | * As long as there is an open device file to the session, or any bound | ||
1043 | * nvgpu channels it will be valid. Once all references to the session | ||
1044 | * are removed the session is deleted. | ||
1045 | * | ||
1046 | */ | ||
1047 | |||
1048 | #define NVGPU_DBG_GPU_IOCTL_MAGIC 'D' | ||
1049 | |||
1050 | /* | ||
1051 | * Binding/attaching a debugger session to an nvgpu channel | ||
1052 | * | ||
1053 | * The 'channel_fd' given here is the fd used to allocate the | ||
1054 | * gpu channel context. | ||
1055 | * | ||
1056 | */ | ||
1057 | struct nvgpu_dbg_gpu_bind_channel_args { | ||
1058 | __u32 channel_fd; /* in */ | ||
1059 | __u32 _pad0[1]; | ||
1060 | }; | ||
1061 | |||
1062 | #define NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL \ | ||
1063 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 1, struct nvgpu_dbg_gpu_bind_channel_args) | ||
1064 | |||
1065 | /* | ||
1066 | * Register operations | ||
1067 | * All operations are targeted towards first channel | ||
1068 | * attached to debug session | ||
1069 | */ | ||
1070 | /* valid op values */ | ||
1071 | #define NVGPU_DBG_GPU_REG_OP_READ_32 (0x00000000) | ||
1072 | #define NVGPU_DBG_GPU_REG_OP_WRITE_32 (0x00000001) | ||
1073 | #define NVGPU_DBG_GPU_REG_OP_READ_64 (0x00000002) | ||
1074 | #define NVGPU_DBG_GPU_REG_OP_WRITE_64 (0x00000003) | ||
1075 | /* note: 8b ops are unsupported */ | ||
1076 | #define NVGPU_DBG_GPU_REG_OP_READ_08 (0x00000004) | ||
1077 | #define NVGPU_DBG_GPU_REG_OP_WRITE_08 (0x00000005) | ||
1078 | |||
1079 | /* valid type values */ | ||
1080 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GLOBAL (0x00000000) | ||
1081 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX (0x00000001) | ||
1082 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002) | ||
1083 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004) | ||
1084 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008) | ||
1085 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010) | ||
1086 | /*#define NVGPU_DBG_GPU_REG_OP_TYPE_FB (0x00000020)*/ | ||
1087 | #define NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040) | ||
1088 | |||
1089 | /* valid status values */ | ||
1090 | #define NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS (0x00000000) | ||
1091 | #define NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_OP (0x00000001) | ||
1092 | #define NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_TYPE (0x00000002) | ||
1093 | #define NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_OFFSET (0x00000004) | ||
1094 | #define NVGPU_DBG_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008) | ||
1095 | #define NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_MASK (0x00000010) | ||
1096 | |||
1097 | struct nvgpu_dbg_gpu_reg_op { | ||
1098 | __u8 op; | ||
1099 | __u8 type; | ||
1100 | __u8 status; | ||
1101 | __u8 quad; | ||
1102 | __u32 group_mask; | ||
1103 | __u32 sub_group_mask; | ||
1104 | __u32 offset; | ||
1105 | __u32 value_lo; | ||
1106 | __u32 value_hi; | ||
1107 | __u32 and_n_mask_lo; | ||
1108 | __u32 and_n_mask_hi; | ||
1109 | }; | ||
1110 | |||
1111 | struct nvgpu_dbg_gpu_exec_reg_ops_args { | ||
1112 | __u64 ops; /* pointer to nvgpu_reg_op operations */ | ||
1113 | __u32 num_ops; | ||
1114 | __u32 _pad0[1]; | ||
1115 | }; | ||
1116 | |||
1117 | #define NVGPU_DBG_GPU_IOCTL_REG_OPS \ | ||
1118 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 2, struct nvgpu_dbg_gpu_exec_reg_ops_args) | ||
1119 | |||
1120 | /* Enable/disable/clear event notifications */ | ||
1121 | struct nvgpu_dbg_gpu_events_ctrl_args { | ||
1122 | __u32 cmd; /* in */ | ||
1123 | __u32 _pad0[1]; | ||
1124 | }; | ||
1125 | |||
1126 | /* valid event ctrl values */ | ||
1127 | #define NVGPU_DBG_GPU_EVENTS_CTRL_CMD_DISABLE (0x00000000) | ||
1128 | #define NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE (0x00000001) | ||
1129 | #define NVGPU_DBG_GPU_EVENTS_CTRL_CMD_CLEAR (0x00000002) | ||
1130 | |||
1131 | #define NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL \ | ||
1132 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 3, struct nvgpu_dbg_gpu_events_ctrl_args) | ||
1133 | |||
1134 | |||
1135 | /* Powergate/Unpowergate control */ | ||
1136 | |||
1137 | #define NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE 1 | ||
1138 | #define NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE 2 | ||
1139 | |||
1140 | struct nvgpu_dbg_gpu_powergate_args { | ||
1141 | __u32 mode; | ||
1142 | } __packed; | ||
1143 | |||
1144 | #define NVGPU_DBG_GPU_IOCTL_POWERGATE \ | ||
1145 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 4, struct nvgpu_dbg_gpu_powergate_args) | ||
1146 | |||
1147 | |||
1148 | /* SMPC Context Switch Mode */ | ||
1149 | #define NVGPU_DBG_GPU_SMPC_CTXSW_MODE_NO_CTXSW (0x00000000) | ||
1150 | #define NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW (0x00000001) | ||
1151 | |||
1152 | struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args { | ||
1153 | __u32 mode; | ||
1154 | } __packed; | ||
1155 | |||
1156 | #define NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE \ | ||
1157 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 5, struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args) | ||
1158 | |||
1159 | /* Suspend /Resume SM control */ | ||
1160 | #define NVGPU_DBG_GPU_SUSPEND_ALL_SMS 1 | ||
1161 | #define NVGPU_DBG_GPU_RESUME_ALL_SMS 2 | ||
1162 | |||
1163 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args { | ||
1164 | __u32 mode; | ||
1165 | } __packed; | ||
1166 | |||
1167 | #define NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS \ | ||
1168 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 6, struct nvgpu_dbg_gpu_suspend_resume_all_sms_args) | ||
1169 | |||
1170 | struct nvgpu_dbg_gpu_perfbuf_map_args { | ||
1171 | __u32 dmabuf_fd; /* in */ | ||
1172 | __u32 reserved; | ||
1173 | __u64 mapping_size; /* in, size of mapped buffer region */ | ||
1174 | __u64 offset; /* out, virtual address of the mapping */ | ||
1175 | }; | ||
1176 | |||
1177 | struct nvgpu_dbg_gpu_perfbuf_unmap_args { | ||
1178 | __u64 offset; | ||
1179 | }; | ||
1180 | |||
1181 | #define NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP \ | ||
1182 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 7, struct nvgpu_dbg_gpu_perfbuf_map_args) | ||
1183 | #define NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP \ | ||
1184 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 8, struct nvgpu_dbg_gpu_perfbuf_unmap_args) | ||
1185 | |||
1186 | /* Enable/disable PC Sampling */ | ||
1187 | struct nvgpu_dbg_gpu_pc_sampling_args { | ||
1188 | __u32 enable; | ||
1189 | __u32 _pad0[1]; | ||
1190 | }; | ||
1191 | |||
1192 | #define NVGPU_DBG_GPU_IOCTL_PC_SAMPLING_DISABLE 0 | ||
1193 | #define NVGPU_DBG_GPU_IOCTL_PC_SAMPLING_ENABLE 1 | ||
1194 | |||
1195 | #define NVGPU_DBG_GPU_IOCTL_PC_SAMPLING \ | ||
1196 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 9, struct nvgpu_dbg_gpu_pc_sampling_args) | ||
1197 | |||
1198 | /* Enable/Disable timeouts */ | ||
1199 | #define NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE 1 | ||
1200 | #define NVGPU_DBG_GPU_IOCTL_TIMEOUT_DISABLE 0 | ||
1201 | |||
1202 | struct nvgpu_dbg_gpu_timeout_args { | ||
1203 | __u32 enable; | ||
1204 | __u32 padding; | ||
1205 | }; | ||
1206 | |||
1207 | #define NVGPU_DBG_GPU_IOCTL_TIMEOUT \ | ||
1208 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 10, struct nvgpu_dbg_gpu_timeout_args) | ||
1209 | |||
1210 | #define NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT \ | ||
1211 | _IOR(NVGPU_DBG_GPU_IOCTL_MAGIC, 11, struct nvgpu_dbg_gpu_timeout_args) | ||
1212 | |||
1213 | |||
1214 | struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args { | ||
1215 | __u32 broadcast; | ||
1216 | __u32 reserved; | ||
1217 | }; | ||
1218 | |||
1219 | #define NVGPU_DBG_GPU_IOCTL_SET_NEXT_STOP_TRIGGER_TYPE \ | ||
1220 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args) | ||
1221 | |||
1222 | |||
1223 | /* PM Context Switch Mode */ | ||
1224 | #define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000) | ||
1225 | #define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW (0x00000001) | ||
1226 | |||
1227 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args { | ||
1228 | __u32 mode; | ||
1229 | __u32 reserved; | ||
1230 | }; | ||
1231 | |||
1232 | #define NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE \ | ||
1233 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 13, struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args) | ||
1234 | |||
1235 | |||
1236 | struct nvgpu_dbg_gpu_sm_error_state_record { | ||
1237 | __u32 hww_global_esr; | ||
1238 | __u32 hww_warp_esr; | ||
1239 | __u64 hww_warp_esr_pc; | ||
1240 | __u32 hww_global_esr_report_mask; | ||
1241 | __u32 hww_warp_esr_report_mask; | ||
1242 | |||
1243 | /* | ||
1244 | * Notes | ||
1245 | * - This struct can be safely appended with new fields. However, always | ||
1246 | * keep the structure size multiple of 8 and make sure that the binary | ||
1247 | * layout does not change between 32-bit and 64-bit architectures. | ||
1248 | */ | ||
1249 | }; | ||
1250 | |||
1251 | struct nvgpu_dbg_gpu_read_single_sm_error_state_args { | ||
1252 | __u32 sm_id; | ||
1253 | __u32 padding; | ||
1254 | __u64 sm_error_state_record_mem; | ||
1255 | __u64 sm_error_state_record_size; | ||
1256 | }; | ||
1257 | |||
1258 | #define NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE \ | ||
1259 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 14, struct nvgpu_dbg_gpu_read_single_sm_error_state_args) | ||
1260 | |||
1261 | |||
1262 | struct nvgpu_dbg_gpu_clear_single_sm_error_state_args { | ||
1263 | __u32 sm_id; | ||
1264 | __u32 padding; | ||
1265 | }; | ||
1266 | |||
1267 | #define NVGPU_DBG_GPU_IOCTL_CLEAR_SINGLE_SM_ERROR_STATE \ | ||
1268 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 15, struct nvgpu_dbg_gpu_clear_single_sm_error_state_args) | ||
1269 | |||
1270 | |||
1271 | struct nvgpu_dbg_gpu_write_single_sm_error_state_args { | ||
1272 | __u32 sm_id; | ||
1273 | __u32 padding; | ||
1274 | __u64 sm_error_state_record_mem; | ||
1275 | __u64 sm_error_state_record_size; | ||
1276 | }; | ||
1277 | |||
1278 | #define NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE \ | ||
1279 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 16, struct nvgpu_dbg_gpu_write_single_sm_error_state_args) | ||
1280 | |||
1281 | /* | ||
1282 | * Unbinding/detaching a debugger session from a nvgpu channel | ||
1283 | * | ||
1284 | * The 'channel_fd' given here is the fd used to allocate the | ||
1285 | * gpu channel context. | ||
1286 | */ | ||
1287 | struct nvgpu_dbg_gpu_unbind_channel_args { | ||
1288 | __u32 channel_fd; /* in */ | ||
1289 | __u32 _pad0[1]; | ||
1290 | }; | ||
1291 | |||
1292 | #define NVGPU_DBG_GPU_IOCTL_UNBIND_CHANNEL \ | ||
1293 | _IOW(NVGPU_DBG_GPU_IOCTL_MAGIC, 17, struct nvgpu_dbg_gpu_unbind_channel_args) | ||
1294 | |||
1295 | |||
1296 | #define NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS 1 | ||
1297 | #define NVGPU_DBG_GPU_RESUME_ALL_CONTEXTS 2 | ||
1298 | |||
1299 | struct nvgpu_dbg_gpu_suspend_resume_contexts_args { | ||
1300 | __u32 action; | ||
1301 | __u32 is_resident_context; | ||
1302 | __s32 resident_context_fd; | ||
1303 | __u32 padding; | ||
1304 | }; | ||
1305 | |||
1306 | #define NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS \ | ||
1307 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 18, struct nvgpu_dbg_gpu_suspend_resume_contexts_args) | ||
1308 | |||
1309 | |||
1310 | #define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ 1 | ||
1311 | #define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_WRITE 2 | ||
1312 | |||
1313 | struct nvgpu_dbg_gpu_access_fb_memory_args { | ||
1314 | __u32 cmd; /* in: either read or write */ | ||
1315 | |||
1316 | __s32 dmabuf_fd; /* in: dmabuf fd of the buffer in FB */ | ||
1317 | __u64 offset; /* in: offset within buffer in FB, should be 4B aligned */ | ||
1318 | |||
1319 | __u64 buffer; /* in/out: temp buffer to read/write from */ | ||
1320 | __u64 size; /* in: size of the buffer i.e. size of read/write in bytes, should be 4B aligned */ | ||
1321 | }; | ||
1322 | |||
1323 | #define NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY \ | ||
1324 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 19, struct nvgpu_dbg_gpu_access_fb_memory_args) | ||
1325 | |||
1326 | struct nvgpu_dbg_gpu_profiler_obj_mgt_args { | ||
1327 | __u32 profiler_handle; | ||
1328 | __u32 reserved; | ||
1329 | }; | ||
1330 | |||
1331 | #define NVGPU_DBG_GPU_IOCTL_PROFILER_ALLOCATE \ | ||
1332 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 20, struct nvgpu_dbg_gpu_profiler_obj_mgt_args) | ||
1333 | |||
1334 | #define NVGPU_DBG_GPU_IOCTL_PROFILER_FREE \ | ||
1335 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 21, struct nvgpu_dbg_gpu_profiler_obj_mgt_args) | ||
1336 | |||
1337 | struct nvgpu_dbg_gpu_profiler_reserve_args { | ||
1338 | __u32 profiler_handle; | ||
1339 | __u32 acquire; | ||
1340 | }; | ||
1341 | |||
1342 | #define NVGPU_DBG_GPU_IOCTL_PROFILER_RESERVE \ | ||
1343 | _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 22, struct nvgpu_dbg_gpu_profiler_reserve_args) | ||
1344 | |||
1345 | #define NVGPU_DBG_GPU_IOCTL_LAST \ | ||
1346 | _IOC_NR(NVGPU_DBG_GPU_IOCTL_PROFILER_RESERVE) | ||
1347 | |||
1348 | #define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ | ||
1349 | sizeof(struct nvgpu_dbg_gpu_access_fb_memory_args) | ||
1350 | |||
1351 | /* | ||
1352 | * /dev/nvhost-gpu device | ||
1353 | */ | ||
1354 | |||
1355 | #define NVGPU_IOCTL_MAGIC 'H' | ||
1356 | #define NVGPU_NO_TIMEOUT ((u32)~0) | ||
1357 | #define NVGPU_TIMEOUT_FLAG_DISABLE_DUMP 0 | ||
1358 | |||
1359 | /* this is also the hardware memory format */ | ||
1360 | struct nvgpu_gpfifo { | ||
1361 | __u32 entry0; /* first word of gpfifo entry */ | ||
1362 | __u32 entry1; /* second word of gpfifo entry */ | ||
1363 | }; | ||
1364 | |||
1365 | struct nvgpu_get_param_args { | ||
1366 | __u32 value; | ||
1367 | } __packed; | ||
1368 | |||
1369 | struct nvgpu_channel_open_args { | ||
1370 | union { | ||
1371 | __s32 channel_fd; /* deprecated: use out.channel_fd instead */ | ||
1372 | struct { | ||
1373 | /* runlist_id is the runlist for the | ||
1374 | * channel. Basically, the runlist specifies the target | ||
1375 | * engine(s) for which the channel is | ||
1376 | * opened. Runlist_id -1 is synonym for the primary | ||
1377 | * graphics runlist. */ | ||
1378 | __s32 runlist_id; | ||
1379 | } in; | ||
1380 | struct { | ||
1381 | __s32 channel_fd; | ||
1382 | } out; | ||
1383 | }; | ||
1384 | }; | ||
1385 | |||
1386 | struct nvgpu_set_nvmap_fd_args { | ||
1387 | __u32 fd; | ||
1388 | } __packed; | ||
1389 | |||
1390 | #define NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO (1 << 0) | ||
1391 | |||
1392 | struct nvgpu_alloc_obj_ctx_args { | ||
1393 | __u32 class_num; /* kepler3d, 2d, compute, etc */ | ||
1394 | __u32 flags; /* input, output */ | ||
1395 | __u64 obj_id; /* output, used to free later */ | ||
1396 | }; | ||
1397 | |||
1398 | struct nvgpu_alloc_gpfifo_args { | ||
1399 | __u32 num_entries; | ||
1400 | #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ | ||
1401 | __u32 flags; | ||
1402 | }; | ||
1403 | |||
1404 | struct nvgpu_alloc_gpfifo_ex_args { | ||
1405 | __u32 num_entries; | ||
1406 | __u32 num_inflight_jobs; | ||
1407 | /* Set owner channel of this gpfifo as a vpr channel. */ | ||
1408 | #define NVGPU_ALLOC_GPFIFO_EX_FLAGS_VPR_ENABLED (1 << 0) | ||
1409 | /* | ||
1410 | * Channel shall exhibit deterministic behavior in the submit path. | ||
1411 | * | ||
1412 | * NOTE: as an exception, VPR resize may still cause the GPU to reset at any | ||
1413 | * time, which is not deterministic behavior. If this is not acceptable, the | ||
1414 | * user has to make sure that VPR resize does not occur. | ||
1415 | * | ||
1416 | * With this flag, any submits with in-kernel job tracking also require that | ||
1417 | * num_inflight_jobs is nonzero, and additionally that | ||
1418 | * NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL is found in gpu | ||
1419 | * characteristics.flags. | ||
1420 | * | ||
1421 | * Note that fast submits (with no in-kernel job tracking) are also | ||
1422 | * deterministic and are supported if the characteristics flags contain | ||
1423 | * NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING; this flag or | ||
1424 | * num_inflight_jobs are not necessary in that case. | ||
1425 | */ | ||
1426 | #define NVGPU_ALLOC_GPFIFO_EX_FLAGS_DETERMINISTIC (1 << 1) | ||
1427 | __u32 flags; | ||
1428 | __u32 reserved[5]; | ||
1429 | }; | ||
1430 | |||
1431 | struct nvgpu_fence { | ||
1432 | __u32 id; /* syncpoint id or sync fence fd */ | ||
1433 | __u32 value; /* syncpoint value (discarded when using sync fence) */ | ||
1434 | }; | ||
1435 | |||
1436 | /* insert a wait on the fence before submitting gpfifo */ | ||
1437 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT (1 << 0) | ||
1438 | /* insert a fence update after submitting gpfifo and | ||
1439 | return the new fence for others to wait on */ | ||
1440 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET (1 << 1) | ||
1441 | /* choose between different gpfifo entry formats */ | ||
1442 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_HW_FORMAT (1 << 2) | ||
1443 | /* interpret fence as a sync fence fd instead of raw syncpoint fence */ | ||
1444 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE (1 << 3) | ||
1445 | /* suppress WFI before fence trigger */ | ||
1446 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_SUPPRESS_WFI (1 << 4) | ||
1447 | /* skip buffer refcounting during submit */ | ||
1448 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_SKIP_BUFFER_REFCOUNTING (1 << 5) | ||
1449 | /* expire current timeslice and reschedule runlist from front */ | ||
1450 | #define NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST (1 << 6) | ||
1451 | |||
1452 | struct nvgpu_submit_gpfifo_args { | ||
1453 | __u64 gpfifo; | ||
1454 | __u32 num_entries; | ||
1455 | __u32 flags; | ||
1456 | struct nvgpu_fence fence; | ||
1457 | }; | ||
1458 | |||
1459 | struct nvgpu_wait_args { | ||
1460 | #define NVGPU_WAIT_TYPE_NOTIFIER 0x0 | ||
1461 | #define NVGPU_WAIT_TYPE_SEMAPHORE 0x1 | ||
1462 | __u32 type; | ||
1463 | __u32 timeout; | ||
1464 | union { | ||
1465 | struct { | ||
1466 | /* handle and offset for notifier memory */ | ||
1467 | __u32 dmabuf_fd; | ||
1468 | __u32 offset; | ||
1469 | __u32 padding1; | ||
1470 | __u32 padding2; | ||
1471 | } notifier; | ||
1472 | struct { | ||
1473 | /* handle and offset for semaphore memory */ | ||
1474 | __u32 dmabuf_fd; | ||
1475 | __u32 offset; | ||
1476 | /* semaphore payload to wait for */ | ||
1477 | __u32 payload; | ||
1478 | __u32 padding; | ||
1479 | } semaphore; | ||
1480 | } condition; /* determined by type field */ | ||
1481 | }; | ||
1482 | |||
1483 | /* cycle stats support */ | ||
1484 | struct nvgpu_cycle_stats_args { | ||
1485 | __u32 dmabuf_fd; | ||
1486 | } __packed; | ||
1487 | |||
1488 | struct nvgpu_set_timeout_args { | ||
1489 | __u32 timeout; | ||
1490 | } __packed; | ||
1491 | |||
1492 | struct nvgpu_set_timeout_ex_args { | ||
1493 | __u32 timeout; | ||
1494 | __u32 flags; | ||
1495 | }; | ||
1496 | |||
1497 | #define NVGPU_ZCULL_MODE_GLOBAL 0 | ||
1498 | #define NVGPU_ZCULL_MODE_NO_CTXSW 1 | ||
1499 | #define NVGPU_ZCULL_MODE_SEPARATE_BUFFER 2 | ||
1500 | #define NVGPU_ZCULL_MODE_PART_OF_REGULAR_BUF 3 | ||
1501 | |||
1502 | struct nvgpu_zcull_bind_args { | ||
1503 | __u64 gpu_va; | ||
1504 | __u32 mode; | ||
1505 | __u32 padding; | ||
1506 | }; | ||
1507 | |||
1508 | struct nvgpu_set_error_notifier { | ||
1509 | __u64 offset; | ||
1510 | __u64 size; | ||
1511 | __u32 mem; | ||
1512 | __u32 padding; | ||
1513 | }; | ||
1514 | |||
1515 | struct nvgpu_notification { | ||
1516 | struct { /* 0000- */ | ||
1517 | __u32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 */ | ||
1518 | } time_stamp; /* -0007 */ | ||
1519 | __u32 info32; /* info returned depends on method 0008-000b */ | ||
1520 | #define NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8 | ||
1521 | #define NVGPU_CHANNEL_GR_ERROR_SW_METHOD 12 | ||
1522 | #define NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY 13 | ||
1523 | #define NVGPU_CHANNEL_GR_EXCEPTION 13 | ||
1524 | #define NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT 24 | ||
1525 | #define NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY 25 | ||
1526 | #define NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 | ||
1527 | #define NVGPU_CHANNEL_PBDMA_ERROR 32 | ||
1528 | #define NVGPU_CHANNEL_FECS_ERR_UNIMP_FIRMWARE_METHOD 37 | ||
1529 | #define NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR 43 | ||
1530 | #define NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH 80 | ||
1531 | __u16 info16; /* info returned depends on method 000c-000d */ | ||
1532 | __u16 status; /* user sets bit 15, NV sets status 000e-000f */ | ||
1533 | #define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 | ||
1534 | }; | ||
1535 | |||
1536 | /* cycle stats snapshot buffer support for mode E */ | ||
1537 | struct nvgpu_cycle_stats_snapshot_args { | ||
1538 | __u32 cmd; /* in: command to handle */ | ||
1539 | __u32 dmabuf_fd; /* in: dma buffer handler */ | ||
1540 | __u32 extra; /* in/out: extra payload e.g.*/ | ||
1541 | /* counter/start perfmon */ | ||
1542 | __u32 pad0[1]; | ||
1543 | }; | ||
1544 | |||
1545 | /* valid commands to control cycle stats shared buffer */ | ||
1546 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH 0 | ||
1547 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH 1 | ||
1548 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH 2 | ||
1549 | |||
1550 | /* disable watchdog per-channel */ | ||
1551 | struct nvgpu_channel_wdt_args { | ||
1552 | __u32 wdt_status; | ||
1553 | __u32 padding; | ||
1554 | }; | ||
1555 | #define NVGPU_IOCTL_CHANNEL_DISABLE_WDT 1 | ||
1556 | #define NVGPU_IOCTL_CHANNEL_ENABLE_WDT 2 | ||
1557 | |||
1558 | /* | ||
1559 | * Interleaving channels in a runlist is an approach to improve | ||
1560 | * GPU scheduling by allowing certain channels to appear multiple | ||
1561 | * times on the runlist. The number of times a channel appears is | ||
1562 | * governed by the following levels: | ||
1563 | * | ||
1564 | * low (L) : appears once | ||
1565 | * medium (M): if L, appears L times | ||
1566 | * else, appears once | ||
1567 | * high (H) : if L, appears (M + 1) x L times | ||
1568 | * else if M, appears M times | ||
1569 | * else, appears once | ||
1570 | */ | ||
1571 | struct nvgpu_runlist_interleave_args { | ||
1572 | __u32 level; | ||
1573 | __u32 reserved; | ||
1574 | }; | ||
1575 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW 0 | ||
1576 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM 1 | ||
1577 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH 2 | ||
1578 | #define NVGPU_RUNLIST_INTERLEAVE_NUM_LEVELS 3 | ||
1579 | |||
1580 | /* controls how long a channel occupies an engine uninterrupted */ | ||
1581 | struct nvgpu_timeslice_args { | ||
1582 | __u32 timeslice_us; | ||
1583 | __u32 reserved; | ||
1584 | }; | ||
1585 | |||
1586 | struct nvgpu_event_id_ctrl_args { | ||
1587 | __u32 cmd; /* in */ | ||
1588 | __u32 event_id; /* in */ | ||
1589 | __s32 event_fd; /* out */ | ||
1590 | __u32 padding; | ||
1591 | }; | ||
1592 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 | ||
1593 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 | ||
1594 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 | ||
1595 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN 5 | ||
1596 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 6 | ||
1597 | |||
1598 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 | ||
1599 | |||
1600 | struct nvgpu_preemption_mode_args { | ||
1601 | /* only one should be enabled at a time */ | ||
1602 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI (1 << 0) | ||
1603 | __u32 graphics_preempt_mode; /* in */ | ||
1604 | |||
1605 | /* only one should be enabled at a time */ | ||
1606 | #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI (1 << 0) | ||
1607 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA (1 << 1) | ||
1608 | __u32 compute_preempt_mode; /* in */ | ||
1609 | }; | ||
1610 | |||
1611 | struct nvgpu_boosted_ctx_args { | ||
1612 | #define NVGPU_BOOSTED_CTX_MODE_NORMAL (0U) | ||
1613 | #define NVGPU_BOOSTED_CTX_MODE_BOOSTED_EXECUTION (1U) | ||
1614 | __u32 boost; | ||
1615 | __u32 padding; | ||
1616 | }; | ||
1617 | |||
1618 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ | ||
1619 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) | ||
1620 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ | ||
1621 | _IOW(NVGPU_IOCTL_MAGIC, 11, struct nvgpu_set_timeout_args) | ||
1622 | #define NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT \ | ||
1623 | _IOR(NVGPU_IOCTL_MAGIC, 12, struct nvgpu_get_param_args) | ||
1624 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX \ | ||
1625 | _IOWR(NVGPU_IOCTL_MAGIC, 18, struct nvgpu_set_timeout_ex_args) | ||
1626 | #define NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO \ | ||
1627 | _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args) | ||
1628 | #define NVGPU_IOCTL_CHANNEL_WAIT \ | ||
1629 | _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args) | ||
1630 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS \ | ||
1631 | _IOWR(NVGPU_IOCTL_MAGIC, 106, struct nvgpu_cycle_stats_args) | ||
1632 | #define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \ | ||
1633 | _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) | ||
1634 | #define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ | ||
1635 | _IOWR(NVGPU_IOCTL_MAGIC, 108, struct nvgpu_alloc_obj_ctx_args) | ||
1636 | #define NVGPU_IOCTL_CHANNEL_ZCULL_BIND \ | ||
1637 | _IOWR(NVGPU_IOCTL_MAGIC, 110, struct nvgpu_zcull_bind_args) | ||
1638 | #define NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER \ | ||
1639 | _IOWR(NVGPU_IOCTL_MAGIC, 111, struct nvgpu_set_error_notifier) | ||
1640 | #define NVGPU_IOCTL_CHANNEL_OPEN \ | ||
1641 | _IOR(NVGPU_IOCTL_MAGIC, 112, struct nvgpu_channel_open_args) | ||
1642 | #define NVGPU_IOCTL_CHANNEL_ENABLE \ | ||
1643 | _IO(NVGPU_IOCTL_MAGIC, 113) | ||
1644 | #define NVGPU_IOCTL_CHANNEL_DISABLE \ | ||
1645 | _IO(NVGPU_IOCTL_MAGIC, 114) | ||
1646 | #define NVGPU_IOCTL_CHANNEL_PREEMPT \ | ||
1647 | _IO(NVGPU_IOCTL_MAGIC, 115) | ||
1648 | #define NVGPU_IOCTL_CHANNEL_FORCE_RESET \ | ||
1649 | _IO(NVGPU_IOCTL_MAGIC, 116) | ||
1650 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ | ||
1651 | _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) | ||
1652 | #define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \ | ||
1653 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) | ||
1654 | #define NVGPU_IOCTL_CHANNEL_WDT \ | ||
1655 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) | ||
1656 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ | ||
1657 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) | ||
1658 | #define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ | ||
1659 | _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) | ||
1660 | #define NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE \ | ||
1661 | _IOW(NVGPU_IOCTL_MAGIC, 122, struct nvgpu_preemption_mode_args) | ||
1662 | #define NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX \ | ||
1663 | _IOW(NVGPU_IOCTL_MAGIC, 123, struct nvgpu_alloc_gpfifo_ex_args) | ||
1664 | #define NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTX \ | ||
1665 | _IOW(NVGPU_IOCTL_MAGIC, 124, struct nvgpu_boosted_ctx_args) | ||
1666 | #define NVGPU_IOCTL_CHANNEL_GET_TIMESLICE \ | ||
1667 | _IOW(NVGPU_IOCTL_MAGIC, 125, struct nvgpu_timeslice_args) | ||
1668 | |||
1669 | #define NVGPU_IOCTL_CHANNEL_LAST \ | ||
1670 | _IOC_NR(NVGPU_IOCTL_CHANNEL_GET_TIMESLICE) | ||
1671 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_alloc_gpfifo_ex_args) | ||
1672 | |||
1673 | /* | ||
1674 | * /dev/nvhost-as-gpu device | ||
1675 | * | ||
1676 | * Opening a '/dev/nvhost-as-gpu' device node creates a new address | ||
1677 | * space. nvgpu channels (for the same module) can then be bound to such an | ||
1678 | * address space to define the addresses it has access to. | ||
1679 | * | ||
1680 | * Once a nvgpu channel has been bound to an address space it cannot be | ||
1681 | * unbound. There is no support for allowing an nvgpu channel to change from | ||
1682 | * one address space to another (or from one to none). | ||
1683 | * | ||
1684 | * As long as there is an open device file to the address space, or any bound | ||
1685 | * nvgpu channels it will be valid. Once all references to the address space | ||
1686 | * are removed the address space is deleted. | ||
1687 | * | ||
1688 | */ | ||
1689 | |||
1690 | #define NVGPU_AS_IOCTL_MAGIC 'A' | ||
1691 | |||
1692 | /* | ||
1693 | * Allocating an address space range: | ||
1694 | * | ||
1695 | * Address ranges created with this ioctl are reserved for later use with | ||
1696 | * fixed-address buffer mappings. | ||
1697 | * | ||
1698 | * If _FLAGS_FIXED_OFFSET is specified then the new range starts at the 'offset' | ||
1699 | * given. Otherwise the address returned is chosen to be a multiple of 'align.' | ||
1700 | * | ||
1701 | */ | ||
1702 | struct nvgpu32_as_alloc_space_args { | ||
1703 | __u32 pages; /* in, pages */ | ||
1704 | __u32 page_size; /* in, bytes */ | ||
1705 | __u32 flags; /* in */ | ||
1706 | #define NVGPU_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET 0x1 | ||
1707 | #define NVGPU_AS_ALLOC_SPACE_FLAGS_SPARSE 0x2 | ||
1708 | union { | ||
1709 | __u64 offset; /* inout, byte address valid iff _FIXED_OFFSET */ | ||
1710 | __u64 align; /* in, alignment multiple (0:={1 or n/a}) */ | ||
1711 | } o_a; | ||
1712 | }; | ||
1713 | |||
1714 | struct nvgpu_as_alloc_space_args { | ||
1715 | __u32 pages; /* in, pages */ | ||
1716 | __u32 page_size; /* in, bytes */ | ||
1717 | __u32 flags; /* in */ | ||
1718 | __u32 padding; /* in */ | ||
1719 | union { | ||
1720 | __u64 offset; /* inout, byte address valid iff _FIXED_OFFSET */ | ||
1721 | __u64 align; /* in, alignment multiple (0:={1 or n/a}) */ | ||
1722 | } o_a; | ||
1723 | }; | ||
1724 | |||
1725 | /* | ||
1726 | * Releasing an address space range: | ||
1727 | * | ||
1728 | * The previously allocated region starting at 'offset' is freed. If there are | ||
1729 | * any buffers currently mapped inside the region the ioctl will fail. | ||
1730 | */ | ||
1731 | struct nvgpu_as_free_space_args { | ||
1732 | __u64 offset; /* in, byte address */ | ||
1733 | __u32 pages; /* in, pages */ | ||
1734 | __u32 page_size; /* in, bytes */ | ||
1735 | }; | ||
1736 | |||
1737 | /* | ||
1738 | * Binding a nvgpu channel to an address space: | ||
1739 | * | ||
1740 | * A channel must be bound to an address space before allocating a gpfifo | ||
1741 | * in nvgpu. The 'channel_fd' given here is the fd used to allocate the | ||
1742 | * channel. Once a channel has been bound to an address space it cannot | ||
1743 | * be unbound (except for when the channel is destroyed). | ||
1744 | */ | ||
1745 | struct nvgpu_as_bind_channel_args { | ||
1746 | __u32 channel_fd; /* in */ | ||
1747 | } __packed; | ||
1748 | |||
1749 | /* | ||
1750 | * Mapping nvmap buffers into an address space: | ||
1751 | * | ||
1752 | * The start address is the 'offset' given if _FIXED_OFFSET is specified. | ||
1753 | * Otherwise the address returned is a multiple of 'align.' | ||
1754 | * | ||
1755 | * If 'page_size' is set to 0 the nvmap buffer's allocation alignment/sizing | ||
1756 | * will be used to determine the page size (largest possible). The page size | ||
1757 | * chosen will be returned back to the caller in the 'page_size' parameter in | ||
1758 | * that case. | ||
1759 | */ | ||
1760 | #define NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET (1 << 0) | ||
1761 | #define NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE (1 << 2) | ||
1762 | #define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT (1 << 4) | ||
1763 | #define NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE (1 << 5) | ||
1764 | #define NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS (1 << 6) | ||
1765 | #define NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL (1 << 8) | ||
1766 | |||
1767 | /* | ||
1768 | * Mapping dmabuf fds into an address space: | ||
1769 | * | ||
1770 | * The caller requests a mapping to a particular page 'kind'. | ||
1771 | * | ||
1772 | * If 'page_size' is set to 0 the dmabuf's alignment/sizing will be used to | ||
1773 | * determine the page size (largest possible). The page size chosen will be | ||
1774 | * returned back to the caller in the 'page_size' parameter in that case. | ||
1775 | */ | ||
1776 | struct nvgpu_as_map_buffer_ex_args { | ||
1777 | /* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */ | ||
1778 | __u32 flags; /* in/out */ | ||
1779 | |||
1780 | /* | ||
1781 | * - If both compr_kind and incompr_kind are set | ||
1782 | * (i.e., value is other than NV_KIND_INVALID), | ||
1783 | * kernel attempts to use compr_kind first. | ||
1784 | * | ||
1785 | * - If compr_kind is set, kernel attempts to allocate | ||
1786 | * comptags for the buffer. If successful, | ||
1787 | * compr_kind is used as the PTE kind. | ||
1788 | * | ||
1789 | * - If incompr_kind is set, kernel uses incompr_kind as the | ||
1790 | * PTE kind, if compr_kind cannot be used. Comptags are not | ||
1791 | * allocated. | ||
1792 | * | ||
1793 | * - If neither compr_kind or incompr_kind is set, the | ||
1794 | * map call will fail. | ||
1795 | */ | ||
1796 | #define NV_KIND_INVALID -1 | ||
1797 | __s16 compr_kind; | ||
1798 | __s16 incompr_kind; | ||
1799 | |||
1800 | __u32 dmabuf_fd; /* in */ | ||
1801 | __u32 page_size; /* inout, 0:= best fit to buffer */ | ||
1802 | |||
1803 | __u64 buffer_offset; /* in, offset of mapped buffer region */ | ||
1804 | __u64 mapping_size; /* in, size of mapped buffer region */ | ||
1805 | |||
1806 | __u64 offset; /* in/out, we use this address if flag | ||
1807 | * FIXED_OFFSET is set. This will fail | ||
1808 | * if space is not properly allocated. The | ||
1809 | * actual virtual address to which we mapped | ||
1810 | * the buffer is returned in this field. */ | ||
1811 | }; | ||
1812 | |||
1813 | /* | ||
1814 | * Get info about buffer compbits. Requires that buffer is mapped with | ||
1815 | * NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS. | ||
1816 | * | ||
1817 | * The compbits for a mappable buffer are organized in a mappable | ||
1818 | * window to the compbits store. In case the window contains comptags | ||
1819 | * for more than one buffer, the buffer comptag line index may differ | ||
1820 | * from the window comptag line index. | ||
1821 | */ | ||
1822 | struct nvgpu_as_get_buffer_compbits_info_args { | ||
1823 | |||
1824 | /* in: address of an existing buffer mapping */ | ||
1825 | __u64 mapping_gva; | ||
1826 | |||
1827 | /* out: size of compbits mapping window (bytes) */ | ||
1828 | __u64 compbits_win_size; | ||
1829 | |||
1830 | /* out: comptag line index of the window start */ | ||
1831 | __u32 compbits_win_ctagline; | ||
1832 | |||
1833 | /* out: comptag line index of the buffer mapping */ | ||
1834 | __u32 mapping_ctagline; | ||
1835 | |||
1836 | /* Buffer uses compbits */ | ||
1837 | #define NVGPU_AS_GET_BUFFER_COMPBITS_INFO_FLAGS_HAS_COMPBITS (1 << 0) | ||
1838 | |||
1839 | /* Buffer compbits are mappable */ | ||
1840 | #define NVGPU_AS_GET_BUFFER_COMPBITS_INFO_FLAGS_MAPPABLE (1 << 1) | ||
1841 | |||
1842 | /* Buffer IOVA addresses are discontiguous */ | ||
1843 | #define NVGPU_AS_GET_BUFFER_COMPBITS_INFO_FLAGS_DISCONTIG_IOVA (1 << 2) | ||
1844 | |||
1845 | /* out */ | ||
1846 | __u32 flags; | ||
1847 | |||
1848 | __u32 reserved1; | ||
1849 | }; | ||
1850 | |||
1851 | /* | ||
1852 | * Map compbits of a mapped buffer to the GPU address space. The | ||
1853 | * compbits mapping is automatically unmapped when the buffer is | ||
1854 | * unmapped. | ||
1855 | * | ||
1856 | * The compbits mapping always uses small pages, it is read-only, and | ||
1857 | * is GPU cacheable. The mapping is a window to the compbits | ||
1858 | * store. The window may not be exactly the size of the cache lines | ||
1859 | * for the buffer mapping. | ||
1860 | */ | ||
1861 | struct nvgpu_as_map_buffer_compbits_args { | ||
1862 | |||
1863 | /* in: address of an existing buffer mapping */ | ||
1864 | __u64 mapping_gva; | ||
1865 | |||
1866 | /* in: gva to the mapped compbits store window when | ||
1867 | * FIXED_OFFSET is set. Otherwise, ignored and should be be 0. | ||
1868 | * | ||
1869 | * For FIXED_OFFSET mapping: | ||
1870 | * - If compbits are already mapped compbits_win_gva | ||
1871 | * must match with the previously mapped gva. | ||
1872 | * - The user must have allocated enough GVA space for the | ||
1873 | * mapping window (see compbits_win_size in | ||
1874 | * nvgpu_as_get_buffer_compbits_info_args) | ||
1875 | * | ||
1876 | * out: gva to the mapped compbits store window */ | ||
1877 | __u64 compbits_win_gva; | ||
1878 | |||
1879 | /* in: reserved, must be 0 | ||
1880 | out: physical or IOMMU address for mapping */ | ||
1881 | union { | ||
1882 | /* contiguous iova addresses */ | ||
1883 | __u64 mapping_iova; | ||
1884 | |||
1885 | /* buffer to receive discontiguous iova addresses (reserved) */ | ||
1886 | __u64 mapping_iova_buf_addr; | ||
1887 | }; | ||
1888 | |||
1889 | /* in: Buffer size (in bytes) for discontiguous iova | ||
1890 | * addresses. Reserved, must be 0. */ | ||
1891 | __u64 mapping_iova_buf_size; | ||
1892 | |||
1893 | #define NVGPU_AS_MAP_BUFFER_COMPBITS_FLAGS_FIXED_OFFSET (1 << 0) | ||
1894 | __u32 flags; | ||
1895 | __u32 reserved1; | ||
1896 | }; | ||
1897 | |||
1898 | /* | ||
1899 | * Unmapping a buffer: | ||
1900 | * | ||
1901 | * To unmap a previously mapped buffer set 'offset' to the offset returned in | ||
1902 | * the mapping call. This includes where a buffer has been mapped into a fixed | ||
1903 | * offset of a previously allocated address space range. | ||
1904 | */ | ||
1905 | struct nvgpu_as_unmap_buffer_args { | ||
1906 | __u64 offset; /* in, byte address */ | ||
1907 | }; | ||
1908 | |||
1909 | |||
1910 | struct nvgpu_as_va_region { | ||
1911 | __u64 offset; | ||
1912 | __u32 page_size; | ||
1913 | __u32 reserved; | ||
1914 | __u64 pages; | ||
1915 | }; | ||
1916 | |||
1917 | struct nvgpu_as_get_va_regions_args { | ||
1918 | __u64 buf_addr; /* Pointer to array of nvgpu_as_va_region:s. | ||
1919 | * Ignored if buf_size is 0 */ | ||
1920 | __u32 buf_size; /* in: userspace buf size (in bytes) | ||
1921 | out: kernel buf size (in bytes) */ | ||
1922 | __u32 reserved; | ||
1923 | }; | ||
1924 | |||
1925 | struct nvgpu_as_map_buffer_batch_args { | ||
1926 | __u64 unmaps; /* ptr to array of nvgpu_as_unmap_buffer_args */ | ||
1927 | __u64 maps; /* ptr to array of nvgpu_as_map_buffer_ex_args */ | ||
1928 | __u32 num_unmaps; /* in: number of unmaps | ||
1929 | * out: on error, number of successful unmaps */ | ||
1930 | __u32 num_maps; /* in: number of maps | ||
1931 | * out: on error, number of successful maps */ | ||
1932 | __u64 reserved; | ||
1933 | }; | ||
1934 | |||
1935 | #define NVGPU_AS_IOCTL_BIND_CHANNEL \ | ||
1936 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 1, struct nvgpu_as_bind_channel_args) | ||
1937 | #define NVGPU32_AS_IOCTL_ALLOC_SPACE \ | ||
1938 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 2, struct nvgpu32_as_alloc_space_args) | ||
1939 | #define NVGPU_AS_IOCTL_FREE_SPACE \ | ||
1940 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 3, struct nvgpu_as_free_space_args) | ||
1941 | #define NVGPU_AS_IOCTL_MAP_BUFFER \ | ||
1942 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 4, struct nvgpu_as_map_buffer_args) | ||
1943 | #define NVGPU_AS_IOCTL_UNMAP_BUFFER \ | ||
1944 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 5, struct nvgpu_as_unmap_buffer_args) | ||
1945 | #define NVGPU_AS_IOCTL_ALLOC_SPACE \ | ||
1946 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 6, struct nvgpu_as_alloc_space_args) | ||
1947 | #define NVGPU_AS_IOCTL_MAP_BUFFER_EX \ | ||
1948 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 7, struct nvgpu_as_map_buffer_ex_args) | ||
1949 | #define NVGPU_AS_IOCTL_GET_VA_REGIONS \ | ||
1950 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 8, struct nvgpu_as_get_va_regions_args) | ||
1951 | #define NVGPU_AS_IOCTL_GET_BUFFER_COMPBITS_INFO \ | ||
1952 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 9, struct nvgpu_as_get_buffer_compbits_info_args) | ||
1953 | #define NVGPU_AS_IOCTL_MAP_BUFFER_COMPBITS \ | ||
1954 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 10, struct nvgpu_as_map_buffer_compbits_args) | ||
1955 | #define NVGPU_AS_IOCTL_MAP_BUFFER_BATCH \ | ||
1956 | _IOWR(NVGPU_AS_IOCTL_MAGIC, 11, struct nvgpu_as_map_buffer_batch_args) | ||
1957 | |||
1958 | #define NVGPU_AS_IOCTL_LAST \ | ||
1959 | _IOC_NR(NVGPU_AS_IOCTL_MAP_BUFFER_BATCH) | ||
1960 | #define NVGPU_AS_IOCTL_MAX_ARG_SIZE \ | ||
1961 | sizeof(struct nvgpu_as_map_buffer_ex_args) | ||
1962 | |||
1963 | |||
1964 | /* | ||
1965 | * /dev/nvhost-ctxsw-gpu device | ||
1966 | * | ||
1967 | * Opening a '/dev/nvhost-ctxsw-gpu' device node creates a way to trace | ||
1968 | * context switches on GR engine | ||
1969 | */ | ||
1970 | |||
1971 | #define NVGPU_CTXSW_IOCTL_MAGIC 'C' | ||
1972 | |||
1973 | #define NVGPU_CTXSW_TAG_SOF 0x00 | ||
1974 | #define NVGPU_CTXSW_TAG_CTXSW_REQ_BY_HOST 0x01 | ||
1975 | #define NVGPU_CTXSW_TAG_FE_ACK 0x02 | ||
1976 | #define NVGPU_CTXSW_TAG_FE_ACK_WFI 0x0a | ||
1977 | #define NVGPU_CTXSW_TAG_FE_ACK_GFXP 0x0b | ||
1978 | #define NVGPU_CTXSW_TAG_FE_ACK_CTAP 0x0c | ||
1979 | #define NVGPU_CTXSW_TAG_FE_ACK_CILP 0x0d | ||
1980 | #define NVGPU_CTXSW_TAG_SAVE_END 0x03 | ||
1981 | #define NVGPU_CTXSW_TAG_RESTORE_START 0x04 | ||
1982 | #define NVGPU_CTXSW_TAG_CONTEXT_START 0x05 | ||
1983 | #define NVGPU_CTXSW_TAG_ENGINE_RESET 0xfe | ||
1984 | #define NVGPU_CTXSW_TAG_INVALID_TIMESTAMP 0xff | ||
1985 | #define NVGPU_CTXSW_TAG_LAST \ | ||
1986 | NVGPU_CTXSW_TAG_INVALID_TIMESTAMP | ||
1987 | |||
1988 | struct nvgpu_ctxsw_trace_entry { | ||
1989 | __u8 tag; | ||
1990 | __u8 vmid; | ||
1991 | __u16 seqno; /* sequence number to detect drops */ | ||
1992 | __u32 context_id; /* context_id as allocated by FECS */ | ||
1993 | __u64 pid; /* 64-bit is max bits of different OS pid */ | ||
1994 | __u64 timestamp; /* 64-bit time */ | ||
1995 | }; | ||
1996 | |||
1997 | #define NVGPU_CTXSW_RING_HEADER_MAGIC 0x7000fade | ||
1998 | #define NVGPU_CTXSW_RING_HEADER_VERSION 0 | ||
1999 | |||
2000 | struct nvgpu_ctxsw_ring_header { | ||
2001 | __u32 magic; | ||
2002 | __u32 version; | ||
2003 | __u32 num_ents; | ||
2004 | __u32 ent_size; | ||
2005 | volatile __u32 drop_count; /* excluding filtered out events */ | ||
2006 | volatile __u32 write_seqno; | ||
2007 | volatile __u32 write_idx; | ||
2008 | volatile __u32 read_idx; | ||
2009 | }; | ||
2010 | |||
2011 | struct nvgpu_ctxsw_ring_setup_args { | ||
2012 | __u32 size; /* [in/out] size of ring buffer in bytes (including | ||
2013 | header). will be rounded page size. this parameter | ||
2014 | is updated with actual allocated size. */ | ||
2015 | }; | ||
2016 | |||
2017 | #define NVGPU_CTXSW_FILTER_SIZE (NVGPU_CTXSW_TAG_LAST + 1) | ||
2018 | #define NVGPU_CTXSW_FILTER_SET(n, p) \ | ||
2019 | ((p)->tag_bits[(n) / 64] |= (1 << ((n) & 63))) | ||
2020 | #define NVGPU_CTXSW_FILTER_CLR(n, p) \ | ||
2021 | ((p)->tag_bits[(n) / 64] &= ~(1 << ((n) & 63))) | ||
2022 | #define NVGPU_CTXSW_FILTER_ISSET(n, p) \ | ||
2023 | ((p)->tag_bits[(n) / 64] & (1 << ((n) & 63))) | ||
2024 | #define NVGPU_CTXSW_FILTER_CLR_ALL(p) memset((void *)(p), 0, sizeof(*(p))) | ||
2025 | #define NVGPU_CTXSW_FILTER_SET_ALL(p) memset((void *)(p), ~0, sizeof(*(p))) | ||
2026 | |||
2027 | struct nvgpu_ctxsw_trace_filter { | ||
2028 | __u64 tag_bits[(NVGPU_CTXSW_FILTER_SIZE + 63) / 64]; | ||
2029 | }; | ||
2030 | |||
2031 | struct nvgpu_ctxsw_trace_filter_args { | ||
2032 | struct nvgpu_ctxsw_trace_filter filter; | ||
2033 | }; | ||
2034 | |||
2035 | #define NVGPU_CTXSW_IOCTL_TRACE_ENABLE \ | ||
2036 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 1) | ||
2037 | #define NVGPU_CTXSW_IOCTL_TRACE_DISABLE \ | ||
2038 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 2) | ||
2039 | #define NVGPU_CTXSW_IOCTL_RING_SETUP \ | ||
2040 | _IOWR(NVGPU_CTXSW_IOCTL_MAGIC, 3, struct nvgpu_ctxsw_ring_setup_args) | ||
2041 | #define NVGPU_CTXSW_IOCTL_SET_FILTER \ | ||
2042 | _IOW(NVGPU_CTXSW_IOCTL_MAGIC, 4, struct nvgpu_ctxsw_trace_filter_args) | ||
2043 | #define NVGPU_CTXSW_IOCTL_GET_FILTER \ | ||
2044 | _IOR(NVGPU_CTXSW_IOCTL_MAGIC, 5, struct nvgpu_ctxsw_trace_filter_args) | ||
2045 | #define NVGPU_CTXSW_IOCTL_POLL \ | ||
2046 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 6) | ||
2047 | |||
2048 | #define NVGPU_CTXSW_IOCTL_LAST \ | ||
2049 | _IOC_NR(NVGPU_CTXSW_IOCTL_POLL) | ||
2050 | |||
2051 | #define NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE \ | ||
2052 | sizeof(struct nvgpu_ctxsw_trace_filter_args) | ||
2053 | |||
2054 | /* | ||
2055 | * /dev/nvhost-sched-gpu device | ||
2056 | * | ||
2057 | * Opening a '/dev/nvhost-sched-gpu' device node creates a way to control | ||
2058 | * GPU scheduling parameters. | ||
2059 | */ | ||
2060 | |||
2061 | #define NVGPU_SCHED_IOCTL_MAGIC 'S' | ||
2062 | |||
2063 | /* | ||
2064 | * When the app manager receives a NVGPU_SCHED_STATUS_TSG_OPEN notification, | ||
2065 | * it is expected to query the list of recently opened TSGs using | ||
2066 | * NVGPU_SCHED_IOCTL_GET_RECENT_TSGS. The kernel driver maintains a bitmap | ||
2067 | * of recently opened TSGs. When the app manager queries the list, it | ||
2068 | * atomically clears the bitmap. This way, at each invocation of | ||
2069 | * NVGPU_SCHED_IOCTL_GET_RECENT_TSGS, app manager only receives the list of | ||
2070 | * TSGs that have been opened since last invocation. | ||
2071 | * | ||
2072 | * If the app manager needs to re-synchronize with the driver, it can use | ||
2073 | * NVGPU_SCHED_IOCTL_GET_TSGS to retrieve the complete list of TSGs. The | ||
2074 | * recent TSG bitmap will be cleared in that case too. | ||
2075 | */ | ||
2076 | struct nvgpu_sched_get_tsgs_args { | ||
2077 | /* in: size of buffer in bytes */ | ||
2078 | /* out: actual size of size of TSG bitmap. if user-provided size is too | ||
2079 | * small, ioctl will return -ENOSPC, and update this field, allowing | ||
2080 | * application to discover required number of bytes and allocate | ||
2081 | * a buffer accordingly. | ||
2082 | */ | ||
2083 | __u32 size; | ||
2084 | |||
2085 | /* in: address of 64-bit aligned buffer */ | ||
2086 | /* out: buffer contains a TSG bitmap. | ||
2087 | * Bit #n will be set in the bitmap if TSG #n is present. | ||
2088 | * When using NVGPU_SCHED_IOCTL_GET_RECENT_TSGS, the first time you use | ||
2089 | * this command, it will return the opened TSGs and subsequent calls | ||
2090 | * will only return the delta (ie. each invocation clears bitmap) | ||
2091 | */ | ||
2092 | __u64 buffer; | ||
2093 | }; | ||
2094 | |||
2095 | struct nvgpu_sched_get_tsgs_by_pid_args { | ||
2096 | /* in: process id for which we want to retrieve TSGs */ | ||
2097 | __u64 pid; | ||
2098 | |||
2099 | /* in: size of buffer in bytes */ | ||
2100 | /* out: actual size of size of TSG bitmap. if user-provided size is too | ||
2101 | * small, ioctl will return -ENOSPC, and update this field, allowing | ||
2102 | * application to discover required number of bytes and allocate | ||
2103 | * a buffer accordingly. | ||
2104 | */ | ||
2105 | __u32 size; | ||
2106 | |||
2107 | /* in: address of 64-bit aligned buffer */ | ||
2108 | /* out: buffer contains a TSG bitmap. */ | ||
2109 | __u64 buffer; | ||
2110 | }; | ||
2111 | |||
2112 | struct nvgpu_sched_tsg_get_params_args { | ||
2113 | __u32 tsgid; /* in: TSG identifier */ | ||
2114 | __u32 timeslice; /* out: timeslice in usecs */ | ||
2115 | __u32 runlist_interleave; | ||
2116 | __u32 graphics_preempt_mode; | ||
2117 | __u32 compute_preempt_mode; | ||
2118 | __u64 pid; /* out: process identifier of TSG owner */ | ||
2119 | }; | ||
2120 | |||
2121 | struct nvgpu_sched_tsg_timeslice_args { | ||
2122 | __u32 tsgid; /* in: TSG identifier */ | ||
2123 | __u32 timeslice; /* in: timeslice in usecs */ | ||
2124 | }; | ||
2125 | |||
2126 | struct nvgpu_sched_tsg_runlist_interleave_args { | ||
2127 | __u32 tsgid; /* in: TSG identifier */ | ||
2128 | |||
2129 | /* in: see NVGPU_RUNLIST_INTERLEAVE_LEVEL_ */ | ||
2130 | __u32 runlist_interleave; | ||
2131 | }; | ||
2132 | |||
2133 | struct nvgpu_sched_api_version_args { | ||
2134 | __u32 version; | ||
2135 | }; | ||
2136 | |||
2137 | struct nvgpu_sched_tsg_refcount_args { | ||
2138 | __u32 tsgid; /* in: TSG identifier */ | ||
2139 | }; | ||
2140 | |||
2141 | #define NVGPU_SCHED_IOCTL_GET_TSGS \ | ||
2142 | _IOWR(NVGPU_SCHED_IOCTL_MAGIC, 1, \ | ||
2143 | struct nvgpu_sched_get_tsgs_args) | ||
2144 | #define NVGPU_SCHED_IOCTL_GET_RECENT_TSGS \ | ||
2145 | _IOWR(NVGPU_SCHED_IOCTL_MAGIC, 2, \ | ||
2146 | struct nvgpu_sched_get_tsgs_args) | ||
2147 | #define NVGPU_SCHED_IOCTL_GET_TSGS_BY_PID \ | ||
2148 | _IOWR(NVGPU_SCHED_IOCTL_MAGIC, 3, \ | ||
2149 | struct nvgpu_sched_get_tsgs_by_pid_args) | ||
2150 | #define NVGPU_SCHED_IOCTL_TSG_GET_PARAMS \ | ||
2151 | _IOWR(NVGPU_SCHED_IOCTL_MAGIC, 4, \ | ||
2152 | struct nvgpu_sched_tsg_get_params_args) | ||
2153 | #define NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE \ | ||
2154 | _IOW(NVGPU_SCHED_IOCTL_MAGIC, 5, \ | ||
2155 | struct nvgpu_sched_tsg_timeslice_args) | ||
2156 | #define NVGPU_SCHED_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \ | ||
2157 | _IOW(NVGPU_SCHED_IOCTL_MAGIC, 6, \ | ||
2158 | struct nvgpu_sched_tsg_runlist_interleave_args) | ||
2159 | #define NVGPU_SCHED_IOCTL_LOCK_CONTROL \ | ||
2160 | _IO(NVGPU_SCHED_IOCTL_MAGIC, 7) | ||
2161 | #define NVGPU_SCHED_IOCTL_UNLOCK_CONTROL \ | ||
2162 | _IO(NVGPU_SCHED_IOCTL_MAGIC, 8) | ||
2163 | #define NVGPU_SCHED_IOCTL_GET_API_VERSION \ | ||
2164 | _IOR(NVGPU_SCHED_IOCTL_MAGIC, 9, \ | ||
2165 | struct nvgpu_sched_api_version_args) | ||
2166 | #define NVGPU_SCHED_IOCTL_GET_TSG \ | ||
2167 | _IOW(NVGPU_SCHED_IOCTL_MAGIC, 10, \ | ||
2168 | struct nvgpu_sched_tsg_refcount_args) | ||
2169 | #define NVGPU_SCHED_IOCTL_PUT_TSG \ | ||
2170 | _IOW(NVGPU_SCHED_IOCTL_MAGIC, 11, \ | ||
2171 | struct nvgpu_sched_tsg_refcount_args) | ||
2172 | #define NVGPU_SCHED_IOCTL_LAST \ | ||
2173 | _IOC_NR(NVGPU_SCHED_IOCTL_PUT_TSG) | ||
2174 | |||
2175 | #define NVGPU_SCHED_IOCTL_MAX_ARG_SIZE \ | ||
2176 | sizeof(struct nvgpu_sched_tsg_get_params_args) | ||
2177 | |||
2178 | |||
2179 | #define NVGPU_SCHED_SET(n, bitmap) \ | ||
2180 | (((__u64 *)(bitmap))[(n) / 64] |= (1ULL << (((__u64)n) & 63))) | ||
2181 | #define NVGPU_SCHED_CLR(n, bitmap) \ | ||
2182 | (((__u64 *)(bitmap))[(n) / 64] &= ~(1ULL << (((__u64)n) & 63))) | ||
2183 | #define NVGPU_SCHED_ISSET(n, bitmap) \ | ||
2184 | (((__u64 *)(bitmap))[(n) / 64] & (1ULL << (((__u64)n) & 63))) | ||
2185 | |||
2186 | #define NVGPU_SCHED_STATUS_TSG_OPEN (1ULL << 0) | ||
2187 | |||
2188 | struct nvgpu_sched_event_arg { | ||
2189 | __u64 reserved; | ||
2190 | __u64 status; | ||
2191 | }; | ||
2192 | |||
2193 | #define NVGPU_SCHED_API_VERSION 1 | ||
2194 | |||
2195 | #endif | ||