diff options
Diffstat (limited to 'include/uapi/linux')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 83 |
1 files changed, 42 insertions, 41 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 2d044db4..49e3fc5c 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -520,8 +520,8 @@ struct nvgpu_gpu_clk_range { | |||
520 | 520 | ||
521 | /* NVGPU_GPU_CLK_DOMAIN_* */ | 521 | /* NVGPU_GPU_CLK_DOMAIN_* */ |
522 | __u32 clk_domain; | 522 | __u32 clk_domain; |
523 | __u32 min_mhz; | 523 | __u64 min_hz; |
524 | __u32 max_mhz; | 524 | __u64 max_hz; |
525 | }; | 525 | }; |
526 | 526 | ||
527 | /* Request on specific clock domains */ | 527 | /* Request on specific clock domains */ |
@@ -551,10 +551,7 @@ struct nvgpu_gpu_clk_range_args { | |||
551 | }; | 551 | }; |
552 | 552 | ||
553 | struct nvgpu_gpu_clk_vf_point { | 553 | struct nvgpu_gpu_clk_vf_point { |
554 | 554 | __u64 freq_hz; | |
555 | /* Flags (not currently used) */ | ||
556 | __u32 flags; | ||
557 | __u32 freq_mhz; | ||
558 | }; | 555 | }; |
559 | 556 | ||
560 | struct nvgpu_gpu_clk_vf_points_args { | 557 | struct nvgpu_gpu_clk_vf_points_args { |
@@ -569,7 +566,7 @@ struct nvgpu_gpu_clk_vf_points_args { | |||
569 | clk_vf_point_entries. If max_entries is zero, | 566 | clk_vf_point_entries. If max_entries is zero, |
570 | NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS will return 0 and max_entries will | 567 | NVGPU_GPU_IOCTL_CLK_GET_VF_POINTS will return 0 and max_entries will |
571 | be set to the max number of VF entries for this clock domain. If | 568 | be set to the max number of VF entries for this clock domain. If |
572 | there are more entries than max_entires, then ioctl will return | 569 | there are more entries than max_entries, then ioctl will return |
573 | -EINVAL. | 570 | -EINVAL. |
574 | */ | 571 | */ |
575 | __u16 max_entries; | 572 | __u16 max_entries; |
@@ -588,24 +585,31 @@ struct nvgpu_gpu_clk_vf_points_args { | |||
588 | __u64 clk_vf_point_entries; | 585 | __u64 clk_vf_point_entries; |
589 | }; | 586 | }; |
590 | 587 | ||
588 | /* Target clock requested by application*/ | ||
589 | #define NVGPU_GPU_CLK_TYPE_TARGET 1 | ||
590 | /* Actual clock frequency for the domain. | ||
591 | May deviate from desired target frequency due to PLL constraints. */ | ||
592 | #define NVGPU_GPU_CLK_TYPE_ACTUAL 2 | ||
593 | /* Effective clock, measured from hardware */ | ||
594 | #define NVGPU_GPU_CLK_TYPE_EFFECTIVE 3 | ||
595 | |||
591 | struct nvgpu_gpu_clk_info { | 596 | struct nvgpu_gpu_clk_info { |
592 | 597 | ||
593 | /* Flags (not currently used) */ | 598 | /* Flags (not currently used) */ |
594 | __u32 flags; | 599 | __u16 flags; |
595 | 600 | ||
596 | /* NVGPU_GPU_CLK_DOMAIN_* */ | 601 | /* in: When NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS set, indicates |
597 | __u32 clk_domain; | 602 | the type of clock info to be returned for this entry. It is |
603 | allowed to have several entries with different clock types in | ||
604 | the same request (for instance query both target and actual | ||
605 | clocks for a given clock domain). This field is ignored for a | ||
606 | SET operation. */ | ||
607 | __u16 clk_type; | ||
598 | 608 | ||
599 | /* target clock frequency for the domain in MHz. Should be | 609 | /* NVGPU_GPU_CLK_DOMAIN_xxx */ |
600 | specified with a non-zero value in NVGPU_GPU_IOCTL_CLK_SET_INFO. | 610 | __u32 clk_domain; |
601 | */ | ||
602 | __u32 target_mhz; | ||
603 | 611 | ||
604 | /* actual clock frequency for the domain in MHz. This value | 612 | __u64 freq_hz; |
605 | may deviate from the desired target frequency due to PLL constraints. | ||
606 | Not used in NVGPU_GPU_IOCTL_CLK_SET_INFO. | ||
607 | */ | ||
608 | __u32 actual_mhz; | ||
609 | }; | 613 | }; |
610 | 614 | ||
611 | struct nvgpu_gpu_clk_get_info_args { | 615 | struct nvgpu_gpu_clk_get_info_args { |
@@ -617,7 +621,11 @@ struct nvgpu_gpu_clk_get_info_args { | |||
617 | */ | 621 | */ |
618 | __u32 flags; | 622 | __u32 flags; |
619 | 623 | ||
620 | __u16 pad0; | 624 | /* in: indicates which type of clock info to be returned (see |
625 | NVGPU_GPU_CLK_TYPE_xxx). If NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS | ||
626 | is defined, clk_type is specified in each clock info entry instead. | ||
627 | */ | ||
628 | __u16 clk_type; | ||
621 | 629 | ||
622 | /* in/out: Number of clock info entries contained in clk_info_entries. | 630 | /* in/out: Number of clock info entries contained in clk_info_entries. |
623 | If zero, NVGPU_GPU_IOCTL_CLK_GET_INFO will return 0 and | 631 | If zero, NVGPU_GPU_IOCTL_CLK_GET_INFO will return 0 and |
@@ -639,12 +647,6 @@ struct nvgpu_gpu_clk_get_info_args { | |||
639 | */ | 647 | */ |
640 | __u64 clk_info_entries; | 648 | __u64 clk_info_entries; |
641 | 649 | ||
642 | __u32 pad1; | ||
643 | |||
644 | /* out: sequence number of last processed request. sequence numbers | ||
645 | are per-user. | ||
646 | */ | ||
647 | __u32 last_req_nr; | ||
648 | }; | 650 | }; |
649 | 651 | ||
650 | struct nvgpu_gpu_clk_set_info_args { | 652 | struct nvgpu_gpu_clk_set_info_args { |
@@ -665,24 +667,21 @@ struct nvgpu_gpu_clk_set_info_args { | |||
665 | */ | 667 | */ |
666 | __u64 clk_info_entries; | 668 | __u64 clk_info_entries; |
667 | 669 | ||
668 | /* out: File descriptor for completions and event notifications. | 670 | /* out: File descriptor for request completion. Application can poll |
669 | If application does not close this fd after completion, then the | 671 | this file descriptor to determine when the request has completed. |
670 | same fd will be returned for subsequent request (recommended). | 672 | The fd must be closed afterwards. |
671 | */ | 673 | */ |
672 | int fd; | 674 | int completion_fd; |
673 | |||
674 | /* out: sequence number for this request. In order to determine that | ||
675 | a request has completed, an application should check this sequence | ||
676 | number against last_req_nr from NVGPU_GPU_IOCTL_CLK_GET_INFO, using | ||
677 | nvgpu_clk_req_complete(req_nr, last_req_nr); | ||
678 | */ | ||
679 | __u32 req_nr; | ||
680 | }; | 675 | }; |
681 | 676 | ||
682 | static inline int nvgpu_clk_req_complete(__u32 req_nr, __u32 last_req_nr) | 677 | struct nvgpu_gpu_clk_get_event_fd_args { |
683 | { | 678 | |
684 | return ((long)(last_req_nr - req_nr) >= 0); | 679 | /* in: Flags (not currently used). */ |
685 | } | 680 | __u32 flags; |
681 | |||
682 | /* out: File descriptor for events, i.e. any clock update. */ | ||
683 | int event_fd; | ||
684 | }; | ||
686 | 685 | ||
687 | struct nvgpu_gpu_get_memory_state_args { | 686 | struct nvgpu_gpu_get_memory_state_args { |
688 | /* | 687 | /* |
@@ -778,6 +777,8 @@ struct nvgpu_gpu_get_fbp_l2_masks_args { | |||
778 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 30, struct nvgpu_gpu_clk_get_info_args) | 777 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 30, struct nvgpu_gpu_clk_get_info_args) |
779 | #define NVGPU_GPU_IOCTL_CLK_SET_INFO \ | 778 | #define NVGPU_GPU_IOCTL_CLK_SET_INFO \ |
780 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 31, struct nvgpu_gpu_clk_set_info_args) | 779 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 31, struct nvgpu_gpu_clk_set_info_args) |
780 | #define NVGPU_GPU_IOCTL_CLK_GET_EVENT_FD \ | ||
781 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 32, struct nvgpu_gpu_clk_get_event_fd_args) | ||
781 | #define NVGPU_GPU_IOCTL_GET_MEMORY_STATE \ | 782 | #define NVGPU_GPU_IOCTL_GET_MEMORY_STATE \ |
782 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 33, \ | 783 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 33, \ |
783 | struct nvgpu_gpu_get_memory_state_args) | 784 | struct nvgpu_gpu_get_memory_state_args) |