diff options
Diffstat (limited to 'include/uapi/linux/nvgpu.h')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 154 |
1 files changed, 150 insertions, 4 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 442a84ac..64ac45b5 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -351,6 +351,28 @@ struct nvgpu_gpu_get_buffer_info_args { | |||
351 | }; | 351 | }; |
352 | }; | 352 | }; |
353 | 353 | ||
354 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT 16 | ||
355 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TSC 1 | ||
356 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_JIFFIES 2 | ||
357 | #define NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TIMEOFDAY 3 | ||
358 | |||
359 | struct nvgpu_gpu_get_cpu_time_correlation_sample { | ||
360 | /* gpu timestamp value */ | ||
361 | __u64 cpu_timestamp; | ||
362 | /* raw GPU counter (PTIMER) value */ | ||
363 | __u64 gpu_timestamp; | ||
364 | }; | ||
365 | |||
366 | struct nvgpu_gpu_get_cpu_time_correlation_info_args { | ||
367 | /* timestamp pairs */ | ||
368 | struct nvgpu_gpu_get_cpu_time_correlation_sample samples[ | ||
369 | NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_MAX_COUNT]; | ||
370 | /* number of pairs to read */ | ||
371 | __u32 count; | ||
372 | /* cpu clock source id */ | ||
373 | __u32 source_id; | ||
374 | }; | ||
375 | |||
354 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 376 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
355 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 377 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
356 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 378 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -397,11 +419,13 @@ struct nvgpu_gpu_get_buffer_info_args { | |||
397 | _IO(NVGPU_GPU_IOCTL_MAGIC, 22) | 419 | _IO(NVGPU_GPU_IOCTL_MAGIC, 22) |
398 | #define NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS \ | 420 | #define NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS \ |
399 | _IO(NVGPU_GPU_IOCTL_MAGIC, 23) | 421 | _IO(NVGPU_GPU_IOCTL_MAGIC, 23) |
400 | 422 | #define NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO \ | |
423 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 24, \ | ||
424 | struct nvgpu_gpu_get_cpu_time_correlation_info_args) | ||
401 | #define NVGPU_GPU_IOCTL_LAST \ | 425 | #define NVGPU_GPU_IOCTL_LAST \ |
402 | _IOC_NR(NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS) | 426 | _IOC_NR(NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO) |
403 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 427 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
404 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) | 428 | sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args) |
405 | 429 | ||
406 | /* | 430 | /* |
407 | * /dev/nvhost-tsg-gpu device | 431 | * /dev/nvhost-tsg-gpu device |
@@ -834,6 +858,34 @@ struct nvgpu_channel_wdt_args { | |||
834 | #define NVGPU_IOCTL_CHANNEL_DISABLE_WDT 1 | 858 | #define NVGPU_IOCTL_CHANNEL_DISABLE_WDT 1 |
835 | #define NVGPU_IOCTL_CHANNEL_ENABLE_WDT 2 | 859 | #define NVGPU_IOCTL_CHANNEL_ENABLE_WDT 2 |
836 | 860 | ||
861 | /* | ||
862 | * Interleaving channels in a runlist is an approach to improve | ||
863 | * GPU scheduling by allowing certain channels to appear multiple | ||
864 | * times on the runlist. The number of times a channel appears is | ||
865 | * governed by the following levels: | ||
866 | * | ||
867 | * low (L) : appears once | ||
868 | * medium (M): if L, appears L times | ||
869 | * else, appears once | ||
870 | * high (H) : if L, appears (M + 1) x L times | ||
871 | * else if M, appears M times | ||
872 | * else, appears once | ||
873 | */ | ||
874 | struct nvgpu_runlist_interleave_args { | ||
875 | __u32 level; | ||
876 | __u32 reserved; | ||
877 | }; | ||
878 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW 0 | ||
879 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM 1 | ||
880 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH 2 | ||
881 | #define NVGPU_RUNLIST_INTERLEAVE_NUM_LEVELS 3 | ||
882 | |||
883 | /* controls how long a channel occupies an engine uninterrupted */ | ||
884 | struct nvgpu_timeslice_args { | ||
885 | __u32 timeslice_us; | ||
886 | __u32 reserved; | ||
887 | }; | ||
888 | |||
837 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ | 889 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ |
838 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) | 890 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) |
839 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ | 891 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ |
@@ -876,9 +928,13 @@ struct nvgpu_channel_wdt_args { | |||
876 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) | 928 | _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args) |
877 | #define NVGPU_IOCTL_CHANNEL_WDT \ | 929 | #define NVGPU_IOCTL_CHANNEL_WDT \ |
878 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) | 930 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) |
931 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ | ||
932 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) | ||
933 | #define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ | ||
934 | _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) | ||
879 | 935 | ||
880 | #define NVGPU_IOCTL_CHANNEL_LAST \ | 936 | #define NVGPU_IOCTL_CHANNEL_LAST \ |
881 | _IOC_NR(NVGPU_IOCTL_CHANNEL_WDT) | 937 | _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_TIMESLICE) |
882 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) | 938 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) |
883 | 939 | ||
884 | /* | 940 | /* |
@@ -1159,4 +1215,94 @@ struct nvgpu_as_map_buffer_batch_args { | |||
1159 | #define NVGPU_AS_IOCTL_MAX_ARG_SIZE \ | 1215 | #define NVGPU_AS_IOCTL_MAX_ARG_SIZE \ |
1160 | sizeof(struct nvgpu_as_map_buffer_ex_args) | 1216 | sizeof(struct nvgpu_as_map_buffer_ex_args) |
1161 | 1217 | ||
1218 | |||
1219 | /* | ||
1220 | * /dev/nvhost-ctxsw-gpu device | ||
1221 | * | ||
1222 | * Opening a '/dev/nvhost-ctxsw-gpu' device node creates a way to trace | ||
1223 | * context switches on GR engine | ||
1224 | */ | ||
1225 | |||
1226 | #define NVGPU_CTXSW_IOCTL_MAGIC 'C' | ||
1227 | |||
1228 | #define NVGPU_CTXSW_TAG_SOF 0x00 | ||
1229 | #define NVGPU_CTXSW_TAG_CTXSW_REQ_BY_HOST 0x01 | ||
1230 | #define NVGPU_CTXSW_TAG_FE_ACK 0x02 | ||
1231 | #define NVGPU_CTXSW_TAG_FE_ACK_WFI 0x0a | ||
1232 | #define NVGPU_CTXSW_TAG_FE_ACK_GFXP 0x0b | ||
1233 | #define NVGPU_CTXSW_TAG_FE_ACK_CTAP 0x0c | ||
1234 | #define NVGPU_CTXSW_TAG_FE_ACK_CILP 0x0d | ||
1235 | #define NVGPU_CTXSW_TAG_SAVE_END 0x03 | ||
1236 | #define NVGPU_CTXSW_TAG_RESTORE_START 0x04 | ||
1237 | #define NVGPU_CTXSW_TAG_CONTEXT_START 0x05 | ||
1238 | #define NVGPU_CTXSW_TAG_INVALID_TIMESTAMP 0xff | ||
1239 | #define NVGPU_CTXSW_TAG_LAST \ | ||
1240 | NVGPU_CTXSW_TAG_INVALID_TIMESTAMP | ||
1241 | |||
1242 | struct nvgpu_ctxsw_trace_entry { | ||
1243 | __u8 tag; | ||
1244 | __u8 vmid; | ||
1245 | __u16 seqno; /* sequence number to detect drops */ | ||
1246 | __u32 context_id; /* context_id as allocated by FECS */ | ||
1247 | __u64 pid; /* 64-bit is max bits of different OS pid */ | ||
1248 | __u64 timestamp; /* 64-bit time */ | ||
1249 | }; | ||
1250 | |||
1251 | #define NVGPU_CTXSW_RING_HEADER_MAGIC 0x7000fade | ||
1252 | #define NVGPU_CTXSW_RING_HEADER_VERSION 0 | ||
1253 | |||
1254 | struct nvgpu_ctxsw_ring_header { | ||
1255 | __u32 magic; | ||
1256 | __u32 version; | ||
1257 | __u32 num_ents; | ||
1258 | __u32 ent_size; | ||
1259 | volatile __u32 drop_count; /* excluding filtered out events */ | ||
1260 | volatile __u32 write_seqno; | ||
1261 | volatile __u32 write_idx; | ||
1262 | volatile __u32 read_idx; | ||
1263 | }; | ||
1264 | |||
1265 | struct nvgpu_ctxsw_ring_setup_args { | ||
1266 | __u32 size; /* [in/out] size of ring buffer in bytes (including | ||
1267 | header). will be rounded page size. this parameter | ||
1268 | is updated with actual allocated size. */ | ||
1269 | }; | ||
1270 | |||
1271 | #define NVGPU_CTXSW_FILTER_SIZE (NVGPU_CTXSW_TAG_LAST + 1) | ||
1272 | #define NVGPU_CTXSW_FILTER_SET(n, p) \ | ||
1273 | ((p)->tag_bits[(n) / 64] |= (1 << ((n) & 63))) | ||
1274 | #define NVGPU_CTXSW_FILTER_CLR(n, p) \ | ||
1275 | ((p)->tag_bits[(n) / 64] &= ~(1 << ((n) & 63))) | ||
1276 | #define NVGPU_CTXSW_FILTER_ISSET(n, p) \ | ||
1277 | ((p)->tag_bits[(n) / 64] & (1 << ((n) & 63))) | ||
1278 | #define NVGPU_CTXSW_FILTER_CLR_ALL(p) memset((void *)(p), 0, sizeof(*(p))) | ||
1279 | #define NVGPU_CTXSW_FILTER_SET_ALL(p) memset((void *)(p), ~0, sizeof(*(p))) | ||
1280 | |||
1281 | struct nvgpu_ctxsw_trace_filter { | ||
1282 | __u64 tag_bits[(NVGPU_CTXSW_FILTER_SIZE + 63) / 64]; | ||
1283 | }; | ||
1284 | |||
1285 | struct nvgpu_ctxsw_trace_filter_args { | ||
1286 | struct nvgpu_ctxsw_trace_filter filter; | ||
1287 | }; | ||
1288 | |||
1289 | #define NVGPU_CTXSW_IOCTL_TRACE_ENABLE \ | ||
1290 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 1) | ||
1291 | #define NVGPU_CTXSW_IOCTL_TRACE_DISABLE \ | ||
1292 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 2) | ||
1293 | #define NVGPU_CTXSW_IOCTL_RING_SETUP \ | ||
1294 | _IOWR(NVGPU_CTXSW_IOCTL_MAGIC, 3, struct nvgpu_ctxsw_ring_setup_args) | ||
1295 | #define NVGPU_CTXSW_IOCTL_SET_FILTER \ | ||
1296 | _IOW(NVGPU_CTXSW_IOCTL_MAGIC, 4, struct nvgpu_ctxsw_trace_filter_args) | ||
1297 | #define NVGPU_CTXSW_IOCTL_GET_FILTER \ | ||
1298 | _IOR(NVGPU_CTXSW_IOCTL_MAGIC, 5, struct nvgpu_ctxsw_trace_filter_args) | ||
1299 | #define NVGPU_CTXSW_IOCTL_POLL \ | ||
1300 | _IO(NVGPU_CTXSW_IOCTL_MAGIC, 6) | ||
1301 | |||
1302 | #define NVGPU_CTXSW_IOCTL_LAST \ | ||
1303 | _IOC_NR(NVGPU_CTXSW_IOCTL_POLL) | ||
1304 | |||
1305 | #define NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE \ | ||
1306 | sizeof(struct nvgpu_ctxsw_trace_filter_args) | ||
1307 | |||
1162 | #endif | 1308 | #endif |