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1 files changed, 74 insertions, 0 deletions
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1/*
2 * NVGPU Public Interface Header
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16/* This file is meant to extend nvgpu.h, not replace it
17 * as such, be sure that nvgpu.h is actually the file performing the
18 * inclusion, to the extent that's possible.
19 */
20#ifndef _UAPI__LINUX_NVGPU_IOCTL_H
21# error "This file is to be included within nvgpu.h only."
22#endif
23
24#ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
25#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
26
27#define NVGPU_GPU_ARCH_GP100 0x00000130
28#define NVGPU_GPU_IMPL_GP104 0x00000004
29#define NVGPU_GPU_IMPL_GP106 0x00000006
30#define NVGPU_GPU_IMPL_GP10B 0x0000000B
31
32/*
33 * this flag is used in struct nvgpu_as_map_buffer_ex_args
34 * to specify IO coherence
35 */
36#define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT (1 << 4)
37
38/*
39 * this flag is used in struct nvgpu_alloc_gpfifo_args
40 * to enable re-playable faults for that channel
41 */
42#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2)
43
44/* Flags in nvgpu_alloc_obj_ctx_args.flags */
45#define NVGPU_ALLOC_OBJ_FLAGS_GFXP (1 << 1)
46#define NVGPU_ALLOC_OBJ_FLAGS_CILP (1 << 2)
47
48/* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */
49#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP (1 << 1)
50/* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */
51#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP (1 << 2)
52
53/* SM LRF ECC is enabled */
54#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
55/* SM SHM ECC is enabled */
56#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM (1ULL << 61)
57/* TEX ECC is enabled */
58#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX (1ULL << 62)
59/* L2 ECC is enabled */
60#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC (1ULL << 63)
61/* All types of ECC are enabled */
62#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
63 (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF | \
64 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM | \
65 NVGPU_GPU_FLAGS_ECC_ENABLED_TEX | \
66 NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
67
68/* Channel event_id in nvgpu_channel_events_ctrl_ext_args */
69#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED 3
70#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE 4
71
72#endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */
73
74