diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/tegra_vgpu.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 6fc298e0..7587d355 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -19,6 +19,10 @@ | |||
19 | #ifndef __TEGRA_VGPU_H | 19 | #ifndef __TEGRA_VGPU_H |
20 | #define __TEGRA_VGPU_H | 20 | #define __TEGRA_VGPU_H |
21 | 21 | ||
22 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
23 | #include <linux/tegra_vgpu_t18x.h> | ||
24 | #endif | ||
25 | |||
22 | enum { | 26 | enum { |
23 | TEGRA_VGPU_MODULE_GPU = 0, | 27 | TEGRA_VGPU_MODULE_GPU = 0, |
24 | }; | 28 | }; |
@@ -65,7 +69,8 @@ enum { | |||
65 | TEGRA_VGPU_CMD_GET_ZCULL_INFO, | 69 | TEGRA_VGPU_CMD_GET_ZCULL_INFO, |
66 | TEGRA_VGPU_CMD_ZBC_SET_TABLE, | 70 | TEGRA_VGPU_CMD_ZBC_SET_TABLE, |
67 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, | 71 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, |
68 | TEGRA_VGPU_CMD_AS_MAP_EX | 72 | TEGRA_VGPU_CMD_AS_MAP_EX, |
73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS | ||
69 | }; | 74 | }; |
70 | 75 | ||
71 | struct tegra_vgpu_connect_params { | 76 | struct tegra_vgpu_connect_params { |
@@ -245,6 +250,15 @@ struct tegra_vgpu_zbc_query_table_params { | |||
245 | u32 index_size; /* [out] size, [in] index */ | 250 | u32 index_size; /* [out] size, [in] index */ |
246 | }; | 251 | }; |
247 | 252 | ||
253 | #define TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX 4 | ||
254 | |||
255 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { | ||
256 | u64 handle; | ||
257 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; | ||
258 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; | ||
259 | u32 mode; | ||
260 | }; | ||
261 | |||
248 | struct tegra_vgpu_cmd_msg { | 262 | struct tegra_vgpu_cmd_msg { |
249 | u32 cmd; | 263 | u32 cmd; |
250 | int ret; | 264 | int ret; |
@@ -268,6 +282,8 @@ struct tegra_vgpu_cmd_msg { | |||
268 | struct tegra_vgpu_zcull_info_params zcull_info; | 282 | struct tegra_vgpu_zcull_info_params zcull_info; |
269 | struct tegra_vgpu_zbc_set_table_params zbc_set_table; | 283 | struct tegra_vgpu_zbc_set_table_params zbc_set_table; |
270 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; | 284 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; |
285 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | ||
286 | char padding[192]; | ||
271 | } params; | 287 | } params; |
272 | }; | 288 | }; |
273 | 289 | ||
@@ -335,6 +351,7 @@ struct tegra_vgpu_intr_msg { | |||
335 | struct tegra_vgpu_fifo_intr_info fifo_intr; | 351 | struct tegra_vgpu_fifo_intr_info fifo_intr; |
336 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; | 352 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; |
337 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | 353 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; |
354 | char padding[32]; | ||
338 | } info; | 355 | } info; |
339 | }; | 356 | }; |
340 | 357 | ||