diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/tegra_vgpu.h | 208 |
1 files changed, 104 insertions, 104 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index fc701eb3..196b08ca 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -37,65 +37,65 @@ enum { | |||
37 | 37 | ||
38 | enum { | 38 | enum { |
39 | TEGRA_VGPU_CMD_CONNECT = 0, | 39 | TEGRA_VGPU_CMD_CONNECT = 0, |
40 | TEGRA_VGPU_CMD_DISCONNECT, | 40 | TEGRA_VGPU_CMD_DISCONNECT = 1, |
41 | TEGRA_VGPU_CMD_ABORT, | 41 | TEGRA_VGPU_CMD_ABORT = 2, |
42 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX, | 42 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3, |
43 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX, | 43 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4, |
44 | TEGRA_VGPU_CMD_GET_ATTRIBUTE, | 44 | TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5, |
45 | TEGRA_VGPU_CMD_MAP_BAR1, | 45 | TEGRA_VGPU_CMD_MAP_BAR1 = 6, |
46 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE, | 46 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, |
47 | TEGRA_VGPU_CMD_AS_BIND_SHARE, | 47 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, |
48 | TEGRA_VGPU_CMD_AS_FREE_SHARE, | 48 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, |
49 | TEGRA_VGPU_CMD_AS_MAP, | 49 | TEGRA_VGPU_CMD_AS_MAP = 10, |
50 | TEGRA_VGPU_CMD_AS_UNMAP, | 50 | TEGRA_VGPU_CMD_AS_UNMAP = 11, |
51 | TEGRA_VGPU_CMD_AS_INVALIDATE, | 51 | TEGRA_VGPU_CMD_AS_INVALIDATE = 12, |
52 | TEGRA_VGPU_CMD_CHANNEL_BIND, | 52 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, |
53 | TEGRA_VGPU_CMD_CHANNEL_UNBIND, | 53 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, |
54 | TEGRA_VGPU_CMD_CHANNEL_DISABLE, | 54 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, |
55 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT, | 55 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16, |
56 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC, | 56 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17, |
57 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX, /* deprecated */ | 57 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX = 18, /* deprecated */ |
58 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX, /* deprecated */ | 58 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX = 19, /* deprecated */ |
59 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX, | 59 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20, |
60 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX, | 60 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21, |
61 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX, | 61 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22, |
62 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX, | 62 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23, |
63 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX, | 63 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24, |
64 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX, | 64 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25, |
65 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX, | 65 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26, |
66 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL, | 66 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27, |
67 | TEGRA_VGPU_CMD_CACHE_MAINT, | 67 | TEGRA_VGPU_CMD_CACHE_MAINT = 28, |
68 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST, | 68 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29, |
69 | TEGRA_VGPU_CMD_GET_ZCULL_INFO, | 69 | TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30, |
70 | TEGRA_VGPU_CMD_ZBC_SET_TABLE, | 70 | TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31, |
71 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, | 71 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32, |
72 | TEGRA_VGPU_CMD_AS_MAP_EX, | 72 | TEGRA_VGPU_CMD_AS_MAP_EX = 33, |
73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, | 73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34, |
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36, |
76 | TEGRA_VGPU_CMD_REG_OPS, | 76 | TEGRA_VGPU_CMD_REG_OPS = 37, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, | 78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39, |
79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE, | 79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40, |
80 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE, | 80 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41, |
81 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE, | 81 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42, |
82 | TEGRA_VGPU_CMD_FECS_TRACE_POLL, | 82 | TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43, |
83 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER, | 83 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44, |
84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, | 84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45, |
85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, | 85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46, |
86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, | 86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47, |
87 | TEGRA_VGPU_CMD_GR_CTX_ALLOC, | 87 | TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48, |
88 | TEGRA_VGPU_CMD_GR_CTX_FREE, | 88 | TEGRA_VGPU_CMD_GR_CTX_FREE = 49, |
89 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX, | 89 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX =50, |
90 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX, | 90 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51, |
91 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL, | 91 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52, |
92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, | 92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53, |
93 | TEGRA_VGPU_CMD_TSG_PREEMPT, | 93 | TEGRA_VGPU_CMD_TSG_PREEMPT = 54, |
94 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE, | 94 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55, |
95 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE, | 95 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56, |
96 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET, | 96 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, |
97 | TEGRA_VGPU_CMD_CHANNEL_ENABLE, | 97 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, |
98 | TEGRA_VGPU_CMD_READ_PTIMER, | 98 | TEGRA_VGPU_CMD_READ_PTIMER = 59, |
99 | }; | 99 | }; |
100 | 100 | ||
101 | struct tegra_vgpu_connect_params { | 101 | struct tegra_vgpu_connect_params { |
@@ -111,27 +111,27 @@ struct tegra_vgpu_channel_hwctx_params { | |||
111 | 111 | ||
112 | enum { | 112 | enum { |
113 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, | 113 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, |
114 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE, | 114 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, |
115 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE, | 115 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, |
116 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES, | 116 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, |
117 | TEGRA_VGPU_ATTRIB_GPC_COUNT, | 117 | TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, |
118 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT, | 118 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, |
119 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT, | 119 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, |
120 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0, | 120 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, |
121 | TEGRA_VGPU_ATTRIB_L2_SIZE, | 121 | TEGRA_VGPU_ATTRIB_L2_SIZE = 8, |
122 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, | 122 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, |
123 | TEGRA_VGPU_ATTRIB_NUM_FBPS, | 123 | TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, |
124 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK, | 124 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, |
125 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, | 125 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, |
126 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, | 126 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, |
127 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, | 127 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, |
128 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE, | 128 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, |
129 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE, | 129 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, |
130 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC, | 130 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, |
131 | TEGRA_VGPU_ATTRIB_LTC_COUNT, | 131 | TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, |
132 | TEGRA_VGPU_ATTRIB_TPC_COUNT, | 132 | TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, |
133 | TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT, | 133 | TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, |
134 | TEGRA_VGPU_ATTRIB_MAX_FREQ, | 134 | TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, |
135 | }; | 135 | }; |
136 | 136 | ||
137 | struct tegra_vgpu_attrib_params { | 137 | struct tegra_vgpu_attrib_params { |
@@ -441,22 +441,22 @@ struct tegra_vgpu_cmd_msg { | |||
441 | 441 | ||
442 | enum { | 442 | enum { |
443 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, | 443 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, |
444 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT, | 444 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1, |
445 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY, | 445 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2, |
446 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD, | 446 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3, |
447 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS, | 447 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4, |
448 | TEGRA_VGPU_GR_INTR_FECS_ERROR, | 448 | TEGRA_VGPU_GR_INTR_FECS_ERROR = 5, |
449 | TEGRA_VGPU_GR_INTR_CLASS_ERROR, | 449 | TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6, |
450 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD, | 450 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7, |
451 | TEGRA_VGPU_GR_INTR_EXCEPTION, | 451 | TEGRA_VGPU_GR_INTR_EXCEPTION = 8, |
452 | TEGRA_VGPU_GR_INTR_SEMAPHORE, | 452 | TEGRA_VGPU_GR_INTR_SEMAPHORE = 9, |
453 | TEGRA_VGPU_FIFO_INTR_PBDMA, | 453 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, |
454 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT, | 454 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, |
455 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT, | 455 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, |
456 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE, | 456 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13, |
457 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL, | 457 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14, |
458 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE, | 458 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15, |
459 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION | 459 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, |
460 | }; | 460 | }; |
461 | 461 | ||
462 | struct tegra_vgpu_gr_intr_info { | 462 | struct tegra_vgpu_gr_intr_info { |
@@ -498,18 +498,18 @@ struct tegra_vgpu_general_event_info { | |||
498 | enum { | 498 | enum { |
499 | 499 | ||
500 | TEGRA_VGPU_INTR_GR = 0, | 500 | TEGRA_VGPU_INTR_GR = 0, |
501 | TEGRA_VGPU_INTR_FIFO, | 501 | TEGRA_VGPU_INTR_FIFO = 1, |
502 | TEGRA_VGPU_INTR_CE2, | 502 | TEGRA_VGPU_INTR_CE2 = 2, |
503 | TEGRA_VGPU_NONSTALL_INTR_GR, | 503 | TEGRA_VGPU_NONSTALL_INTR_GR = 3, |
504 | TEGRA_VGPU_NONSTALL_INTR_FIFO, | 504 | TEGRA_VGPU_NONSTALL_INTR_FIFO = 4, |
505 | TEGRA_VGPU_NONSTALL_INTR_CE2 | 505 | TEGRA_VGPU_NONSTALL_INTR_CE2 = 5, |
506 | }; | 506 | }; |
507 | 507 | ||
508 | enum { | 508 | enum { |
509 | TEGRA_VGPU_EVENT_INTR = 0, | 509 | TEGRA_VGPU_EVENT_INTR = 0, |
510 | TEGRA_VGPU_EVENT_ABORT, | 510 | TEGRA_VGPU_EVENT_ABORT = 1, |
511 | TEGRA_VGPU_EVENT_FECS_TRACE, | 511 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, |
512 | TEGRA_VGPU_EVENT_CHANNEL, | 512 | TEGRA_VGPU_EVENT_CHANNEL = 3, |
513 | }; | 513 | }; |
514 | 514 | ||
515 | struct tegra_vgpu_intr_msg { | 515 | struct tegra_vgpu_intr_msg { |