diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/tegra_vgpu.h | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index d517fabc..1d195efd 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -54,8 +54,8 @@ enum { | |||
54 | TEGRA_VGPU_CMD_CHANNEL_DISABLE, | 54 | TEGRA_VGPU_CMD_CHANNEL_DISABLE, |
55 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT, | 55 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT, |
56 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC, | 56 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC, |
57 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX, | 57 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX, /* deprecated */ |
58 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX, | 58 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX, /* deprecated */ |
59 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX, | 59 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX, |
60 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX, | 60 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX, |
61 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX, | 61 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX, |
@@ -84,6 +84,10 @@ enum { | |||
84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, | 84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, |
85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, | 85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, |
86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, | 86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, |
87 | TEGRA_VGPU_CMD_GR_CTX_ALLOC, | ||
88 | TEGRA_VGPU_CMD_GR_CTX_FREE, | ||
89 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX, | ||
90 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX, | ||
87 | }; | 91 | }; |
88 | 92 | ||
89 | struct tegra_vgpu_connect_params { | 93 | struct tegra_vgpu_connect_params { |
@@ -192,7 +196,7 @@ struct tegra_vgpu_ramfc_params { | |||
192 | u8 iova; | 196 | u8 iova; |
193 | }; | 197 | }; |
194 | 198 | ||
195 | struct tegra_vgpu_gr_ctx_params { | 199 | struct tegra_vgpu_ch_ctx_params { |
196 | u64 handle; | 200 | u64 handle; |
197 | u64 gr_ctx_va; | 201 | u64 gr_ctx_va; |
198 | u64 patch_ctx_va; | 202 | u64 patch_ctx_va; |
@@ -268,10 +272,11 @@ struct tegra_vgpu_zbc_query_table_params { | |||
268 | #define TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX 4 | 272 | #define TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX 4 |
269 | 273 | ||
270 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { | 274 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { |
271 | u64 handle; | 275 | u64 handle; /* deprecated */ |
272 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; | 276 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; |
273 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; | 277 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX]; |
274 | u32 mode; | 278 | u32 mode; |
279 | u64 gr_ctx_handle; | ||
275 | }; | 280 | }; |
276 | 281 | ||
277 | struct tegra_vgpu_mmu_debug_mode { | 282 | struct tegra_vgpu_mmu_debug_mode { |
@@ -339,6 +344,23 @@ struct tegra_vgpu_channel_free_hwpm_ctx { | |||
339 | u64 handle; | 344 | u64 handle; |
340 | }; | 345 | }; |
341 | 346 | ||
347 | struct tegra_vgpu_gr_ctx_params { | ||
348 | u64 gr_ctx_handle; | ||
349 | u64 as_handle; | ||
350 | u64 gr_ctx_va; | ||
351 | u32 class_num; | ||
352 | }; | ||
353 | |||
354 | struct tegra_vgpu_channel_bind_gr_ctx_params { | ||
355 | u64 ch_handle; | ||
356 | u64 gr_ctx_handle; | ||
357 | }; | ||
358 | |||
359 | struct tegra_vgpu_tsg_bind_gr_ctx_params { | ||
360 | u32 tsg_id; | ||
361 | u64 gr_ctx_handle; | ||
362 | }; | ||
363 | |||
342 | struct tegra_vgpu_cmd_msg { | 364 | struct tegra_vgpu_cmd_msg { |
343 | u32 cmd; | 365 | u32 cmd; |
344 | int ret; | 366 | int ret; |
@@ -354,7 +376,7 @@ struct tegra_vgpu_cmd_msg { | |||
354 | struct tegra_vgpu_as_invalidate_params as_invalidate; | 376 | struct tegra_vgpu_as_invalidate_params as_invalidate; |
355 | struct tegra_vgpu_channel_config_params channel_config; | 377 | struct tegra_vgpu_channel_config_params channel_config; |
356 | struct tegra_vgpu_ramfc_params ramfc; | 378 | struct tegra_vgpu_ramfc_params ramfc; |
357 | struct tegra_vgpu_gr_ctx_params gr_ctx; | 379 | struct tegra_vgpu_ch_ctx_params ch_ctx; |
358 | struct tegra_vgpu_zcull_bind_params zcull_bind; | 380 | struct tegra_vgpu_zcull_bind_params zcull_bind; |
359 | struct tegra_vgpu_cache_maint_params cache_maint; | 381 | struct tegra_vgpu_cache_maint_params cache_maint; |
360 | struct tegra_vgpu_runlist_params runlist; | 382 | struct tegra_vgpu_runlist_params runlist; |
@@ -372,6 +394,9 @@ struct tegra_vgpu_cmd_msg { | |||
372 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; | 394 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; |
373 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | 395 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; |
374 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | 396 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; |
397 | struct tegra_vgpu_gr_ctx_params gr_ctx; | ||
398 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | ||
399 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | ||
375 | char padding[192]; | 400 | char padding[192]; |
376 | } params; | 401 | } params; |
377 | }; | 402 | }; |