diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/tegra_vgpu.h | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index e0a7ff66..61ffff70 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GPU Virtualization Interfaces to Server | 2 | * Tegra GPU Virtualization Interfaces to Server |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -210,7 +210,18 @@ struct tegra_vgpu_cmd_msg { | |||
210 | }; | 210 | }; |
211 | 211 | ||
212 | enum { | 212 | enum { |
213 | TEGRA_VGPU_GR_INTR_NOTIFY = 0 | 213 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, |
214 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT, | ||
215 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY, | ||
216 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD, | ||
217 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS, | ||
218 | TEGRA_VGPU_GR_INTR_FECS_ERROR, | ||
219 | TEGRA_VGPU_GR_INTR_CLASS_ERROR, | ||
220 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD, | ||
221 | TEGRA_VGPU_GR_INTR_EXCEPTION, | ||
222 | TEGRA_VGPU_FIFO_INTR_PBDMA, | ||
223 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT, | ||
224 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT | ||
214 | }; | 225 | }; |
215 | 226 | ||
216 | struct tegra_vgpu_gr_intr_info { | 227 | struct tegra_vgpu_gr_intr_info { |
@@ -218,8 +229,14 @@ struct tegra_vgpu_gr_intr_info { | |||
218 | u32 chid; | 229 | u32 chid; |
219 | }; | 230 | }; |
220 | 231 | ||
232 | struct tegra_vgpu_fifo_intr_info { | ||
233 | u32 type; | ||
234 | u32 chid; | ||
235 | }; | ||
236 | |||
221 | enum { | 237 | enum { |
222 | TEGRA_VGPU_INTR_GR = 0 | 238 | TEGRA_VGPU_INTR_GR = 0, |
239 | TEGRA_VGPU_INTR_FIFO | ||
223 | }; | 240 | }; |
224 | 241 | ||
225 | enum { | 242 | enum { |
@@ -232,6 +249,7 @@ struct tegra_vgpu_intr_msg { | |||
232 | u32 unit; | 249 | u32 unit; |
233 | union { | 250 | union { |
234 | struct tegra_vgpu_gr_intr_info gr_intr; | 251 | struct tegra_vgpu_gr_intr_info gr_intr; |
252 | struct tegra_vgpu_fifo_intr_info fifo_intr; | ||
235 | } info; | 253 | } info; |
236 | }; | 254 | }; |
237 | 255 | ||