diff options
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/tegra_vgpu.h | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 979d454e..67bd0d76 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -77,10 +77,10 @@ enum { | |||
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, | 78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, |
79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE, | 79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE, |
80 | RESVD1, | 80 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE, |
81 | RESVD2, | 81 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE, |
82 | RESVD3, | 82 | TEGRA_VGPU_CMD_FECS_TRACE_POLL, |
83 | RESVD4, | 83 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER, |
84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, | 84 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE, |
85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, | 85 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE, |
86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, | 86 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX, |
@@ -319,6 +319,11 @@ struct tegra_vgpu_channel_timeslice_params { | |||
319 | u32 timeslice_us; | 319 | u32 timeslice_us; |
320 | }; | 320 | }; |
321 | 321 | ||
322 | #define TEGRA_VGPU_FECS_TRACE_FILTER_SIZE 256 | ||
323 | struct tegra_vgpu_fecs_trace_filter { | ||
324 | u64 tag_bits[(TEGRA_VGPU_FECS_TRACE_FILTER_SIZE + 63) / 64]; | ||
325 | }; | ||
326 | |||
322 | enum { | 327 | enum { |
323 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, | 328 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, |
324 | TEGRA_VGPU_CTXSW_MODE_CTXSW, | 329 | TEGRA_VGPU_CTXSW_MODE_CTXSW, |
@@ -363,6 +368,7 @@ struct tegra_vgpu_cmd_msg { | |||
363 | struct tegra_vgpu_channel_priority_params channel_priority; | 368 | struct tegra_vgpu_channel_priority_params channel_priority; |
364 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | 369 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; |
365 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | 370 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; |
371 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; | ||
366 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | 372 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; |
367 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | 373 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; |
368 | char padding[192]; | 374 | char padding[192]; |
@@ -412,6 +418,15 @@ struct tegra_vgpu_ce2_nonstall_intr_info { | |||
412 | }; | 418 | }; |
413 | 419 | ||
414 | enum { | 420 | enum { |
421 | TEGRA_VGPU_FECS_TRACE_DATA_UPDATE = 0 | ||
422 | }; | ||
423 | |||
424 | struct tegra_vgpu_fecs_trace_event_info { | ||
425 | u32 type; | ||
426 | }; | ||
427 | |||
428 | enum { | ||
429 | |||
415 | TEGRA_VGPU_INTR_GR = 0, | 430 | TEGRA_VGPU_INTR_GR = 0, |
416 | TEGRA_VGPU_INTR_FIFO, | 431 | TEGRA_VGPU_INTR_FIFO, |
417 | TEGRA_VGPU_INTR_CE2, | 432 | TEGRA_VGPU_INTR_CE2, |
@@ -422,7 +437,8 @@ enum { | |||
422 | 437 | ||
423 | enum { | 438 | enum { |
424 | TEGRA_VGPU_EVENT_INTR = 0, | 439 | TEGRA_VGPU_EVENT_INTR = 0, |
425 | TEGRA_VGPU_EVENT_ABORT | 440 | TEGRA_VGPU_EVENT_ABORT, |
441 | TEGRA_VGPU_EVENT_FECS_TRACE | ||
426 | }; | 442 | }; |
427 | 443 | ||
428 | struct tegra_vgpu_intr_msg { | 444 | struct tegra_vgpu_intr_msg { |
@@ -434,6 +450,7 @@ struct tegra_vgpu_intr_msg { | |||
434 | struct tegra_vgpu_fifo_intr_info fifo_intr; | 450 | struct tegra_vgpu_fifo_intr_info fifo_intr; |
435 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; | 451 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; |
436 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | 452 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; |
453 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; | ||
437 | char padding[32]; | 454 | char padding[32]; |
438 | } info; | 455 | } info; |
439 | }; | 456 | }; |