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Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 692 |
1 files changed, 692 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h new file mode 100644 index 00000000..bfa5862b --- /dev/null +++ b/include/linux/tegra_vgpu.h | |||
@@ -0,0 +1,692 @@ | |||
1 | /* | ||
2 | * Tegra GPU Virtualization Interfaces to Server | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef __TEGRA_VGPU_H | ||
20 | #define __TEGRA_VGPU_H | ||
21 | |||
22 | #include <nvgpu/types.h> | ||
23 | |||
24 | #ifdef CONFIG_TEGRA_19x_GPU | ||
25 | #include <linux/tegra_vgpu_t19x.h> | ||
26 | #endif | ||
27 | |||
28 | enum { | ||
29 | TEGRA_VGPU_MODULE_GPU = 0, | ||
30 | }; | ||
31 | |||
32 | enum { | ||
33 | /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list, | ||
34 | * in tegra_vhost.h | ||
35 | */ | ||
36 | TEGRA_VGPU_QUEUE_CMD = 3, | ||
37 | TEGRA_VGPU_QUEUE_INTR | ||
38 | }; | ||
39 | |||
40 | enum { | ||
41 | TEGRA_VGPU_CMD_CONNECT = 0, | ||
42 | TEGRA_VGPU_CMD_DISCONNECT = 1, | ||
43 | TEGRA_VGPU_CMD_ABORT = 2, | ||
44 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3, | ||
45 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4, | ||
46 | TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5, | ||
47 | TEGRA_VGPU_CMD_MAP_BAR1 = 6, | ||
48 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, | ||
49 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, | ||
50 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, | ||
51 | TEGRA_VGPU_CMD_AS_MAP = 10, | ||
52 | TEGRA_VGPU_CMD_AS_UNMAP = 11, | ||
53 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, | ||
54 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, | ||
55 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, | ||
56 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16, | ||
57 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17, | ||
58 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20, | ||
59 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21, | ||
60 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22, | ||
61 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23, | ||
62 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24, | ||
63 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25, | ||
64 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26, | ||
65 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27, | ||
66 | TEGRA_VGPU_CMD_CACHE_MAINT = 28, | ||
67 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29, | ||
68 | TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30, | ||
69 | TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31, | ||
70 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32, | ||
71 | TEGRA_VGPU_CMD_AS_MAP_EX = 33, | ||
72 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34, | ||
73 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35, | ||
74 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36, | ||
75 | TEGRA_VGPU_CMD_REG_OPS = 37, | ||
76 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38, | ||
77 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39, | ||
78 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40, | ||
79 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41, | ||
80 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42, | ||
81 | TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43, | ||
82 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44, | ||
83 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45, | ||
84 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46, | ||
85 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47, | ||
86 | TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48, | ||
87 | TEGRA_VGPU_CMD_GR_CTX_FREE = 49, | ||
88 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX =50, | ||
89 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51, | ||
90 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52, | ||
91 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53, | ||
92 | TEGRA_VGPU_CMD_TSG_PREEMPT = 54, | ||
93 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55, | ||
94 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56, | ||
95 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, | ||
96 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, | ||
97 | TEGRA_VGPU_CMD_READ_PTIMER = 59, | ||
98 | TEGRA_VGPU_CMD_SET_POWERGATE = 60, | ||
99 | TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, | ||
100 | TEGRA_VGPU_CMD_GET_CONSTANTS = 62, | ||
101 | TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, | ||
102 | TEGRA_VGPU_CMD_TSG_OPEN = 64, | ||
103 | TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, | ||
104 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, | ||
105 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, | ||
106 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, | ||
107 | TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69, | ||
108 | TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70, | ||
109 | TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71, | ||
110 | TEGRA_VGPU_CMD_PROF_MGT = 72, | ||
111 | TEGRA_VGPU_CMD_PERFBUF_MGT = 73, | ||
112 | TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, | ||
113 | }; | ||
114 | |||
115 | struct tegra_vgpu_connect_params { | ||
116 | u32 module; | ||
117 | u64 handle; | ||
118 | }; | ||
119 | |||
120 | struct tegra_vgpu_channel_hwctx_params { | ||
121 | u32 id; | ||
122 | u64 pid; | ||
123 | u64 handle; | ||
124 | }; | ||
125 | |||
126 | struct tegra_vgpu_attrib_params { | ||
127 | u32 attrib; | ||
128 | u32 value; | ||
129 | }; | ||
130 | |||
131 | struct tegra_vgpu_as_share_params { | ||
132 | u64 size; | ||
133 | u64 handle; | ||
134 | u32 big_page_size; | ||
135 | }; | ||
136 | |||
137 | struct tegra_vgpu_as_bind_share_params { | ||
138 | u64 as_handle; | ||
139 | u64 chan_handle; | ||
140 | }; | ||
141 | |||
142 | enum { | ||
143 | TEGRA_VGPU_MAP_PROT_NONE = 0, | ||
144 | TEGRA_VGPU_MAP_PROT_READ_ONLY, | ||
145 | TEGRA_VGPU_MAP_PROT_WRITE_ONLY | ||
146 | }; | ||
147 | |||
148 | struct tegra_vgpu_as_map_params { | ||
149 | u64 handle; | ||
150 | u64 addr; | ||
151 | u64 gpu_va; | ||
152 | u64 size; | ||
153 | u8 pgsz_idx; | ||
154 | u8 iova; | ||
155 | u8 kind; | ||
156 | u8 cacheable; | ||
157 | u8 clear_ctags; | ||
158 | u8 prot; | ||
159 | u32 ctag_offset; | ||
160 | }; | ||
161 | |||
162 | struct tegra_vgpu_as_map_ex_params { | ||
163 | u64 handle; | ||
164 | u64 gpu_va; | ||
165 | u64 size; | ||
166 | u32 mem_desc_count; | ||
167 | u8 pgsz_idx; | ||
168 | u8 iova; | ||
169 | u8 kind; | ||
170 | u8 cacheable; | ||
171 | u8 clear_ctags; | ||
172 | u8 prot; | ||
173 | u32 ctag_offset; | ||
174 | }; | ||
175 | |||
176 | struct tegra_vgpu_mem_desc { | ||
177 | u64 addr; | ||
178 | u64 length; | ||
179 | }; | ||
180 | |||
181 | struct tegra_vgpu_channel_config_params { | ||
182 | u64 handle; | ||
183 | }; | ||
184 | |||
185 | struct tegra_vgpu_ramfc_params { | ||
186 | u64 handle; | ||
187 | u64 gpfifo_va; | ||
188 | u32 num_entries; | ||
189 | u64 userd_addr; | ||
190 | u8 iova; | ||
191 | }; | ||
192 | |||
193 | struct tegra_vgpu_ch_ctx_params { | ||
194 | u64 handle; | ||
195 | u64 gr_ctx_va; | ||
196 | u64 patch_ctx_va; | ||
197 | u64 cb_va; | ||
198 | u64 attr_va; | ||
199 | u64 page_pool_va; | ||
200 | u64 priv_access_map_va; | ||
201 | u32 class_num; | ||
202 | }; | ||
203 | |||
204 | struct tegra_vgpu_zcull_bind_params { | ||
205 | u64 handle; | ||
206 | u64 zcull_va; | ||
207 | u32 mode; | ||
208 | }; | ||
209 | |||
210 | enum { | ||
211 | TEGRA_VGPU_L2_MAINT_FLUSH = 0, | ||
212 | TEGRA_VGPU_L2_MAINT_INV, | ||
213 | TEGRA_VGPU_L2_MAINT_FLUSH_INV, | ||
214 | TEGRA_VGPU_FB_FLUSH | ||
215 | }; | ||
216 | |||
217 | struct tegra_vgpu_cache_maint_params { | ||
218 | u8 op; | ||
219 | }; | ||
220 | |||
221 | struct tegra_vgpu_runlist_params { | ||
222 | u8 runlist_id; | ||
223 | u32 num_entries; | ||
224 | }; | ||
225 | |||
226 | struct tegra_vgpu_golden_ctx_params { | ||
227 | u32 size; | ||
228 | }; | ||
229 | |||
230 | struct tegra_vgpu_zcull_info_params { | ||
231 | u32 width_align_pixels; | ||
232 | u32 height_align_pixels; | ||
233 | u32 pixel_squares_by_aliquots; | ||
234 | u32 aliquot_total; | ||
235 | u32 region_byte_multiplier; | ||
236 | u32 region_header_size; | ||
237 | u32 subregion_header_size; | ||
238 | u32 subregion_width_align_pixels; | ||
239 | u32 subregion_height_align_pixels; | ||
240 | u32 subregion_count; | ||
241 | }; | ||
242 | |||
243 | #define TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE 4 | ||
244 | #define TEGRA_VGPU_ZBC_TYPE_INVALID 0 | ||
245 | #define TEGRA_VGPU_ZBC_TYPE_COLOR 1 | ||
246 | #define TEGRA_VGPU_ZBC_TYPE_DEPTH 2 | ||
247 | |||
248 | struct tegra_vgpu_zbc_set_table_params { | ||
249 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
250 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
251 | u32 depth; | ||
252 | u32 format; | ||
253 | u32 type; /* color or depth */ | ||
254 | }; | ||
255 | |||
256 | struct tegra_vgpu_zbc_query_table_params { | ||
257 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
258 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
259 | u32 depth; | ||
260 | u32 ref_cnt; | ||
261 | u32 format; | ||
262 | u32 type; /* color or depth */ | ||
263 | u32 index_size; /* [out] size, [in] index */ | ||
264 | }; | ||
265 | |||
266 | enum { | ||
267 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN, | ||
268 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL, | ||
269 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL, | ||
270 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB, | ||
271 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST | ||
272 | }; | ||
273 | |||
274 | enum { | ||
275 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI, | ||
276 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP, | ||
277 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA, | ||
278 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP, | ||
279 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST | ||
280 | }; | ||
281 | |||
282 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { | ||
283 | u64 handle; /* deprecated */ | ||
284 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
285 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
286 | u32 mode; | ||
287 | u64 gr_ctx_handle; | ||
288 | }; | ||
289 | |||
290 | struct tegra_vgpu_mmu_debug_mode { | ||
291 | u32 enable; | ||
292 | }; | ||
293 | |||
294 | struct tegra_vgpu_sm_debug_mode { | ||
295 | u64 handle; | ||
296 | u64 sms; | ||
297 | u32 enable; | ||
298 | }; | ||
299 | |||
300 | struct tegra_vgpu_reg_op { | ||
301 | u8 op; | ||
302 | u8 type; | ||
303 | u8 status; | ||
304 | u8 quad; | ||
305 | u32 group_mask; | ||
306 | u32 sub_group_mask; | ||
307 | u32 offset; | ||
308 | u32 value_lo; | ||
309 | u32 value_hi; | ||
310 | u32 and_n_mask_lo; | ||
311 | u32 and_n_mask_hi; | ||
312 | }; | ||
313 | |||
314 | struct tegra_vgpu_reg_ops_params { | ||
315 | u64 handle; | ||
316 | u64 num_ops; | ||
317 | u32 is_profiler; | ||
318 | }; | ||
319 | |||
320 | struct tegra_vgpu_channel_priority_params { | ||
321 | u64 handle; | ||
322 | u32 priority; | ||
323 | }; | ||
324 | |||
325 | /* level follows nvgpu.h definitions */ | ||
326 | struct tegra_vgpu_channel_runlist_interleave_params { | ||
327 | u64 handle; | ||
328 | u32 level; | ||
329 | }; | ||
330 | |||
331 | struct tegra_vgpu_channel_timeslice_params { | ||
332 | u64 handle; | ||
333 | u32 timeslice_us; | ||
334 | }; | ||
335 | |||
336 | #define TEGRA_VGPU_FECS_TRACE_FILTER_SIZE 256 | ||
337 | struct tegra_vgpu_fecs_trace_filter { | ||
338 | u64 tag_bits[(TEGRA_VGPU_FECS_TRACE_FILTER_SIZE + 63) / 64]; | ||
339 | }; | ||
340 | |||
341 | enum { | ||
342 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, | ||
343 | TEGRA_VGPU_CTXSW_MODE_CTXSW, | ||
344 | }; | ||
345 | |||
346 | struct tegra_vgpu_channel_set_ctxsw_mode { | ||
347 | u64 handle; | ||
348 | u64 gpu_va; | ||
349 | u32 mode; | ||
350 | }; | ||
351 | |||
352 | struct tegra_vgpu_channel_free_hwpm_ctx { | ||
353 | u64 handle; | ||
354 | }; | ||
355 | |||
356 | struct tegra_vgpu_gr_ctx_params { | ||
357 | u64 gr_ctx_handle; | ||
358 | u64 as_handle; | ||
359 | u64 gr_ctx_va; | ||
360 | u32 class_num; | ||
361 | }; | ||
362 | |||
363 | struct tegra_vgpu_channel_bind_gr_ctx_params { | ||
364 | u64 ch_handle; | ||
365 | u64 gr_ctx_handle; | ||
366 | }; | ||
367 | |||
368 | struct tegra_vgpu_tsg_bind_gr_ctx_params { | ||
369 | u32 tsg_id; | ||
370 | u64 gr_ctx_handle; | ||
371 | }; | ||
372 | |||
373 | struct tegra_vgpu_tsg_bind_unbind_channel_params { | ||
374 | u32 tsg_id; | ||
375 | u64 ch_handle; | ||
376 | }; | ||
377 | |||
378 | struct tegra_vgpu_tsg_preempt_params { | ||
379 | u32 tsg_id; | ||
380 | }; | ||
381 | |||
382 | struct tegra_vgpu_tsg_timeslice_params { | ||
383 | u32 tsg_id; | ||
384 | u32 timeslice_us; | ||
385 | }; | ||
386 | |||
387 | struct tegra_vgpu_tsg_open_params { | ||
388 | u32 tsg_id; | ||
389 | }; | ||
390 | |||
391 | /* level follows nvgpu.h definitions */ | ||
392 | struct tegra_vgpu_tsg_runlist_interleave_params { | ||
393 | u32 tsg_id; | ||
394 | u32 level; | ||
395 | }; | ||
396 | |||
397 | struct tegra_vgpu_read_ptimer_params { | ||
398 | u64 time; | ||
399 | }; | ||
400 | |||
401 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT 16 | ||
402 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC 1 | ||
403 | struct tegra_vgpu_get_timestamps_zipper_params { | ||
404 | /* timestamp pairs */ | ||
405 | struct { | ||
406 | /* gpu timestamp value */ | ||
407 | u64 cpu_timestamp; | ||
408 | /* raw GPU counter (PTIMER) value */ | ||
409 | u64 gpu_timestamp; | ||
410 | } samples[TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT]; | ||
411 | /* number of pairs to read */ | ||
412 | u32 count; | ||
413 | /* cpu clock source id */ | ||
414 | u32 source_id; | ||
415 | }; | ||
416 | |||
417 | struct tegra_vgpu_set_powergate_params { | ||
418 | u32 mode; | ||
419 | }; | ||
420 | |||
421 | struct tegra_vgpu_gpu_clk_rate_params { | ||
422 | u32 rate; /* in kHz */ | ||
423 | }; | ||
424 | |||
425 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | ||
426 | #define TEGRA_VGPU_MAX_ENGINES 4 | ||
427 | struct tegra_vgpu_engines_info { | ||
428 | u32 num_engines; | ||
429 | struct engineinfo { | ||
430 | u32 engine_id; | ||
431 | u32 intr_mask; | ||
432 | u32 reset_mask; | ||
433 | u32 runlist_id; | ||
434 | u32 pbdma_id; | ||
435 | u32 inst_id; | ||
436 | u32 pri_base; | ||
437 | u32 engine_enum; | ||
438 | u32 fault_id; | ||
439 | } info[TEGRA_VGPU_MAX_ENGINES]; | ||
440 | }; | ||
441 | |||
442 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 | ||
443 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 | ||
444 | |||
445 | struct tegra_vgpu_constants_params { | ||
446 | u32 arch; | ||
447 | u32 impl; | ||
448 | u32 rev; | ||
449 | u32 max_freq; | ||
450 | u32 num_channels; | ||
451 | u32 golden_ctx_size; | ||
452 | u32 zcull_ctx_size; | ||
453 | u32 l2_size; | ||
454 | u32 ltc_count; | ||
455 | u32 cacheline_size; | ||
456 | u32 slices_per_ltc; | ||
457 | u32 comptags_per_cacheline; | ||
458 | u32 comptag_lines; | ||
459 | u32 sm_arch_sm_version; | ||
460 | u32 sm_arch_spa_version; | ||
461 | u32 sm_arch_warp_count; | ||
462 | u32 max_gpc_count; | ||
463 | u32 gpc_count; | ||
464 | u32 max_tpc_per_gpc_count; | ||
465 | u32 num_fbps; | ||
466 | u32 fbp_en_mask; | ||
467 | u32 ltc_per_fbp; | ||
468 | u32 max_lts_per_ltc; | ||
469 | u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
470 | /* mask bits should be equal or larger than | ||
471 | * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC | ||
472 | */ | ||
473 | u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
474 | u32 hwpm_ctx_size; | ||
475 | u8 force_preempt_mode; | ||
476 | u32 default_timeslice_us; | ||
477 | u32 preempt_ctx_size; | ||
478 | u32 channel_base; | ||
479 | struct tegra_vgpu_engines_info engines_info; | ||
480 | u32 num_pce; | ||
481 | }; | ||
482 | |||
483 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | ||
484 | u64 handle; | ||
485 | u32 perfmon_start; | ||
486 | u32 perfmon_count; | ||
487 | u32 buf_info; /* client->srvr: get ptr; srvr->client: num pending */ | ||
488 | u8 subcmd; | ||
489 | u8 hw_overflow; | ||
490 | }; | ||
491 | |||
492 | struct tegra_vgpu_gpu_load_params { | ||
493 | u32 load; | ||
494 | }; | ||
495 | |||
496 | struct tegra_vgpu_suspend_resume_contexts { | ||
497 | u32 num_channels; | ||
498 | u16 resident_chid; | ||
499 | }; | ||
500 | |||
501 | struct tegra_vgpu_clear_sm_error_state { | ||
502 | u64 handle; | ||
503 | u32 sm_id; | ||
504 | }; | ||
505 | |||
506 | enum { | ||
507 | TEGRA_VGPU_PROF_GET_GLOBAL = 0, | ||
508 | TEGRA_VGPU_PROF_GET_CONTEXT, | ||
509 | TEGRA_VGPU_PROF_RELEASE | ||
510 | }; | ||
511 | |||
512 | struct tegra_vgpu_prof_mgt_params { | ||
513 | u32 mode; | ||
514 | }; | ||
515 | |||
516 | struct tegra_vgpu_perfbuf_mgt_params { | ||
517 | u64 vm_handle; | ||
518 | u64 offset; | ||
519 | u32 size; | ||
520 | }; | ||
521 | |||
522 | #define TEGRA_VGPU_GPU_FREQ_TABLE_SIZE 25 | ||
523 | |||
524 | struct tegra_vgpu_get_gpu_freq_table_params { | ||
525 | u32 num_freqs; | ||
526 | u32 freqs[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; /* in kHz */ | ||
527 | }; | ||
528 | |||
529 | struct tegra_vgpu_cmd_msg { | ||
530 | u32 cmd; | ||
531 | int ret; | ||
532 | u64 handle; | ||
533 | union { | ||
534 | struct tegra_vgpu_connect_params connect; | ||
535 | struct tegra_vgpu_channel_hwctx_params channel_hwctx; | ||
536 | struct tegra_vgpu_attrib_params attrib; | ||
537 | struct tegra_vgpu_as_share_params as_share; | ||
538 | struct tegra_vgpu_as_bind_share_params as_bind_share; | ||
539 | struct tegra_vgpu_as_map_params as_map; | ||
540 | struct tegra_vgpu_as_map_ex_params as_map_ex; | ||
541 | struct tegra_vgpu_channel_config_params channel_config; | ||
542 | struct tegra_vgpu_ramfc_params ramfc; | ||
543 | struct tegra_vgpu_ch_ctx_params ch_ctx; | ||
544 | struct tegra_vgpu_zcull_bind_params zcull_bind; | ||
545 | struct tegra_vgpu_cache_maint_params cache_maint; | ||
546 | struct tegra_vgpu_runlist_params runlist; | ||
547 | struct tegra_vgpu_golden_ctx_params golden_ctx; | ||
548 | struct tegra_vgpu_zcull_info_params zcull_info; | ||
549 | struct tegra_vgpu_zbc_set_table_params zbc_set_table; | ||
550 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; | ||
551 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | ||
552 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | ||
553 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | ||
554 | struct tegra_vgpu_reg_ops_params reg_ops; | ||
555 | struct tegra_vgpu_channel_priority_params channel_priority; | ||
556 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | ||
557 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | ||
558 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; | ||
559 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | ||
560 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | ||
561 | struct tegra_vgpu_gr_ctx_params gr_ctx; | ||
562 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | ||
563 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | ||
564 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | ||
565 | struct tegra_vgpu_tsg_open_params tsg_open; | ||
566 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | ||
567 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | ||
568 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | ||
569 | struct tegra_vgpu_read_ptimer_params read_ptimer; | ||
570 | struct tegra_vgpu_set_powergate_params set_powergate; | ||
571 | struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; | ||
572 | struct tegra_vgpu_constants_params constants; | ||
573 | struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot; | ||
574 | struct tegra_vgpu_gpu_load_params gpu_load; | ||
575 | struct tegra_vgpu_suspend_resume_contexts suspend_contexts; | ||
576 | struct tegra_vgpu_suspend_resume_contexts resume_contexts; | ||
577 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; | ||
578 | struct tegra_vgpu_prof_mgt_params prof_management; | ||
579 | struct tegra_vgpu_perfbuf_mgt_params perfbuf_management; | ||
580 | struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; | ||
581 | struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table; | ||
582 | #ifdef CONFIG_TEGRA_19x_GPU | ||
583 | union tegra_vgpu_t19x_params t19x; | ||
584 | #endif | ||
585 | char padding[192]; | ||
586 | } params; | ||
587 | }; | ||
588 | |||
589 | enum { | ||
590 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, | ||
591 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1, | ||
592 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2, | ||
593 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3, | ||
594 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4, | ||
595 | TEGRA_VGPU_GR_INTR_FECS_ERROR = 5, | ||
596 | TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6, | ||
597 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7, | ||
598 | TEGRA_VGPU_GR_INTR_EXCEPTION = 8, | ||
599 | TEGRA_VGPU_GR_INTR_SEMAPHORE = 9, | ||
600 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, | ||
601 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, | ||
602 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, | ||
603 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13, | ||
604 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14, | ||
605 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15, | ||
606 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, | ||
607 | }; | ||
608 | |||
609 | struct tegra_vgpu_gr_intr_info { | ||
610 | u32 type; | ||
611 | u32 chid; | ||
612 | }; | ||
613 | |||
614 | struct tegra_vgpu_gr_nonstall_intr_info { | ||
615 | u32 type; | ||
616 | }; | ||
617 | |||
618 | struct tegra_vgpu_fifo_intr_info { | ||
619 | u32 type; | ||
620 | u32 chid; | ||
621 | }; | ||
622 | |||
623 | struct tegra_vgpu_fifo_nonstall_intr_info { | ||
624 | u32 type; | ||
625 | }; | ||
626 | |||
627 | struct tegra_vgpu_ce2_nonstall_intr_info { | ||
628 | u32 type; | ||
629 | }; | ||
630 | |||
631 | enum { | ||
632 | TEGRA_VGPU_FECS_TRACE_DATA_UPDATE = 0 | ||
633 | }; | ||
634 | |||
635 | struct tegra_vgpu_fecs_trace_event_info { | ||
636 | u32 type; | ||
637 | }; | ||
638 | |||
639 | struct tegra_vgpu_channel_event_info { | ||
640 | u32 event_id; | ||
641 | u32 is_tsg; | ||
642 | u32 id; /* channel id or tsg id */ | ||
643 | }; | ||
644 | |||
645 | struct tegra_vgpu_sm_esr_info { | ||
646 | u32 sm_id; | ||
647 | u32 hww_global_esr; | ||
648 | u32 hww_warp_esr; | ||
649 | u64 hww_warp_esr_pc; | ||
650 | u32 hww_global_esr_report_mask; | ||
651 | u32 hww_warp_esr_report_mask; | ||
652 | }; | ||
653 | |||
654 | enum { | ||
655 | |||
656 | TEGRA_VGPU_INTR_GR = 0, | ||
657 | TEGRA_VGPU_INTR_FIFO = 1, | ||
658 | TEGRA_VGPU_INTR_CE2 = 2, | ||
659 | TEGRA_VGPU_NONSTALL_INTR_GR = 3, | ||
660 | TEGRA_VGPU_NONSTALL_INTR_FIFO = 4, | ||
661 | TEGRA_VGPU_NONSTALL_INTR_CE2 = 5, | ||
662 | }; | ||
663 | |||
664 | enum { | ||
665 | TEGRA_VGPU_EVENT_INTR = 0, | ||
666 | TEGRA_VGPU_EVENT_ABORT = 1, | ||
667 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, | ||
668 | TEGRA_VGPU_EVENT_CHANNEL = 3, | ||
669 | TEGRA_VGPU_EVENT_SM_ESR = 4, | ||
670 | }; | ||
671 | |||
672 | struct tegra_vgpu_intr_msg { | ||
673 | unsigned int event; | ||
674 | u32 unit; | ||
675 | union { | ||
676 | struct tegra_vgpu_gr_intr_info gr_intr; | ||
677 | struct tegra_vgpu_gr_nonstall_intr_info gr_nonstall_intr; | ||
678 | struct tegra_vgpu_fifo_intr_info fifo_intr; | ||
679 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; | ||
680 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | ||
681 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; | ||
682 | struct tegra_vgpu_channel_event_info channel_event; | ||
683 | struct tegra_vgpu_sm_esr_info sm_esr; | ||
684 | char padding[32]; | ||
685 | } info; | ||
686 | }; | ||
687 | |||
688 | #define TEGRA_VGPU_QUEUE_SIZES \ | ||
689 | 512, \ | ||
690 | sizeof(struct tegra_vgpu_intr_msg) | ||
691 | |||
692 | #endif | ||